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lyqin@cti.com.cn (Leon Qin) writes: > news:<usne2hwwa.fsf@trw.com>... > I need move data from one port to another port which hao a diffrent > clock. Both clock are diffrent freq( both about 27MHz) and phase. > I found the RDempty delay has more 3 period (about 8). In that case I'm stumped! According to the Max plus 2 helpfile, rdempty etc. should be delayed by 1 cycle, and there are 3 cycles of synchronisation between the clock domains. Those are the defaults, you could tweak them to see what happens... Are you using schematics, VHDL or Verilog for this design? Cheers, Martin -- martin.j.thompson@trw.com TRW Automotive Technical Centre, Solihull, UKArticle: 34751
"Tony Proudfoot" <tonyp@vl.com.au> writes: > Does anyone else have practical experience using an LPM_FIFO_DC in an > Altera 10k130e device ? I have measured some very strange behaviour > with this fifo and I can't figure it out. I am using two seperate > clock domains to write and read the fifo. The behaviour goes like > this; Fifo empty flag on the read side is logic 1, thus fifo is empty. > I clock one qword into the fifo, using the wrreq signal on the write. > Some clocks later (~6), the empty flag on the read side goes to logic > 0. I assert rdreq on the read side and the qword emerges from the > fifo. Hurrah. > > Now the bit thats killing me. Everything same as above, except when I > assert rdreq the qword does NOT emerge from the fifo. If I assert > rdreq again, the qword emerges. > So are you saying that sometimes it works and sometimes it doesn't, or that it always takes two rdreqs to get the word out. Or is it just the first word? I recall seeing something strange happening once with a non-DC LPM_FIFO in simulation, needing an extra cycle of rdreq high after the empty flag goes low , so all my data seemed to have one cycle extra latency... is that what you're seeing? I can't help much as this was quite a long time ago and I just put it down to my inexperience - I'll see if I can dig it out later on... > > Does anyone know why this is happening ? Are there known 'gotchas' > interfacing to these fifos ? > > Any help, hints or tips are much appreciated, regards Tony. Sorry not to be more help! Cheers, Martin -- martin.j.thompson@trw.com TRW Automotive Technical Centre, Solihull, UKArticle: 34752
Hi, Was wondering if anyone can spot a problem with the following. I am using a 32MHz clock on a Spartan II. I then output the same clock signal, and use it to drive an ADC. The outputs of the ADC are latched by a parallel register, and outputted again. Comparing the output of my register and the inputs to the register on a scope, it seems that the register is missing a number of bits, although this may be invalid data from the ADC which isn't being clocked by the register. Unfortunately, I would be able to see if I could have a third scope channel on the same screen to look at the clock signal, but this isn't possible. Does anyone have an idea as to whether I am missing bits or not? Am I using the correct clock input buffers (ibufg followed by a bufg)? Regards AdrianArticle: 34753
Egbert Molenkamp has posted an elegant solution to this problem in the
comp.lang.vhdl newsgroup. Below is his source code:
Thanks to all for the help.
Michael
entity scheduler is
generic (line_width : natural := 8);
port (current : natural range 0 to line_width-1;
line : bit_vector(0 to line_width-1);
nxt : out natural range 0 to line_width-1);
end scheduler;
architecture behaviour of scheduler is
begin
process(current,line)
variable sel : natural RANGE 0 TO line_width-1;
constant nul : bit_vector(0 to line_width-1) := (others => '0');
begin
assert nul/=line report "no free channels available" severity note;
for i in line'range loop
sel := (current + 1 + i) mod line_width;
exit when line(sel)='1';
end loop;
nxt <= sel;
end process;
end behaviour;
Article: 34754Hi, Can anyone guide me in selecting a FPGA board meeting the following requirements? 1)We require to operate at 60MHz and need a PCI interface on 1 side (we have our own PCI core) 2)I think the size of our design is such that it will fit into an APEX1000 or a Xilinx VirtexE XCV2000 3)The cost of the board along with the FPGA should be < 2000 US $ 4)We dont mind going for a 2-FPGA solution (i.e 2 FPGAs on 1 board) Waiting in anticipation -AmeyArticle: 34755
Michael Boehnel <boehnel@iti.tu-graz.ac.at> wrote: > I think your solution doesn't take the Marker-array in account. Marker > isn't fixed! It changes during operation. And so the count sequence > changes dynamically. Oh I see. Good luck then. You can still do it with a for loop I think. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 34756
You can use either the Xilinx foundation 3.0 or Xilinx ISE 3.0 Both can all you need. Terrence "Noelia" <paulanm@usc.es> ????? news:ee723a7.-1@WebX.sUN8CHnE... > Hello, > > I have my VHDL code and I want to > map it to a FPGA. I have used the Synopsys tools to compile, to > simulate and to synthetize my design. However, I want > to know if I can do all the design > flow using the Xilinx tools. That is, a Xilinx compiler, a Xilinx simulator, a Xilinx synthetizer. > If it is possible, which tools I need? > > Thanks and kind regards.Article: 34757
Ray, I agree. In future we are thinking of having a secure website URL so that 'real' customers can have access to the Errata. We really did try to make sure the part and the paper went together, but even so, we have heard back that this was not always the case. We don't relly want to air all of the dirty laundry in the public square (or even the clean laundry). But we do want open and frank conversation with customers so that we both benefit. But I am with you: I used to be a customer, and although it has been three years and one month, I at least can still understand the need, and the frustration of having and not having the information when it is needed. As the first customer still (I manage the FPGA Lab which gets the first silicon before the tools have been debugged, and before the data sheets are 'fixed' and when the speeds files are still 'pretend'), I am very sensitive to not knowing. By the way, the 2V3000 does not have the SRL16 problem, nor does it have the variable phase shift problem. Both were fixed for the 2V3000 ES parts. Andreas: if you do not have the errata, I will email it to you. Please email me at austin@xilinx.com. Austin Ray Andraka wrote: > Austin, > > That information should be made easily available to people before they get the > chips in their hands. Some of the broken things are show stoppers if you need > them in your design (eg. SRL16's). The time to find that out is before you do > your concept design, not when you receive the errata sheet with your parts > order. > > Austin Lesea wrote: > > > Andreas, > > > > Please contact a Xilinx FAE, or a Xilinx sales office to obtain the ES > > Errata Sheet. This document contains detailed information about any > > discrepancies that may exist in the ES material from the data sheet. > > > > This information was shipped with every ES shipment, but it has come to our > > attention that sometimes this information was not passed along with the > > parts. > > > > Austin Lesea > > FPGA Lab Manager > > FPG > > ICDES > > Xilinx > > > > Andreas Kugel wrote: > > > > > I will get our new Virtex-2 board (supports 64 Bit PCI with a PLX bridge > > > - sorry, no Xilinx PC- ) end of september. Devices I have are > > > XC2V3000-4BF957CES (engineering samples). Is anyone aware of particular > > > features of the ES devices (e.g. something doesn't work ...) > > > > > > Thanks, > > > Andreas > > > > > > -- > > > Andreas Kugel - University of Mannheim - Dept. of Computer Science V > > > FPGA-Processor Group > > > B6,23-29/A - 68131 Mannheim - Germany > > > Phone:+(49)621 181 2632 - Fax:+(49)621 181 3580 > > > mailto:kugel@ti.uni-mannheim.de > > > http://www-li5.ti.uni-mannheim.de/fpga/index.shtml > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.comArticle: 34758
Could it be that rdreq was asserted too early in relation to the empty flag going low? Is rdreq synchronous to the read clock and is it asserted the cycle after the empty flag going low? The on-line help on LPM_FIFO_DC says: "Reading is disabled if rdempty = 1." "rdempty If asserted, indicates that the lpm_fifo_dc is empty and disables the rdreq port. Synchronized with rdclock." Simulation results are not by chance and I'd say there has to be a difference in the stimuli. The only one I could think of is the rdreq coming too early. Regards Wolfgang "Tony Proudfoot" <tonyp@vl.com.au> schrieb im Newsbeitrag news:3b972491$0$20942$7f31c96c@news01.syd.optusnet.com.au... > Does anyone else have practical experience using an LPM_FIFO_DC in an Altera > 10k130e device ? > I have measured some very strange behaviour with this fifo and I can't > figure it out. > I am using two seperate clock domains to write and read the fifo. > The behaviour goes like this; > Fifo empty flag on the read side is logic 1, thus fifo is empty. > I clock one qword into the fifo, using the wrreq signal on the write. > Some clocks later (~6), the empty flag on the read side goes to logic 0. > I assert rdreq on the read side and the qword emerges from the fifo. Hurrah. > > Now the bit thats killing me. > Everything same as above, except when I assert rdreq the qword does NOT > emerge from the fifo. If I assert rdreq again, the qword emerges. > > > Does anyone know why this is happening ? > Are there known 'gotchas' interfacing to these fifos ? > > Any help, hints or tips are much appreciated, > regards > Tony. > -- > _________________________________ > Tony Proudfoot, tonyp@vl.com.au > Hardware Design Engineer > Virtual Logic Pty Ltd > Ph: +61(0)2 9599 3255 > _________________________________ > > >Article: 34759
Kamran,
Well, at 55C ambient, and 15 watts, if you had 5 C/W with 750 cu ft per minute airflow for the part without a heatsink on the pcb, that is 5*15, or 75 C rise, from 55C,
is 130C die temperature.
Ouch. The absolute maximum rating is 125 C, so it would probably last days, or even weeks. I would be concerned about heat damage to the pcb, and adjacent components.
It certainly wouldn't be meeting the speeds files performance numbers when this hot (probably 20% worse, or ~2 speed grades).
With anything less than 750 cu ft per minute, the device would get too hot, probably melt the solder, and fall off the board.
Heatsinks from:
Aavid Thermal Technologies:
363014
362914
372024
336614
371924
Or:
Chipcoolers:
HTS343
HTS344
HTS345
Would all work to keep you cool enough even in still air to not exceed 108 C die temperature.
Given the price of a 2V6000, the heatsink is spare change. Why would you abuse it so?
Austin
KAMRAN wrote:
> I WOULD LIKE TO ASK YOU THE XC2V6000 chip ( Package code: FF1152) HOW LONG WOULD LAST LONG (BE SAFE) TO OPERATE AT 15W WITOUTH USING HEATSINK AT ROOM TEMP. (55 DEG.)?
> SOME DATA MIGHT HELP:Thermal data and Maximum power dissipation of the selected Device and Package based on Tj-max and Ta-ambient: (Tj = 100 deg C ,Ta = 45 deg C.)
> -------------------------------------------------------------------------------------
> JA(0) = 11.4 C/Watt
> JC = 1.1 C/Watt
> JA(250) = 7.3 C/Watt
> JA(500) = 5.8 C/Watt
> JA(750) = 5.0 C/Watt
> ------------------------------------------------------------------------------------
> POWER 0 LFM = 4.8 Watts
> POWER 250 LFM = 7.5
> POWER 500 LFM = 9.4
>
> THANKING YOU IN ADVANCE,
> KAMRAN
Article: 34760I having great difficulties configurating a spartan XS15 by microprocessor. I'm doing this : - I'm using Webfitter freeware. - The XS15 is hardwired to SERIAL SLAVE MODE 1. Create bit file with following attributes: - Use CCLK as startup clk. - Done should go high after success configuration (4 CCLK's) HAVE I FORGOTTEN ANYTHING? 2. Create MCS file with following att. - Serial HEX file 3. Import the HEX file into memory. - When I dump the memory in a viewer the first bytes look like this: FF FF FF FF 55 99 AA 66 0C 00 01 80 00 00 00 E0 0C 80 06 80 00 00 00 B0 0C 80 04 80 00 01 FC B4 0C 00 03 80 00 00 00 00 0C 00 01 80 00 00 00 90 0C 00 04 80 00 00 00 00 0C 00 01 80 00 00 00 80 0C 00 02 00 0A 00 1A 58 00 48 0C 00 00 00 00 00 wich i think is ok? 4. Then Start configuring. PROGRAM LOW wait PROGRAM HIGH wait for INIT to go HIGH wait 20 us read 1 byte from memory TX byte with LSB FIRST repeat until 0x6088 bytes are transmitted THIS METHODE DOES'NT WORK................. WHY????? Please HelpArticle: 34761
If you look at the bitstream data then the MSB of a byte comes first. You should transmit MSB first, not LSB first. Note: if you ever might want to use slave parallel you will have to convert all bytes Andreas Allan Pedersen schrieb: > I having great difficulties configurating a spartan XS15 by > microprocessor. I'm doing this : > > - I'm using Webfitter freeware. > - The XS15 is hardwired to SERIAL SLAVE MODE > > 1. Create bit file with following attributes: > > - Use CCLK as startup clk. > - Done should go high after success configuration (4 CCLK's) > > HAVE I FORGOTTEN ANYTHING? > > 2. Create MCS file with following att. > > - Serial HEX file > > 3. Import the HEX file into memory. > > - When I dump the memory in a viewer the first bytes look like this: > > FF FF FF FF 55 99 AA 66 0C 00 01 80 00 00 00 E0 > 0C 80 06 80 00 00 00 B0 0C 80 04 80 00 01 FC B4 > 0C 00 03 80 00 00 00 00 0C 00 01 80 00 00 00 90 > 0C 00 04 80 00 00 00 00 0C 00 01 80 00 00 00 80 > 0C 00 02 00 0A 00 1A 58 00 48 0C 00 00 00 00 00 > > wich i think is ok? > > 4. Then Start configuring. > > PROGRAM LOW > wait > PROGRAM HIGH > > wait for INIT to go HIGH > > wait 20 us > > read 1 byte from memory > > TX byte with LSB FIRST > > repeat until 0x6088 bytes are transmitted > > THIS METHODE DOES'NT WORK................. WHY????? > > Please Help -- Andreas Kugel - University of Mannheim - Dept. of Computer Science V FPGA-Processor Group B6,23-29/A - 68131 Mannheim - Germany Phone:+(49)621 181 2632 - Fax:+(49)621 181 3580 mailto:kugel@ti.uni-mannheim.de http://www-li5.ti.uni-mannheim.de/fpga/index.shtmlArticle: 34762
Hi amey hegde schrieb: > Hi, > Can anyone guide me in selecting a FPGA board meeting the following > requirements? > 1)We require to operate at 60MHz and need a PCI interface on 1 side (we > have our own PCI core) > 2)I think the size of our design is such that it will fit into an APEX1000 > or a Xilinx VirtexE XCV2000 Anything else you need ? Memory ? I/O connectors ? > > 3)The cost of the board along with the FPGA should be < 2000 US $ If this is a hard limit you will probably not get a commercial product. > We will have a XC2V3000 board in a few weeks from now (prototype). Let me know if that would be of interest to you. Andreas > > 4)We dont mind going for a 2-FPGA solution (i.e 2 FPGAs on 1 board) > > Waiting in anticipation > -Amey -- Andreas Kugel - University of Mannheim - Dept. of Computer Science V FPGA-Processor Group B6,23-29/A - 68131 Mannheim - Germany Phone:+(49)621 181 2632 - Fax:+(49)621 181 3580 mailto:kugel@ti.uni-mannheim.de http://www-li5.ti.uni-mannheim.de/fpga/index.shtmlArticle: 34763
As I understand it, you have a register between the ADC and the FPGA which is clocked by the ADC clock. This is a fairly common arrangement to get around long settling times in the ADC. I also understand you to mean it is this external register which is getting corrupted. If that is the case, you are either clocking the register during the output transition of the ADC data, or you have a signals integrity problem on your board, probably with the clock. If the first register after the ADC is in the FPGA, then you are likely getting nailed by clock skew. Use the DLL to align the ADC clock and the FPGA's internal clock (see the app note). The FPGA's IOBs on the ADC inputs should be registered too. Check the ADC data sheet carefully, many have a long settling time, which combined with long setup times in the FPGA inputs may spell trouble. At a minimum, (at 35 MHz), you'll need to make sure you do everything you can to minimize the FPGA set-up time. Noddy wrote: > Hi, > > Was wondering if anyone can spot a problem with the following. I am using a > 32MHz clock on a Spartan II. I then output the same clock signal, and use it > to drive an ADC. The outputs of the ADC are latched by a parallel register, > and outputted again. Comparing the output of my register and the inputs to > the register on a scope, it seems that the register is missing a number of > bits, although this may be invalid data from the ADC which isn't being > clocked by the register. Unfortunately, I would be able to see if I could > have a third scope channel on the same screen to look at the clock signal, > but this isn't possible. > > Does anyone have an idea as to whether I am missing bits or not? Am I using > the correct clock input buffers (ibufg followed by a bufg)? > > Regards > Adrian -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 34764
Tony Proudfoot wrote:
>
> Does anyone else have practical experience using an LPM_FIFO_DC in an Altera
> 10k130e device ?
> I have measured some very strange behaviour with this fifo and I can't
> figure it out.
>
> Any help, hints or tips are much appreciated,
Have you looked at the code?
--Mike Treseler
-----------------------------------------------------
-- Version 2.0 (lpm 220) Date 01/04/00
-- 3. LPM_FIFO_DC is rewritten to have correct outputs.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_FIFO_DC is
generic (LPM_WIDTH : positive ;
LPM_WIDTHU : positive := 1;
LPM_NUMWORDS : positive;
LPM_SHOWAHEAD : string := "OFF";
LPM_TYPE : string := "LPM_FIFO_DC";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRCLOCK : in std_logic;
RDCLOCK : in std_logic;
WRREQ : in std_logic;
RDREQ : in std_logic;
ACLR : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
WRUSEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
RDUSEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
WRFULL : out std_logic;
RDFULL : out std_logic;
WREMPTY : out std_logic;
RDEMPTY : out std_logic);
end LPM_FIFO_DC;
architecture LPM_SYN of lpm_fifo_dc is
type lpm_memory is array (lpm_numwords-1 downto 0) of
std_logic_vector(lpm_width-1 downto 0);
signal i_q : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal i_read_and_write : std_logic := '0';
signal i_rdptr, i_wrptr : integer := 0;
signal i_rdempty, i_wrempty : std_logic := '1';
signal i_rdfull, i_wrfull : std_logic := '0';
signal i_rdusedw, i_wrusedw : integer := 0;
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
constant RDPTR_DP : integer := 5;
constant WRPTR_DP : integer := 5;
constant RDUSEDW_DP : integer := 1;
constant WRUSEDW_DP : integer := 1;
constant FULL_RISEEARLY : integer := 2;
type t_rdptrpipe is array (0 to RDPTR_DP) of integer;
type t_wrptrpipe is array (0 to WRPTR_DP) of integer;
type t_rdusedwpipe is array (0 to RDUSEDW_DP) of integer;
type t_wrusedwpipe is array (0 to WRUSEDW_DP) of integer;
begin
process (rdclock, wrclock, aclr, i_read_and_write)
variable mem_data : lpm_memory := (OTHERS => ZEROS);
variable pipe_wrptr : t_rdptrpipe := (OTHERS => 0);
variable pipe_rdptr : t_wrptrpipe := (OTHERS => 0);
variable pipe_rdusedw : t_rdusedwpipe := (OTHERS => 0);
variable pipe_wrusedw : t_wrusedwpipe := (OTHERS => 0);
begin
if (ACLR = '1') then
----- CLEAR ALL VARIABLES -----
i_q <= ZEROS;
i_read_and_write <= '0';
i_rdptr <= 0;
i_wrptr <= 0;
i_rdempty <= '1';
i_wrempty <= '1';
i_rdfull <= '0';
i_wrfull <= '0';
-- i_rdusedw and i_wrusedw are cleard in the pipelines.
if (lpm_showahead = "ON") then
i_q <= mem_data(0);
end if;
elsif (wrclock'event and wrclock = '1') then
----- SET FLAGS -----
if (i_wrusedw >= lpm_numwords-1-FULL_RISEEARLY) then
i_wrfull <= '1';
else
i_wrfull <= '0';
end if;
if (i_wrusedw <= 0 and i_rdptr = i_wrptr) then
i_wrempty <= '1';
end if;
if (wrreq = '1' and i_wrfull = '0' and not wrreq'event) then
----- WRITE DATA -----
mem_data(i_wrptr) := data;
----- SET FLAGS -----
i_wrempty <= '0';
----- INC WRPTR -----
if (i_wrptr >= lpm_numwords-1) then
i_wrptr <= 0;
else
i_wrptr <= i_wrptr + 1;
end if;
end if;
if (rdclock'event and rdclock = '1') then
i_read_and_write <= '1';
end if;
elsif ((rdclock'event and rdclock = '1') or
i_read_and_write = '1') then
i_read_and_write <= '0';
----- SET FLAGS -----
if (i_rdusedw >= lpm_numwords-1-FULL_RISEEARLY) then
i_rdfull <= '1';
else
i_rdfull <= '0';
end if;
if (i_rdptr = i_wrptr) then
i_rdempty <= '1';
elsif (i_rdempty = '1' and i_rdusedw > 0) then
i_rdempty <= '0';
end if;
----- Q SHOWAHEAD -----
if (lpm_showahead = "ON" and i_rdptr /= i_wrptr) then
i_q <= mem_data(i_rdptr);
end if;
if (rdreq = '1' and i_rdempty = '0' and not rdreq'event) then
----- READ DATA -----
i_q <= mem_data(i_rdptr);
if (lpm_showahead = "ON") then
if (i_rdptr = i_wrptr) then
i_q <= ZEROS;
else
if (i_rdptr >= lpm_numwords-1) then
i_q <= mem_data(0);
else
i_q <= mem_data(i_rdptr+1);
end if;
end if;
end if;
----- SET FLAGS -----
if ((i_rdptr = lpm_numwords-1 and i_wrptr = 0) or
i_rdptr+1 = i_wrptr) then
i_rdempty <= '1';
end if;
----- INC RDPTR -----
if (i_rdptr >= lpm_numwords-1) then
i_rdptr <= 0;
else
i_rdptr <= i_rdptr + 1;
end if;
end if;
end if;
----- DELAY WRPTR FOR RDUSEDW -----
pipe_wrptr(RDPTR_DP) := i_wrptr;
if (RDPTR_DP > 0) then
if (ACLR = '1') then
for i in 0 to RDPTR_DP loop
pipe_wrptr(i) := 0;
end loop;
elsif (rdclock'event and rdclock = '1') then
pipe_wrptr(0 to RDPTR_DP-1) := pipe_wrptr(1 to RDPTR_DP);
end if;
end if;
if (pipe_wrptr(0) >= i_rdptr) then
pipe_rdusedw(RDUSEDW_DP) := pipe_wrptr(0) - i_rdptr;
else
pipe_rdusedw(RDUSEDW_DP) := lpm_numwords + pipe_wrptr(0) - i_rdptr;
end if;
----- DELAY RDPTR FOR WRUSEDW -----
pipe_rdptr(WRPTR_DP) := i_rdptr;
if (WRPTR_DP > 0) then
if (ACLR = '1') then
for i in 0 to WRPTR_DP loop
pipe_rdptr(i) := 0;
end loop;
elsif (wrclock'event and wrclock = '1') then
pipe_rdptr(0 to WRPTR_DP-1) := pipe_rdptr(1 to WRPTR_DP);
end if;
end if;
if (i_wrptr >= pipe_rdptr(0)) then
pipe_wrusedw(WRUSEDW_DP) := i_wrptr - pipe_rdptr(0);
else
pipe_wrusedw(WRUSEDW_DP) := lpm_numwords + i_wrptr - pipe_rdptr(0);
end if;
----- DELAY RDUSEDW -----
if (RDUSEDW_DP > 0) then
if (ACLR = '1') then
for i in 0 to RDUSEDW_DP loop
pipe_rdusedw(i) := 0;
end loop;
elsif (rdclock'event and rdclock = '1') then
pipe_rdusedw(0 to RDUSEDW_DP-1) := pipe_rdusedw(1 to RDUSEDW_DP);
end if;
end if;
i_rdusedw <= pipe_rdusedw(0);
----- DELAY WRUSEDW -----
if (WRUSEDW_DP > 0) then
if (ACLR = '1') then
for i in 0 to WRUSEDW_DP loop
pipe_wrusedw(i) := 0;
end loop;
elsif (wrclock'event and wrclock = '1') then
pipe_wrusedw(0 to WRUSEDW_DP-1) := pipe_wrusedw(1 to WRUSEDW_DP);
end if;
end if;
i_wrusedw <= pipe_wrusedw(0);
end process;
----- SET OUTPUTS ------
q <= i_q;
rdempty <= i_rdempty;
wrempty <= i_wrempty;
rdfull <= i_rdfull;
wrfull <= i_wrfull;
rdusedw <= conv_std_logic_vector(i_rdusedw, lpm_widthu);
wrusedw <= conv_std_logic_vector(i_wrusedw, lpm_widthu);
end LPM_SYN;
Article: 34765
The MPGA, an open source design for a 'meta-FPGA' with open
programming specifications, now has public mailing lists and web
forums at SourceForge. If you are interested in this development,
please join the discussion!
See the new SourceForge MPGA project:
http://sourceforge.net/projects/mpga/
or go directly to the mailing lists:
http://sourceforge.net/mail/?group_id=34637
and web forums:
http://sourceforge.net/forum/?group_id=34637
The MPGA home page is still at:
http://ce.et.tudelft.nl/~reinoud/mpga/README.html
See you there!
- Reinoud
(Spam goes to wanabe, mail to wanadoo!)
Article: 34766Thanks for the kind words. The xilinx routing is sort of hierarchical too, but in a different way. Actually it is more a structural difference. The xilinx architecture is a rather uniform sea of fairly simple cells with a set of routing that extends single, hex and long lines (for virtex) in each direction. You get on the long lines directly from the CLB's GRM (this is the routing matrix switch block). The Altera structure is more like a tiled array of PLDs. The LAB has local connections to 8 or 10 LE's which are a lut and flip-flop. These are set up almost like a small pld (but with LUTs instead of an and-or array). Then the LABs connect in a row or mega-lab.... To get from one row to another you have to go on a column route, then to a row route then to the LAB local route then to the LE. The local interconnect in V2 mostly buys you performance when your combinatorial logic between registers is wider than a LUT. For heavily pipelined designs that are careful not to exceed the LUT width, the local interconnect only buys a little, and then mostly after some very careful floorplanning. The key to performance is local interconnect, but the overall performance is usually limited by fanout of control signals going into a carry chain. Peter Ormsby wrote: > \__\/ > > Ray Andraka did a good job describing the differences. One thing I would > like to point out is that the Altera document you're pointing to is six (!) > years old. Like Mr. Andraka points out, newer Altera families have a > heirarchy of interconnect. APEX 20KE devices have LAB interconnects span 10 > logic elements (LUT/FF cells), MegaLAB interconnects span 16 or 24 LABs, and > several other levels of interconnect that are shorter than > all-the-way-across-the-device. To see even a different implementation of > interconnect, take a look at Altera's Mercury devices. In those the I/O > pads are dispersed throughout the die rather than just around the edges, > giving you the ability to use local interconnect on I/O signals, even from > nodes burried in the middle of the device. I would suggest that the Altera > document you point to doesn't mean much with respect to the more current > familes of programmable logic devices. > > BTW, I think that this idea of interconnect hierarchy is applicable to > Xilinx devices too - maybe someone who understands the Virtex II > architecture better that I could address what having more slices per CLB > means with respect to local interconnect within a CLB vs. interconnect > between CLBs. > > -Pete- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 34767
A long time before, I saw a free IP core for ISA. But I can not remember the URL and I don't know the kind of it. You can try to look it up in google On 18 Apr 2001 18:46:23 GMT, ernstegon.NO@SPAM.freeze.com (Ernst Rattenhuber) wrote: >I need some kind of IP module that implements an ISA bus interface. It could be >in the form of a "black box" or in the form of synthesizable VHDL code. I >believe Xilinx used to have something along those lines, but it seems to have >been discontinued. Now they only offer a "PCI Development Kit" for the PCI bus, >and it's rather expensive too (~9000 US dollars). > >My needs are not so great in terms of performance, and I'm not prepared to fork >out that kind of money. So if someone could suggest an ISA solution that could >be purchased for 1000 dollars or less, I'd be grateful. > >I need it for the design of a PC/104 board that is to be the interface between >measurement devices and an embedded PC. The measurement devices use a >proprietary, synchronous serial protocol. I'm planning to implement the whole >thing in a single FPGA, preferably a Spartan-II device. > >TIA, > >Ernst Rattenhuber > > >P.S. Email replies can be sent to the address in my header minus the obvious >spam deterrent parts.Article: 34768
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Michael Boehnel wrote: > > For scheduling I'd like to implement a special counter: > > The counter has an extra input "Marked" of type STD_LOGIC_VECTOR(N-1 > downto 0). The counter jumps to the next value with Marked(i)='1'. E.g.: > Actual Counter=2, Marked(2,3,4,6,7)='0' , Marked(1,5)='1', => Next > actual counter := 5 ... > Wearing my "Murthy was an optimist" hat ... and with experience of how programs can go wrong: What happens if no Marked(i) is non-zero? In the software analogue we would have a rather nasty infinite loop - I would expect something equally unpleasant to occur in the hardware designed to the specification. AndyArticle: 34770
> Unfortunately, I would be able to see if I could >have a third scope channel on the same screen to look at the clock signal, >but this isn't possible. You can often get one-more scope channel by using the external sync. This works quite well if you want to sync on something simple like a clock. Use a probe normally to set things up. Put the second probe on another signal for a double check. Now move the first probe over to the external sync and switch the sync selector to use it. The second signal shouldn't change. As long as you don't need to change the sweep speed or horiz position this works reasonably well. You have to remember what the sync signal looks like. I usually do something simple like put the rising edge of the clock in the middle of the screen because that's easy to remember. -- These are my opinions, not necessarily my employeers. I hate spam.Article: 34771
Andy, I have to say that in the original version Mr Molenkamp had an assert (which is ignored for synthesis) on that case which I have removed. But as this is a for loop I think there should'nt be a problem with exiting. The exit statement is only for an early exit of the loop. MichaelArticle: 34772
Hi, the XCV2000E and the EP20K1000E are about the same size (approx. 38400 logic cells). Pricing for these devices depends on speed grade as well as the package type and for small quantities I found the following: XCV2000E: 2367 - 5572 US $ EP20K1000E: 1150 - 2830 US $ You mentioned 60 MHz and I assume you need PCI @ 33 MHz so the slowest speed grade will probably not be enough. With this device cost just for the FPGA you'll probably not be able to find a PCI board with one of these devices at or below 2000 US $ Regards Wolfgang "amey hegde" <amey@controlnet.co.in> schrieb im Newsbeitrag news:f8b003f9.0109060521.1d448e39@posting.google.com... > Hi, > Can anyone guide me in selecting a FPGA board meeting the following > requirements? > 1)We require to operate at 60MHz and need a PCI interface on 1 side (we > have our own PCI core) > 2)I think the size of our design is such that it will fit into an APEX1000 > or a Xilinx VirtexE XCV2000 > 3)The cost of the board along with the FPGA should be < 2000 US $ > 4)We dont mind going for a 2-FPGA solution (i.e 2 FPGAs on 1 board) > > Waiting in anticipation > -AmeyArticle: 34773
In this case the counter value is freezed. MichaelArticle: 34774
Hi,
I've got a problem. I want to re-write my read register from 'if'-
statements to a 'case' statement (VHDL), but my device doesn't seem to work
anymore when I do so.
I've replaced this:
if RST = '0' and (S_CH_OE ='1' and conv_integer(A_L) = 1) then
D_RD <= D_RX;
elsif RST = '0' and (S_CH_OE ='1' and conv_integer(A_L) = 2) then
D_RD(7 downto 0) <= (RX_RDY, TX_RDY, IRQ_SL, IND, I_IRQ_RX_EN,
I_IRQ_TX_EN, I_IRQ_SL_EN, I_IRQ_IN_EN);
else
D_RD <= (others => 'Z');
end if;
with this:
if S_CH_OE = '1' and RST = '0' then
case (conv_integer(A_L)) is
when 1 => D_RD <= D_RX;
when 2 => D_RD(7 downto 0) <= (RX_RDY, TX_RDY, IRQ_SL, IND,
I_IRQ_RX_EN, I_IRQ_TX_EN, I_IRQ_SL_EN, I_IRQ_IN_EN);
when others => D_RD <= (others => 'Z');
end case;
end if;
In my oppinion this should work...... anybody got any idea on what might be
wrong ??
thanx,
H.
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