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Xilinx has an app-note on a plug and play ISA interface at: http://www.xilinx.com/appnotes/plugplay.pdf It is probably more elaborate than you need, but it will at least give you the worst case. A simple ISA interface takes little more than address decoding qualified by IOCS or MEMCS. There are a number of books like the annabooks ($$) series that detail the ISA interface Ernst Rattenhuber wrote: > > I need some kind of IP module that implements an ISA bus interface. It could be > in the form of a "black box" or in the form of synthesizable VHDL code. I > believe Xilinx used to have something along those lines, but it seems to have > been discontinued. Now they only offer a "PCI Development Kit" for the PCI bus, > and it's rather expensive too (~9000 US dollars). > > My needs are not so great in terms of performance, and I'm not prepared to fork > out that kind of money. So if someone could suggest an ISA solution that could > be purchased for 1000 dollars or less, I'd be grateful. > > I need it for the design of a PC/104 board that is to be the interface between > measurement devices and an embedded PC. The measurement devices use a > proprietary, synchronous serial protocol. I'm planning to implement the whole > thing in a single FPGA, preferably a Spartan-II device. > > TIA, > > Ernst Rattenhuber > > P.S. Email replies can be sent to the address in my header minus the obvious > spam deterrent parts. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30651
Is there any linux shareware out there that will allow me to compile Verilog into a Xilinx bitstream? Am I asking for too much? A newbie to linux and FPGAs.Article: 30652
Allan Herriman wrote: > > > Our local Xilinx rep said that this seems to be a bug that they've > already identified, and it'll be fixed in service pack 8. > I couldn't find it in the Answers database though. > > Regards, > Allan. That's what they said about 2.1i & SP6. I wonder if there's something really deep-seated going on here since the problem has been around since at least 1.5i. Christain Schneider's comment about writing his own loop to do MPPR is exactly the work-around suggested to me 18+ months ago by the Xilinx support line.Article: 30653
Hi Dirk, Check out: "FPGA? What's that? A plain English answer to the question...", at http://www.burched.com.au/what.html Hope that helps :) Best regards Tony Burch www.BurchED.com.au Lowest cost, easiest-to-use FPGA prototyping kits! "Dirk Munk" <munk@home.nl> wrote in message news:3AE09B9B.7838C4BB@home.nl... > Hi, > > In a computer system that was used as a software RIP (EFI Fiery) to > drive a very big XEROX printer, we found a "mxv convertor board" with a > Altera Flex epf10k20rc208-4 chip. > > We already found out that it is a FPGA chip, but we have no idea what a > FPGA chip is suppose to do. > > Would someone please be so kind to enlighten us ? > > regards, > > Dirk >Article: 30654
ernstegon.NO@SPAM.freeze.com (Ernst Rattenhuber) writes: > Thanks, Nial. I guess you're probably right. I'll look into the ISA bus > specification (if I can get hold of it; it seems the IEEE specification has > been withdrawn). > > Ernst Rattenhuber There is only an IEEE *Draft* Std available. They didn't finish it yet :-) You can also have a look at Intel 440BX spec. You will notice that there are slight differences between Intel spec and the IEEE draft. Depending on the mode of operation a ISA read or write access needs about 160 ns or 540 ns. This kind of interface will be very easy to implement. -- ChrisArticle: 30655
Hi, I can't seem to find a site that sells wincupl. Is it still supported? -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 30656
Russell Shaw wrote: > > Hi, > > I can't seem to find a site that sells wincupl. Is it still supported? An Atmel library WinCUPL is available free on the Atmel WEB, this includes a virtual device type, so can create portable PLA files. Also, Protel's PLD support is via Wincupl engine. We do a lot of PLD ip in CUPL. -jg -- ======= 80x51 Tools & PLD IP Specialists ========= = http://www.DesignTools.co.nzArticle: 30657
Find the latest electrical/electronic engineering jobs http://a1ajobs.com/ee/ Use our archives to find your next job.. Easy keyword search engine. ASIC,RF,DSP,FPGA VHDL etc.. thanks for letting us post here..Article: 30658
k <ndgipper@blarg.net> writes: > Is there any linux shareware out there that will allow me to compile > Verilog into a Xilinx bitstream? > Am I asking for too much? You might be able to run the command line tools from Xilinx' free "WebPack ISE" package under WINE. B. Joshua Rosen has written a web page about running the "real" (e.g., pay money for) Xilinx tools: http://www.polybus.com/xilinx_on_linux.html I run WebPack ISE on Windows 98 SE on VMware on Linux, but neither VMware nor Windows 98 SE are free.Article: 30659
Yes, but is the atmel wincupl limited at all relative to the 'real' one? I can't seem to find the real one. Jim Granville wrote: > > Russell Shaw wrote: > > > > Hi, > > > > I can't seem to find a site that sells wincupl. Is it still supported? > > An Atmel library WinCUPL is available free on the Atmel WEB, this > includes a virtual device type, so can create portable PLA files. > > Also, Protel's PLD support is via Wincupl engine. > > We do a lot of PLD ip in CUPL. > > -jg > > -- > ======= 80x51 Tools & PLD IP Specialists ========= > = http://www.DesignTools.co.nz -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 30660
Insight make a Spartan-II PCI board. http://www.insight-electronics.com/solutions/kits/xilinx/index.shtml bye, Mark. Dan <daniel.deconinck@sympatico.ca> wrote in message news:3v0E6.701011$JT5.18572623@news20.bellglobal.com... > Hi , > > I need a Spartan II on a PCI bus. > > Who manufactures such boards ? > > Sincerely > Daniel DeConinck > High Res Technologies, Inc. > > > >Article: 30661
Utku Ozcan <ozcan@netas.com.tr> wrote: > BTW, from a designer point of view, I would recommend Xilinx should > give more information what impacts for each cost table value are on > the design. It is not declared anywhere. Ie. are cost tables from 1 > to 50 for speed and 51 till 1000 for area? It would have been Good point. Lately I've been working on P&R of a complex design (about 55% of a Virtex-E 2000). There are some super-critical paths in there. I've actually taken to routing them separately (MPPR), then using that to guide the full route. This flow seems to be working well so far. It occurs to me that you could have a design which is sufficiently complex that a single cost table will never get a good result for the entire chip. Especially if you are working in an XC2V6000 or larger. Perhaps I'm seeing this already. The flow I'm using now works with one critical module, but doesn't really scale to several. The only solution I can see at the moment is the modular flow now available in 3.x. It only allows two levels of hierarchy, but that's probably enough. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 30662
Jun wrote: > Hi > > I have tried to implement a > schematic in Xilinx Foundation 3.li > My target frequency is 50Mhz, when > the software finishes implementation, > the log file fe.log says > Maxium frequency is 10.5 Mhz > > What does it mean? Does it mean that > the maxium frequency of this bit file > after downloading to FPGA could only > be 10.5Mhz? > > Thanks a lot! fe.log means Flow Engine log file. You will see all the contents in the Flow Engine window in this file. I think you are talking about static timing analysis tool TRCE's report, which is also in this fe.log. 10.5 MHz might not correspond your clock. It can belong to one of your TIMESPECs although your clock constraint is satisfied. STA report shows the frequency of the slowest timing constraint defined in UCF file. You must read your PAR report (*.par file), which in the same directory where fe.log is. It gives frequency values of all of your timing constraints defined in your UCF file. UtkuArticle: 30663
Hi. I'm poor at English. Please excuse me. I want to know reconfigurable processor. What is this? So, what is differences between other processor like CISC or RISC? Thanks. Have a nice day.Article: 30664
Hi, I'm wondering why many of the newer (dedicated or FPGA) filter or upconversion devices have CIC interpolators/filters, with a lower limit on the amount of interpolation available, eg, many have a minimum interpolation of 8. For an interpolation value say of 3, with a low pass response, are there better (faster or more silicon-area efficient) ways to achieve this than CIC ? I'm particularly interested in FPGA implementations of the filters, rather than software. regards, Paul Teagle CAE ElectronicsArticle: 30665
HI My design targeted at 50Mhz however I could only get 10MHz Is there any way to improve the maxium frequency? Thanks a lot!Article: 30666
Hi Sorry to bother Here I need to design a counter I can counter from 0 to M( M is the input value), I hope the counter frequency to be as high as possible, Can anyone has some good suggestion? Also I have read something from Xilinx website, like prescaler counter etc, Where can I find more detailed information about prescaler counter or fast counter? Thanks a lot!Article: 30667
Helen, you mentioned 50 MHz. Any counter macro or library element will run faster than 50 MHz. You don't need anything exotic like a prescaler. Just make sure you use the dedicated carry, which every library element does automatically, at least in the case of Xilinx FPGAs. Read the data sheet and examine the delay parameters. 50 MHz is easy! Peter Alfke, Xilinx Applications ==================================== Helen wrote: > Hi Sorry to bother > Here I need to design a counter > I can counter from 0 to M( M is the input value), I hope the counter > frequency to be as high as possible, > Can anyone has some good suggestion? > Also I have read something from Xilinx website, like prescaler counter etc, Where can I find more detailed information about prescaler counter or fast counter? > Thanks a lot!Article: 30668
All, I have one register in my design that is clocked by a signal not on a GCLK pin... Right now I run it through and IBUF, then a BUFG and then to the register, but it gets routed all over the place in doing this. Is it possible to just run the signal from the IBUF to this one register? The tools don't seem to like it, I get errors during translate saying the signal has an illegal connection... I'm using foundation 3.1i sp7 and VHDL design entry. thx m -- Matt Billenstein mbillens (at) one (dot) net http://w3.one.net/~mbillens/Article: 30669
50MHz should be no problem for Altera, Xilinx, or Lucent FPGAs (and most others). One optimization you might want to consider: instead of clearing the counter to 0, and then counting up to M -- If M is an n-bit register or value, make the counter n+1 bits wide. initialise the counter by LOADing the 1s complement of M (all bits of M are inverted). The MSB is initialised to "1". count up to 0. When the MSB is 0, you've reached your terminal count. Now you can "decode" the terminal count state with a single signal, rather than an n-bit comparison. You can accomplish the same thing by loading the value M into your counter (the MSB always gets init'd to 0), and counting DOWN to 0. When the MSB becomes "1" (the count is now negative), you've reached the terminal count. Depending on how you handle the counting and initialising, either of these methods will give you one extra count. If you can compensate for or tolerate this, the decoding logic will have been made much simpler. If this is a ridiculously obvious optimisation, please accept my apology. -- Bob Elkind, eteam@aracnet.com Helen wrote: > > Hi Sorry to bother > Here I need to design a counter > I can counter from 0 to M( M is the input value), I hope the counter > frequency to be as high as possible, > Can anyone has some good suggestion? > Also I have read something from Xilinx website, like prescaler counter etc, Where can I find more detailed information about prescaler counter or fast counter? > Thanks a lot!Article: 30670
Hi folks, I'm currently looking for an "old" piece of software from Altera, called the DSP Design Kit. I have read some articles in EDNMag on the web where it was used, but I can't find it.I've e-mailed Altera, but they directed me to their FIR Compiler Megafunction, which costs way too much! I think the DSP Design Kit is free, or was anyway. So, is there anyone who knows where I can obtain, preferrably download, the DSP Design Kit? Any help will be much appreciated! regards Kristian -- ----------------------------------- Kristian Rye Vennesland E-mail : Kristirv@stud.iet.hist.no Cell.phone : +47 97 03 14 94 Mail Address: Kristian Rye Vennesland Nonnegata 2B 7014 Trondheim N-7014 NORWAY -----------------------------------Article: 30671
Yes, it can be done in any of the latest crop of families. However, for a single thread you will not be using the block rams or virtex II multipliers, as they will not run at 240 MHz. Several of the respondents to this thread suggested various sine/cosine look-up schemes, but for your application I do not recommend that approach. Instead, use a CORDIC rotator, as discussed in my article (http://www.xilinx.com/xcell/xl38/xcell38_48.pdf) in the Dec2000 issue of the Xilinx XCELL magazine, as it will give you better fidelity, performance and density than other methods. To hit the 240 Mhz with the rotator, you'll have to go to some low level pipelining. In virtexII, you should be able to hit 240 with a single instance. In Virtex-E, you'll get a better chance of success using two parallel rotators, each handling alternate samples, as very extensive pipelining would be required otherwise. Since the CORDIC does not require a history of samples, this should be no problem. You will have considerably better results with the xilinx architecture than with altera on this design because the add/subtracts in the CORDIC are implementable in one layer of logic in the Xilinx, where they require two levels in altera because of the carry chain structures. Contact me privately for a quote. Paul Teagle wrote: > > Hi, > > I'm looking for a very rough back-of-the-envelope estimate on the > feasibility of implementing a complex DDS & modulator component in a FPGA. > The relevant specs are: > > - operating at 240 mega complex samples/sec > > - 16 bit I & Q inputs to the modulator > > - phase accumulator 32 bits > > - 18 bit sine/cosine look-up accuracy, 20 bit result > > - 5 bit phase dither (selectable) on lsb's > > Assume the data is sourced on-chip and goes to other destinations on-chip. > > A reasonable amount of pipeling can be tolerated. > > We have no preference of Altera/Xilinx at the moment. SRAM based is > required, though, as is having a fair amount of other FPGA area for other > functions. > > There are several other aspects of the design (interpolators, multipliers > etc) that I haven't mentioned, but its the DDS that I think is the most > complicated. > > Any of you contractors out there want to hazard a rough order of magnitude > of cost for developing this sort of thing, maybe in terms of hours & > dollars, and amount of area it would consume on device XYZ ? > > regards, > > Paul Teagle > Systems Engineer > CAE Electronics -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30672
Kevin Neilson wrote: > > The DDS is normally straightforward but 240MHz is pretty fast for a Xilinx. > I just had to do a fast one so here's a couple of hints: > > -The 32-bit phase accumulator can be fully pipelined by making it a group of > 32 half adders, with the carries pipelined from one to the next. Then you > need to delay the lower bits to match them with the upper bits; you can use > the SRLs for this. This is bigger, but faster. > -The BlockRAMs will never work at 240MHz. The clock->out time is about 3ns, > but it also takes a while to route the output to the next register. One > trick is to use both ports of the dual-port BRAM sine lookup table. You use > the first port on one cycle, the next on the next cycle, etc, making the > BRAM a 2-cycle path. (You have to commutate the two output ports into one.) > But you probably can't have 2^18 precision, because that would require all > the BRAM in an extended memory part. > -There was an article in the Xilinx XCell magazine about the Cordic > algorithm, which might be applicable to you. for 18 bits, CORDIC is the only reasonable way to go. I've done linear interpolation for sine/cosine tables (for example a 100 MS/S tuner design in altera 10K250-2), but you won't get beyond 9 or 10 bits of phase resolution by that method. You are entirely correct that the block rams will not get anywhere close to 240 Mhz. If you were to use the block ram approach, you'd be best off using two on an alternating sample basis. As you point out, you can use both ports to double the effective bandwidth. You still need to double the RAM count however to get simultaneous sine and cosine. > > I think the phase ditherer is just a simple LFSR you can XOR with the LSBs. > > There's got to be a way to reduce the sine lookup table size. I wonder if > you could linearly interpolate between two points in a smaller table? Or > maybe calculate sine using some sort of hardware Maclaurin series > calculator? > > "Paul Teagle" <pteagle@chariot.net.au> wrote in message > news:3add9bf3_1@news.chariot.net.au... > > Hi, > > > > I'm looking for a very rough back-of-the-envelope estimate on the > > feasibility of implementing a complex DDS & modulator component in a FPGA. > > The relevant specs are: > > > > - operating at 240 mega complex samples/sec > > > > - 16 bit I & Q inputs to the modulator > > > > - phase accumulator 32 bits > > > > - 18 bit sine/cosine look-up accuracy, 20 bit result > > > > - 5 bit phase dither (selectable) on lsb's > > > > Assume the data is sourced on-chip and goes to other destinations on-chip. > > > > A reasonable amount of pipeling can be tolerated. > > > > We have no preference of Altera/Xilinx at the moment. SRAM based is > > required, though, as is having a fair amount of other FPGA area for other > > functions. > > > > There are several other aspects of the design (interpolators, multipliers > > etc) that I haven't mentioned, but its the DDS that I think is the most > > complicated. > > > > Any of you contractors out there want to hazard a rough order of magnitude > > of cost for developing this sort of thing, maybe in terms of hours & > > dollars, and amount of area it would consume on device XYZ ? > > > > regards, > > > > Paul Teagle > > Systems Engineer > > CAE Electronics > > > > > > > > > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30673
Paul Teagle wrote: > ) > > Obviously, we'll need a couple more multipliers & adders, but from the sound > of it, the Virtex-II multipliers will cope with the speed (?) No. unpipelined, the 18x18 multiply is a measley 140 MHz. Using the pipeline register, which is not enabled in software and not characterized in the specs yet, it is rumored that you'll get about 205 MHz. This assumes very little if any routing delay to/from the multiplier as well. > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30674
Paul, I think you also mentioned (but now rereading it I don't see it) that your local oscillator has a fixed frequency. If that is the case, you would gain a huge processing advantage if you can lock your sample frequency to the local oscillator frequency at either Fo=Fs/4 or fo=3Fs/4. By doing that, your mixer reduces to a pair of gated two's complement stages and you get zero sine approximation and phase angle truncation errors. If the front end does not have to be tuned, make some system level design changes to allow simplified hardware! Paul Teagle wrote: > > Kevin Neilson <kevin_neilson@yahoo.com> wrote in message > news:i7wD6.268$cf6.37903@newsread2.prod.itd.earthlink.net... > > The DDS is normally straightforward but 240MHz is pretty fast for a > Xilinx. > > my thinking as well - pretty fast, but not absolutely TOO fast. > > > I just had to do a fast one so here's a couple of hints: > > > > -The 32-bit phase accumulator can be fully pipelined by making it a group > of > > 32 half adders, with the carries pipelined from one to the next. Then you > > need to delay the lower bits to match them with the upper bits; you can > use > > the SRLs for this. This is bigger, but faster. > > One thing I forgot to mention was that the frequency value stays constant, > but I'm not sure if this helps. > > > -The BlockRAMs will never work at 240MHz. The clock->out time is about > 3ns, > > but it also takes a while to route the output to the next register. One > > trick is to use both ports of the dual-port BRAM sine lookup table. You > use > > the first port on one cycle, the next on the next cycle, etc, making the > > BRAM a 2-cycle path. (You have to commutate the two output ports into > one.) > > But you probably can't have 2^18 precision, because that would require all > > the BRAM in an extended memory part. > > > -There was an article in the Xilinx XCell magazine about the Cordic > > algorithm, which might be applicable to you. > > > > Ray Andraka's area, I think. > > > I think the phase ditherer is just a simple LFSR you can XOR with the > LSBs. > > > > There's got to be a way to reduce the sine lookup table size. I wonder if > > you could linearly interpolate between two points in a smaller table? Or > > maybe calculate sine using some sort of hardware Maclaurin series > > calculator? > > Perhaps a coarse/fine table: > > sin(a+b) = sin(a)cos(b) + sin(b)cos(a) > > where a = 9 bits coarse angle (say 0 to 360/(2^8)) = 0.7 degrees > b = 9 bits fine angle (say 0 to 0.7/(2^9)) = 1.37millidegrees > > Thus two, 512 word look-up tables, rather than a single 262k table, to get > the same precision...Dual port to access the sine & cosine simultaneously, > with any caveats for look-up speed. > > Maybe some complication to put the angle into an (a+b) format first, but how > hard can it be :-) > > Obviously, we'll need a couple more multipliers & adders, but from the sound > of it, the Virtex-II multipliers will cope with the speed (?) > > Time to start reviewing the device specs. > > Thanks for the input so far. > > regards, > > Paul T. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com
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