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Is there a place on the Xilinx site to read the release notes? Just wondering what's in Service Pack 8. LesArticle: 31326
Hi, I have just discovered this newsgroup, so if I am asking a FAQ, please excuse. I have been running the Xilinx Weblink software for some time, but now installed it for the first time on my new notebook under ME. I am trying to implement my first (and extremely simple) piece of VHDL but get error exit 2 from the fitter, with a red cross next to the "Create Timing Simulation Model". This is regardless of whether I make the "output file format" VHDL or "None" in the fitter properties under the field "timing simulation" In the log it says:" EXEWRAP detected a return code of '2' from program 'hitop'" Thanks StephenArticle: 31327
> for an asynchronous data stream, oversampling at a factor of 4 or even 8 > is probably not enough. If you look at any data-sheets, such as the > Infineon C166 Architecture, you will usually find that the over-sample > rate for an asynchronous interface is usually 16. The best value to I agree. I used a 'conventional' 74C297 ADPLL architecture (you can look up the 74HC297 on Philips's semiconductor website, they have complete schematics) to perform digital clock recovery. It was far from painless. In my case, the receiver circuit monitors an incoming biphase-mark coded (BMC) signal. The signal has 0/1(1/0) transitions at either 1X or 2X the 'data-bit frequency' (symbol rate.) I found that using an oversampling factor of 100X or more was a minimal requirement for maintaining acceptable jitter. On the other hand, I really had no clue how to design an ADPLL. I put together a state-machine which 'plucked' the incoming signal of 2X-transitions, leaving behind only 1X transitions. Then, I connect the 74HC297 ADPLL to lock onto this spectrally-filtered signal. The main problem, was that the system had to maintain a very wide frequency capture range (from 1.0x - 2.5x.) I could not think of a simple way to do this, so I 'cheated' and used external knowledge of the incoming signal to give me a rough-estimate of the symbol-rate. (the BMC signal is demodulated from an FM-carrier, and I can use a simple binary-slicer to 'count' the #FM-waves per second. The FM-carrier's frequency can vary, but the relationship of carrier-to- symbol frequency is fixed to a constant.) darn it, I'm rambling again...Article: 31328
> > I'm a user of ModelSim PE/VHDL. For financial reasons beyond my control I am > > being asked to consider switching to modelsim XE. I recall seeing somewhere > > that XE is literally just a slowed down version of PE (something like 3x or > > 5x). > > I think so. Why not download an eval and run it on your own code. Because maybe the web (evaluation) versions differ significantly from the retail product, to the point that downloading the evaluation version to evaluate the retail-version is pointless? Just speaking hypothetically, I have no evidence to support or refute my hypothetical question.Article: 31329
Les S Brodie <les_brodie@agilent.com> writes: > Is there a place on the Xilinx site to read the release notes? Just > wondering what's in Service Pack 8. http://www.xilinx.com/support/techsup/sw_updates/31i/33i_sp8/33i_sp8_readme_pc.htm You may need to enter your Xilinx Username & Password - I'm not sure. HTH, KentArticle: 31330
Hello Paul, I'm seeing this exact problem with the Virtex E VHDL UNISIM library. In simulation, I have to force a single clock pulse on CLKA before writes to port B take. All of my previous designs have had continuously running clocks on both ports so I never saw this problem before. On my current design, however, CLKA comes intermittently from the outside world. One of the most challenging parts of FPGA design is fooling the tools into working. Rob Weinstein IDS - Phoenix On Sun, 13 May 2001 11:59:50 +0100, "Paul McCanny" <p.mccanny@ee.qub.ac.uk> wrote: >Hi, >I was wondering if anybody else was having problems using the Virtex2 >blockRAM. I have a piece of code that uses the two ports provided. One of >these is set only to read (port A), the other is set to strobe between read >and writes (port B). When simulating I noticed that the memory doesn't >behave like it should. For some reason the portB does not seem to >successfully write to the port until the portA clock is activated. Then >everything works fine. I hacked a solution to this problem by making portA >clock when reset is held high but I was just wondering if anyone else had >similar problems and if I can expect any more. > >Thanks, > >Paul > >Article: 31331
Stephen du Toit wrote: > > Hi, > I have just discovered this newsgroup, so if I am asking a FAQ, please > excuse. > I have been running the Xilinx Weblink software for some time, but now > installed it for the first time on my new notebook under ME. I am trying to > implement my first (and extremely simple) piece of VHDL but get error exit 2 > from the fitter, with a red cross next to the "Create Timing Simulation > Model". This is regardless of whether I make the "output file format" VHDL > or "None" in the fitter properties under the field "timing simulation" > > In the log it says:" EXEWRAP detected a return code of '2' from program > 'hitop'" > > Thanks > Stephen Dear Stephen, You don't have to excuse - all welcome on this NG [excepting marketing, lawyers, & recruitment agencies who can't write English]. The first port of call for this sort of thing is the Xilinx answers data base. But in this case I might be able to help you a little quicker. Win98/ME sometimes have trouble with long path names. I tripped over this a couple of weeks ago in a rare excursion onto a Win98 machine. If I were you I would persuade my firm that its in their interests to pay you to upgrade your laptop to WinNT-workstation or whatever's the cheapest flavour of Win2K. It doesn't matter what they call it Win95/98/ME is still MSDOS-with-a-nose-job.Article: 31332
Kent Orthner <korthner@hotmail.nospam.com> writes: > Les S Brodie <les_brodie@agilent.com> writes: > > > Is there a place on the Xilinx site to read the release notes? Just > > wondering what's in Service Pack 8. > > http://www.xilinx.com/support/techsup/sw_updates/31i/33i_sp8/33i_sp8_readme_pc.htm > > You may need to enter your Xilinx Username & Password - I'm not > sure. They corrected the speed files! You need a password to fetch the Service Pack it's now 70 000 kB big! -- ChrisArticle: 31333
Hi Julia,
> Hi there!
>
> Anyone can point me to a good and sufficient tutorial (in the internet) in
> the FPGA to start with it from zero to the top (basics, design,.. etc)?
>
1) Learn how to do Logic Design, if you don't know already. I'd
recommend your local university library.
2) You can uses either schematic entry or a hardware description
language (HDL) to enter your design.
HDLs like VHDL or Verilog have the advantage that you can apply
methods from software engineering like version control and
reusability, so I'd recommend this aproach.
There are good FAQs available in comp.lang.vhdl comp.lang.verilog.
2a) It's also a good idea to simulate the behavior of the design, to
check it.
3) Synthesize the design to the target technology. This translates the
HDL to a lower, technology specific level.
4) Use the tools the FPGA vendor provide to create a file, a bitstream
or whatever to be able to program a FPGA.
4a) You can do a timing simulation of the design now to verify if
everything is ok.
For points 2a) to 4a) I'd recommend the Xilinx homepage
(www.xilinx.com) as a resource. Xilinx has links and collected
tutorials from may vendors of synthesis tools, who mention how to code
a design, give example designs and give more information on FPGA
technology.
http://support.xilinx.com/apps/hdl.htm
Ciao,
Chris
Article: 31334Hi, Anyone have a working example of the 16-point FFT using the Xilinx core from the coregen? In my implementation, Modelsim 5.5a PE displays an error message indicating : mux2w16r has changed so vfft16v2 needs to be recompiled. I have receompiled the unisim, simprims, logiblox and coregen libraries, still having the same error. The same error occurs when I use the previous Modelsim 5.4e PE edition.Article: 31335
Has anyone used the Triscend E5 (8051 core w/FPGA) ? I'm looking for experiences both positive and negative. We had a vendor presentation, and it looked good, but my questions to their technical support have gone unanswered and I'm afraid they're not going to be around long. Thank you, Steven J. Ackerman, Consultant ACS, Sarasota, FL http://www.acscontrol.com steve@acscontrol.com sja@gte.netArticle: 31336
"Steven J. Ackerman" wrote: > Has anyone used the Triscend E5 (8051 core w/FPGA) ? > > I'm looking for experiences both positive and negative. > > We had a vendor presentation, and it looked good, but my > questions to their technical support have gone unanswered > and I'm afraid they're not going to be around long. > > Thank you, > > Steven J. Ackerman, Consultant > ACS, Sarasota, FL > http://www.acscontrol.com > steve@acscontrol.com > sja@gte.net Steve: My company makes a tutorial package for the TE5 that includes a development board (with schematic), FastChip software (full license), and a tutorial that shows how to use the chip and software. You can look at the kit at http://www.xess.com/prod022.php3. There are links on that page to a more detailed description of the board and to the tutorial. You can download chapters of the tutorial and possibly find some answers to your questions there. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 31337
Am I the only one who think this is grossly inappropriate ? Eric.Article: 31338
It's not free but Aldec's Active HDL is much cheaper than Modeltech and = does an excellent job. Regards, Tom Dillon Dillon Engineering, Inc. http://www.dilloneng.com >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<< On 5/14/2001, 4:59:49 AM, "Meelis Kuris" <matiku@hot.ee> wrote regarding= =20 free simulator: > Hi! > I've been using Modeltech XE which comes with WebPack > and I'm getting really tired of this design size limitation and > it's generally quite slow and the DCM phase shift problem I wrote abou= t, > etc. > So, what other free/shareware simulator can I use for simulation > where I can also use Virtex2 specific things like DCM? > Can I use Veribest simulator coming with Actel Desktop > software? Is it possible to use unisim library with it? > How? Tried linking the same unisim library which was meant > for Modelsim, no success. > Or any other suggestions? > Thanks, > MeelisArticle: 31339
I wish I could provide a nice link or suggested reading material. It seems there are many paths that can lead you away from a decent design implementation. Essentially what is needed for a digital PLL is 1) a reference clock that's greater than the digital rate, 2) a way to generate an "error signal" to say when your data edges are faster/slower than your internally generated clock, and 3) a way to use the error signal to change your frequency. Additional information that's neccesary to determine how agile the generated clock needs to be is if there's significant input jitter (the data edges are somewhat ahead or behind in time) or changes in frequency. If there's a wide frequency range to use, there may need to be a coarse adjustment before a precise lock may occur. If the frequency is constant and known, life can be very easy. The DPLL in a uart is pretty sure it knows the frequency. When a data edge comes in (at the start bit), the following bits in the character are just sampled at known intervals after that first edge. For a 16x clock, sampling a bit every 16 clocks works within that ~10 bit window. If the data stream is continuous, each edge could reset the "zero phase" of the clock. Effectively, the error has been sampled at the data transition and subtracted out for the further samples. For longer times between data edges where the frequency offset can be a problem, things get more involved. Rather than talk about it in detail (frequency accumulators, integrating error, non-integral clocks) you can email me if you have further questions.Article: 31340
The links to the contents of the latest version don't work. Please correct the problem.Article: 31341
Eric wrote: > > Am I the only one who think this is grossly inappropriate ? > > Eric. I thought the same at first but after reading what appear to be the catch-all and innovation stifling nature of the ``patents'' I at least partly changed my mind & removed the ``grossly''. Its still inappropriate but if the patents are as bad as the abstracts make out then who better to shoot them down than readers of this NG ? Of course the patents may be being presented in the worst possible light, I'll check up. If so then normal service vis-a-vis all things lawyer will be resumed.Article: 31342
As you know, Atmel software version 7 no longer comes with anything but place-and-route. So I'm hoping that I could synthesize and simulate with Electric. However, Electric's fpga technology environment requires the user to make up code for specific fpga's. Not having learned how to do that myself, I wonder whether anyone out there has made up such technology code for the Atmel AT40. Thanks.Article: 31343
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Hi, The Xilinx PCI interface is compliant and should work seamlessly with all PCI compliant systems. The problem you are encountering is most likely the result of the large I/O space request made by your design. Some machines may not have 256 bytes of contiguous I/O space available to accommodate your card. In which case, it will not configure. Other machines may have 256 bytes of contiguous I/O space, but other devices in the system may need to be mapped in I/O space as well -- in this case, the operating system or plug and play driver will run into a conflict -- leaving one or more devices unconfigured. If it should happen to be that the disk controller is not configured due to resource conflict, you will observe the machine fail to boot. I would highly suggest that you avoid use of I/O space as if it were the plague, especially in new designs. Unless you are doing a design that requires I/O space for legacy reasons, use memory space instead. Eric > I'm using a Xilinx PCI core (33Mhz, 32bits) in a Spartan 200 FPGA on a > specific PCI board. When i am using this board in "old" computers > (Pentium 200MMX for example), everything works correctly: The computer > detects the board and maps its memory and I/O as asked in the macro > (256 bytes of I/O and 512Kb of memory). > > But when i'm trying to use the board in recent computers (Pentium III), > i have some problems: first some computers cannot boot. If i change > the amount of I/O (256 -> 64 bytes), then the computer can boot, the > I/O are mapped but the memory is not mapped. > > I'm wondering if the problem comes from the computer (Bios an PnP) or > if it comes from the Xilinx PCI core: May be this core is not supported > by recent PCI chipset used in recent computers.Article: 31345
No. I am, however, available for such consulting. Where do I sign up? Eric Some other Eric wrote: > > Am I the only one who think this is grossly inappropriate ? > > Eric.Article: 31346
asfsdfrewrew wrote: > > > > I'm a user of ModelSim PE/VHDL. For financial reasons beyond my control I am > > > being asked to consider switching to modelsim XE. I recall seeing somewhere > > > that XE is literally just a slowed down version of PE (something like 3x or > > > 5x). > > > > I think so. Why not download an eval and run it on your own code. > > Because maybe the web (evaluation) versions differ significantly from > the > retail product, to the point that downloading the evaluation version to > evaluate the retail-version is pointless? > > Just speaking hypothetically, I have no evidence to support or refute my > hypothetical question. I have downloaded the trial version and it is limited to 500 lines of executable code. It is not a fast version of the simulator, but once your program is larger than 500 lines, the simulator becomes 10x or so slower and nearly unusable. From reading the Xilinx web site, (and you have to search very hard to find it) the XE simulator has a similar maximum program size. I don't remember the exact size, but I think it is 5000 executable lines. So don't assume that the $1000 XE simulator is good enough for your application. You may be very disappointed. If necessary, speak with Xilinx before you commit to taking the step backward. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 31347
Tom Kaminski wrote: > > I'm also having problems with FPGA express & One hot state machines. This > is what I've found: > > The finite state machine itself is synthesized correctly using dual process > method or single process method (ie. both sythesize with one register per > state). However, if you use the state signal outside of the FSM process, > FPGA express uses all the registers in the FSM to determine if it is in > that state. The proper way is to only compare one state register. I found this out the hard way a few years ago when I was first learning VHDL. It was a nightmare for a newbie. I don't know that you can call it a "bug". But as a result, I don't do my FSMs using the standard coding style. I explicitly define my states and use IF statements to check for state values using a simple AND... // This is verilog, I have gotten rusty in VHDL if (pres_state & STATE1) begin ... put your next state assignments here end This will detect the state by checking only the one bit that defines that state. It also works for both the state code and any output code you care to use, like this... assign output_A = (pres_state & STATE1) || (pres_state & STATE2) ; // or whatever states you need Of course, this coding style only allows one hot encoding. So you lose some of the flexibility of the case statement approach. I don't remember for sure, but I belive you can use separate state assignments and output assignments with one hot encoding. But you have to put the output assignments in a second process that uses a case statement. I also seem to remember that FPGA Express will generate a lot of logic for the register enable when you don't define each output in all of the cases. But it has been a long time. My memory could be wrong or they may have changed their implementation. One other comment about using one-hot encoding. It is very efficient for making fast FSMs when you don't have a lot of state transitions into and out of each and every state. Essentially, in one-hot encoding each bit is an independant function. The equation for this function will have an input for each state and input condition(s) that describe a transition into or out of that state. So if you have a state with three inputs and three outputs, all involving separate states and conditions, you will have a function of 12 inputs, not counting the "stay in this state" transition if it exists. So it is not uncommon for one-hot encoding to make a bigger, slower FSM than a binary encoded one. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 31348
Neil Franklin wrote: > > gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > > > Neil Franklin <neil@franklin.ch.remove> writes: > > > > >Eric Smith <eric-no-spam-for-me@brouhaha.com> writes: > > > > >> Bzzzt! No longer commercially available. > > > > >Not any more? Bummer. > > > > >All the more reason for me to get on with my clone then. :-) > > > > There is now a software emulator that runs under most unix > > systems. The remaining bugs are rapidly being worked out. > > Actually multiple of them: TS-10, E-10 and simh2.6 > > But emulators are not quite the same thing as real hardware. :-) Depends on the hardware. I would be willing to bet that an emulator on a current desktop will run faster than the original machine from when, the late 70's, early 80's? Even if you clone the hardware in an FPGA, I bet an emulator can keep up unless you do a lot of opimizations such as pipelining, etc which the original machine likely used sparingly. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 31349
Rick Collins wrote: Depends on the hardware. I would be willing to bet that an emulator on a > current desktop will run faster than the original machine from when, the > late 70's, early 80's? Even if you clone the hardware in an FPGA, I bet > an emulator can keep up unless you do a lot of opimizations such as > pipelining, etc which the original machine likely used sparingly. It also depends on the the size of the emulator too! I am designing a small cpu with a 12 bit byte size. With the FPGA hardware I have the best speed I can get is a 4 Mhz 6809 style memory cycle ( 16 Mhz clock). The FPGA will clock up to 6 Mhz (24Mhz) in this design.A simple loop benchmark of 1000,000 times is 5.75 seconds with the 250 ns memory cycle. On a creaky old P150 running a emulator under linux the bench mark runs at 5 seconds real time. Since the emulator is small I can assume the program fits in the external cache. If the external cache is 25 ns ( 10x faster than my cpu) I can assume the emulator will always run faster than my cpu. FPGA speeds are about the same 74ALSxx or custom chips in the early 80's. ( Read before the 386 :-) ). With what little FPGA designs I have done (Altera/Quicklogic) I have found both chips to be about the same speed. Personally I like the quicklogic FPGA over the Altera FPGA. Since I found getting a PROM burnt for my FPGA board is very pricey if I do PCB for my computer I might pick the Quicklogic chip over the Altera one. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk
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