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Hi, I have generated a bit file for Virtex-E using BitGen. While trying to download the design on the chip which resides on a development kit, the folowng error pops up in the Hardware Debugger: "Device is not configured. Done is not high." Regards, Asfandyar.Article: 31901
http://support.xilinx.com/support/techsup/tutorials/tutorials31i.htmArticle: 31902
Hi,
Just to clear up a bit of confusion on my part:
If i.e. the XC4000E states System Performance beyond 80MHz, does that
mean the maximum
clock is 80 MHz or that is the maximum rate at which data can get from pin
to pin after going through some internal combinatorial logic.
Article: 31903"Chuck Woodring" <woodringfam@earthlink.net> writes: > Just to clear up a bit of confusion on my part: > > If i.e. the XC4000E states System Performance beyond 80MHz, does that > mean the maximum > clock is 80 MHz or that is the maximum rate at which data can get from pin > to pin after going through some internal combinatorial logic. Arguably it doesn't mean much of anything. The only way to tell how fast your design can be clocked is to look at the timing analysis report. I suppose you could say that they are claiming that SOME designs may run faster than 80 MHz. They certainly aren't claiming that YOUR design will run that fast. (Well, maybe marketroids even make that claim, but don't necessarily expect it to be true.) About the only thing marketing quoted numbers like that are useful for is comparing different families of parts from the same vendor. And even that can be somewhat marginal.Article: 31904
"Miha Dolenc" <mihad@opencores.org> wrote in <9efpdd$4rh$1@planja.arnes.si>: > Hello everyone! > > I'm a member of OPENCORES group and we are working on FREE IP PCI > bridge core. > > I have a problem. I use NCSim and I can't seem to get primitives from > XILINX Spartan and Virtex working in it. We are trying to use Block > SelectRAM+ cells for FIFO implementation. > I've compiled unisim and simprim libraries with NCVlog and got one > warning (log file doesn't show the reason) for each primitive in the > library. When I simulate FIFO design, all outputs are always HighZ, > regardles of enable, reset or any other signal. Does anyone know what > to do? > > Thanx! > > Regards, > Miha Dolenc > > P.S. > If anyone wants to help us out with actual core design please > contat me > or visit our webpage > http://www.opencores.org/cores/pci/ > > > I also use NCSim to simulate SelectRAM+ FIFO.Our Virtex simulation primitives is on folder /unisim, and I use cell "RAM16X1D", "RAM16X1S"... On RTL simulation, don't use /simprim, it's used in GSIM. Xilinx P&R tool receive "RAM16X1D", "RAM16X1S"... BTW, on common case, I run "ncxlmode" at RSIM.Article: 31905
I can help hardware engineers in Southern California find jobs. Interested parties should contact me at ECCRAIG@YAHOO.COM. Ed Craig cyber_spook wrote: > Is anyone looking for an Hardware engineer? Or can anyone recommend a > good agent? > > I live in the South East of the UK > > Regards > > Cyber_spook_man > pjc@cyberspook.freeserve.co.ukArticle: 31906
Hi all, I am looking to purchase some used development board. There is this one design based on teh XC4005XL fpga, that's 9000 gates. And I am just wondering from you folks, it is board modern enough to spend my money on? I maen I don't want to buy a board and learn if its based on obsolete technology. With these FPGA, things become obsolete so fast.Article: 31907
System performance of 80 MHz means that you can do meaningful things at an 80-MHz clock rate. Not that every conceivable logic will run at that speed, but that reasonably complex logic can run at that speed. Today, we talk of 150 and 200 MHz for fairly complex logic in Virtex-II, and clock rates of up to 400 MHz ( e.g. for shift registers.) The real max speed depends on the design, and Xilinx gives you the analysis tools that let you calculate this worst-case guaranteed number with fractional-MHz accuracy. Peter Alfke, Xilinx Applications. ============================= Chuck Woodring wrote: > Hi, > Just to clear up a bit of confusion on my part: > > If i.e. the XC4000E states System Performance beyond 80MHz, does that > mean the maximum > clock is 80 MHz or that is the maximum rate at which data can get from pin > to pin after going through some internal combinatorial logic.Article: 31908
Well, it's not the newest technology, it's 2 generations behind, and by today's standard, the capacity is very small, well below the smallest chips in the newer families ( Virtex and Virtex-II. ) But it's 3.3 V technolgy, which is good, and means it will be around and be supported for years to come. So, it's a small, "mature" device that lacks many of the features in the newer families, notably clock management and BlockRAM. But for small jobs, it should be just fine. Peter Alfke, Xilinx Applications SN wrote: > Hi all, I am looking to purchase some used development board. There is > this > one design based on teh XC4005XL fpga, that's 9000 gates. And I am just > > wondering from you folks, it is board modern enough to spend my money > on? > I maen I don't want to buy a board and learn if its based on obsolete > technology. > With these FPGA, things become obsolete so fast.Article: 31909
I am interested in the Virtex Series (not Virtex II). The problem is Where can I buy it?. And, Which are the prices of them?. I live in (Malaga) Spain. If Virtex Series are not supported by Xilinx change the word Virtex by Virtex II in the before paragraph. Do there exist others FPGA or similar products in the market?. Which are the links on the distints FPGA with independents comparatives?. THANKS. My name is Julian Calderon Almendros. I Live in Malaga (Costa del Sol) Spain. I am professor of Digital Electronics and Microelectronic and Microlectronic Laboratory. University of Malaga (UMA). Universitary Politechnic School of UMA. Department of Electronic Technology.Article: 31910
Virtex is too expensive. You should buy Virtex-E or Spartan-II. With a little luck, in small quantities both can be bought in europe from Inisght Electronics. If you only need a few parts for research you can request a donation from the Xilinx University Program. Kolja Sulimma "Julián Calderón Almendros" wrote: > I am interested in the Virtex Series (not Virtex II). The problem is Where > can I buy it?. And, Which are the prices of them?. I live in (Malaga) Spain. > If Virtex Series are not supported by Xilinx change the word Virtex by > Virtex II in the before paragraph. > Do there exist others FPGA or similar products in the market?. > Which are the links on the distints FPGA with independents comparatives?. > THANKS. > > My name is Julian Calderon Almendros. > I Live in Malaga (Costa del Sol) Spain. > I am professor of Digital Electronics and Microelectronic and Microlectronic > Laboratory. > University of Malaga (UMA). > Universitary Politechnic School of UMA. > Department of Electronic Technology.Article: 31911
Matthias Fuchs <matthias.fuchs@esd-electronics.com> wrote in message news:3B1FAD1E.4F46A283@esd-electronics.com... > Hi ! > > How can I force tristate enable registers into IOBs (xilinx Spartan II) > ? > Hi Matthias, I use FPGA Express but have experienced similar problems. My solution was to create a primitive entity that did work ie wrote code for a single IOB that worked, and then used a generate at a higher level to create multiple instances of that primative. With my synth tool (at the time) I even had to create a prim that had a TS (tristate) signal rather than an OE signal and invert it outside the primitive otherwise the tool would not infer the reg in the IOB - good huh. It was messy, but I have given up on trying to be too clever when having to hand-hold the tools. With my toolset you also have top tell the synth tool _and_ the placement tool to set "use IOB regs = true" or "push regs into IOBs" or whatever equivalent to make this work. Hope this helps, reply to group if you want code. FredArticle: 31912
Michael, check out the DIGILAB 10K10 at: http://www.elca.de/Products/prod%20d10k10e.html Guess you're from Germany - right? You can order this board from Conrad Elektronik. - Wolfgang Michael Zirngibl <greenland@vr-web.de> wrote in message news:9fm9ig$892$03$1@news.t-online.com... > Is there a cheap & available FPGA starterkit > that comes with VHDL software ? > > Michael > >Article: 31913
Tomek, have a look at www.trenz-electronic.de , section Free Dowloads. We have an application note implementing our Full Speed USB Function Controller on an XESS XSP-010 board, which is basically the same as the XS-40 board you are asking for. The project files are available under GPL after completing a short registration form and include a behavioral model of our core. The example is VHDL- but the Xilinx WebPack software includes a VHDL synthesizer for free which supports the Spartan family of devices. Hope this helps, best regards Felix Bertram ___ Dip.-Ing Felix Bertram Trenz Electronic Duenner Kirchweg 77 D - 32257 Buende Mailto:f.bertram@trenz-electronic.de http://www.trenz-electronic.deArticle: 31914
Hi, I'm studying the following architecture : I have an APEX200E with 1 embbeded NIOS microcontroller which runs his program from an external flash. The APEX's configuration file beeing contained in his 2 EPC2 configuration flash PROM. My main problem is NIOS and FPGA software update. I intend to use JTAG. The FPGA's EPC2 would be programmed by their JTAG pins. The flash memory has no JTAG pins. So I was wondering if I could program it by driving the FPGA's pins ( the address, data and control bus pins ) using the FPGA's JTAG capabilities. Does anyone has already done such a thing ? Does it works ? What is the consequence on the JTAG software on the host PC ? Thanks in advance. Stephane. Thales Microelectronics.Article: 31916
Hi all! I'm going to setup a Windows NT lab with either Xilinx webpack or Xilinx Foundation 3.1. We have up until now only been using Xilinx Alliance for Solaris. Anyway, my question is if anyone sucessfully has managed to setup such a lab. We tried to install Webpack with MXE (Modelsim XE) but, for some reason, Modelsim needs write access to the windows system directory. We do not want several hundreds of students having write access to the system directory... Has anyone got a solution to this problem? / Jonas ThorArticle: 31917
sorry, I mean "DONE" pin in my last sentence "stefaan vanheesbeke" <stefaan.vanheesbeke@pandora.be> wrote in message news:PJPT6.17916$mR5.1553354@afrodite.telenet-ops.be... > Hi, > > As far as I know, the configuration pins become user I/O's after > initialisation. You can't do anything with changing the mode pins after > configuration. > > Are you really sure that the device is configured (check the MODE pin)? > > "Werner Dreher" <dreher@informatik.uni-tuebingen.de> schreef in bericht > news:3B1E530D.1A348D65@informatik.uni-tuebingen.de... > > hello world, > > > > I'm designing a board with a SpartanII. The FPGA should be > > configured using slave parallel mode (with a microcontroller), > > and I want to be able to do readback (also in slave parallel). > > Up to this point all is clear. > > > > But after configuration and while no readback is in progress, > > I want to use the pins D0...D7, _CS, _WRITE and BUSY as user > > I/Os. I understand the data sheet in the way that this should > > be possible: "These pins become user I/Os after > > configuration unless the Slave Parallel port is retained." > > But how to retain the slave parallel port, and how to _not_ > > retain? > > Should I change the mode pins after configuration to free > > D0...? Are the mode pins sampled after configuration too? > > (the data sheet says that M0,M1,M2 are sampled before > > configuration when _INIT goes high after clearing the > > configuration memory.) > > Or are D0...D7 user I/Os after configuration when _CS is not > > asserted? But how to use _CS as user I/O? > > > > I can't find any hints in the data sheet or appnotes. > > Can anyone help me? > > > > Greetings > > Werner > >Article: 31918
Hi SN, I suggest that you don't purchase an old technology development board, when you can buy a brand new one for < US$120! The B3-SPARTAN2+ board from Burch Electronic Designs has a modern 200K gate Spartan2 device. http://www.burched.com.au/bedspartan2.html A download cable is included, and it works with the free Xilinx WebPACK software (note that WebPACK does not support XC4005XL). Compare this to the XC4005XL 9K gates - more than 22 x more gates, and a more modern architecture device (more on the chip: routing resources, DLLs etc.). You can have alot more fun with 200K gates ! :) Secure online ordering is available. International orders are very welcome. Best regards Tony Burch http://www.BurchED.com.au Lowest cost, easy-to-use FPGA prototyping kits! "SN" <strshn2001@home.com> wrote in message news:3B2054B3.2BBE8245@home.com... > Hi all, I am looking to purchase some used development board. There is > this > one design based on teh XC4005XL fpga, that's 9000 gates. And I am just > > wondering from you folks, it is board modern enough to spend my money > on? > I maen I don't want to buy a board and learn if its based on obsolete > technology. > With these FPGA, things become obsolete so fast. >Article: 31919
Hi all! I'm going to setup a Windows NT lab with either Xilinx webpack or Xilinx Foundation 3.1. We have up until now only been using Xilinx Alliance for Solaris. Anyway, my question is if anyone sucessfully has managed to setup such a lab. We tried to install Webpack with MXE (Modelsim XE) but, for some reason, Modelsim needs write access to the windows system directory. We do not want several hundreds of students having write access to the system directory... Has anyone got a solution to this problem? / Jonas ThorArticle: 31920
Foundation also needs write access to some system directories, but only to certain files that it copies there. I do not remember which right now. I general, Foundation is not very well suited for multi user environments, as it is common with windows software. (For example, every user sees the same file history) Usually selecting $USERHOME as the path, (or one of the other environment variables) should do the trick but it seems that only Microsoft themselves knows how to handle paths correctly. Aldec for sure doesn't. Kolja Sulimma Jonas Thor wrote: > Hi all! > > I'm going to setup a Windows NT lab with either Xilinx webpack or > Xilinx Foundation 3.1. We have up until now only been using Xilinx > Alliance for Solaris. > > Anyway, my question is if anyone sucessfully has managed to setup such > a lab. We tried to install Webpack with MXE (Modelsim XE) but, for > some reason, Modelsim needs write access to the windows system > directory. We do not want several hundreds of students having write > access to the system directory... > > Has anyone got a solution to this problem? > > / Jonas ThorArticle: 31921
Hello! I want to know if any good book/s is available that explain the basics of the CS-ACELP algorithm used in the ITU-T G.729 voice compression standard? Or is there any other material on any website available (not the G.729 standard..but the theory behind the CS-ACELP ) ThanxArticle: 31922
In article <3B1909B5.21119BF6@interlog.com>, Iouri Besperstov says... > >No, I didn't find on Zilog.com, I think Zilog doesn't provide open microprocessor core >any different idea where I can get core fore Z180 or Z182 Don't know about the Z180 or Z182, but the Z80 is almost certainly the most copied CPU in history. Many ASIC mfrs include the Z80 model as part of their library, so designers can build the Z80 into embedded products. JackArticle: 31923
I contacted Xilinx support about this same issue in September last year. This is their response: "Only workaround found is to do incremental synthesis. That is, code the behavior for your flop in a separate verilog module, synthesize it, then instantiate that black box in your main code. " Not too practical. Another workaround that I found was to set the maximum fanout attribute for those flip flops to 1, so that they do not get merged. Or use synopsys FPGA express. Jason Daughenbaugh http://www.aedinc.netArticle: 31924
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