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Austin Franklin wrote: > > I don't agree that schematics substitute for a block diagram. They are > > often so full of details that you can't see the flow for the gates! > > It all depends on how well you know how to use the tools! Obvioulsy, you're > not a schematic guy ;-) You certainly shouldn't have many, if any at all, > gates on your schematics, except at the lowest levels, or a random gate here > and there...for simplicity of drawing... > > > Using heirarchical schematics start causing some of the same problems > > that HDLs have. The signal names get complicated by the heirarchy path > > and even renamed as one wire that traverses several levels will have > > several names. The back end tool will want to pick just one name for the > > whole net, but which one? > > This is not a problem. The names are deterministic, unlike HDLs, which are > NOT deterministic. The signal names will be what ever is the topest level > signal name is. If you name your heirarchical elements, then the signal > name is very easy to follow. In another round of the, seemingly eternal, HDL vs. Schems debate no one seems to have brought up what I consider one of the biggest drawbacks of schems. Since they are usually binary files they are difficult to impossible to put under any meaningful form of version control i.e. one that can do diffs between revisions. One of the ++'s of text files is that its very easy to get something like CVS to ignore whitespace changes so that diffs don't get drowned. Even if there were a text file based schem package its a lot more difficult to extract the connectivity "signal" from the graphical "noise". The other missing issue, heavily related to the above, is portability.Article: 32001
Rick Filipkiewicz wrote: > > Eric wrote: > > (lots of snip) > > Problem is the same as trying to make pizza delivery with an 18 weels truck. > > > Sure you could deliver hundreds of them at a time, but who needs this kind > > of "performance" ? what peoples want is just one fresh pizza, delivered ASAP, > > not a zillion, delivered cold and somehow melted with the box, 1 hour later. > > Here too, latency matters a lot more than volume/bandwidth. > > That's the nicest analogy I've seen for what I usually paraphrase, following Bill > Clinton's first campaign, as: > > ``Its the latency, stupid'' > > No offence intended. > > Note that DDR DRAM also falls into this category of solving the easy bandwidth > problem instead of the hard latency one but at least it doesn't force you into > insanely expensive controllers, PCB technology, and license fees. There is an > indirect latency benefit in that high bandwidth stuff like PCI traffic uses less > memory time. > > <more snip> > > > Well, maybe this goes a bit off topic, but since Rambus started to bully > > SDRAM memory controllers makers (Hitachi H8 / PC chipset makers), it would > > be wise to keep an eye on what's to come for FPGA based controllers. > > > > Eric. > > They'll have to go after Xilinx first since the Virtex2 defines 2 ``DDR registers'' > in the IOB and there have been DDR DRAM controller apps notes on their web site for > ages. > > Great posting Eric. It should appear somewhere on a DRAM FAQ but Rambus would > probably sue the FAQ hoster. In fact if I were you I would consider getting a lawyer > now & moving all your assets off-shore. > > An interesting side note: When this came up I went I downloaded a RDRAM data sheet. > What did I see on the Rambus home page ? A little picture with a hot spot marked > ``New Litigation''. I think that just about says it all ... All of this sounds good on paper, but what do the benchmarks say? Are there any apples to apples comparisons? Or is the world split into AMD/DDR and P4/RDRAM? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 32002
Andy, I won't argue that there is any excuse for the way FPGA development tools are written. The standard of quality is low and I don't see where it has improved much over the last few years. But I can tell you why. It is simply a matter of quantity and the rapid rate of change of the hardware they must support. The FPGA vendors only sell a few thousand seats of these tools every year. With the limited revenue this brings in they just don't have the resources to hone the tools to "perfection". (I know we are a long way from perfection). With the hardware changing by coming out with a new family every year or two, and adding new members nearly constantly, the software teams are doing all they can to keep up. Whining may make you feel better and can serve as a means of feedback when posted to the newsgroup. But you need to temper your wants with your needs. If the problem you listed was the biggest problem you have with the tools, you will be very lucky. I would like a simulation tool that does not crash every fourth or fifth time I reload the design and I would really, really love a backend tool that lets me do a single mode of timing constraints rather than making me enter them twice in two formats; once for P&R and once for timing analysis (Altera MaxPlus+II). You might want to send the details of the VHDL issue to Xilinx support. If they don't know about it, they will likely want to fix it. Andy Peters wrote: > > OK, so I'm trying to synthesize some VHDL code that simulates fine. Nothing fancy, just some generates to create some registers. > > The synthesizer complains: ERROR : (VHP__0163). Where's the list of errors? Hitting F1 is no help. OK, look at the message: "Unexpected symbol read: BEGIN." > > Wait, this tool doesn't seem to understand the LRM. My generate statement looks like: > > foo: for ff in 0 to 2 generate > begin > bar: process (clk, rst) is > begin > if rst = '1' then > b(ff) <= '0'; > elsif rising_edge(clk) then > b(ff) <= c(ff); > end if; > end process bar; > end generate foo; > > Hmmm..Ashenden sez this is OK; so does ModelSim. So, what's wrong? Does XST support generates? > > Soooo... what's with the online help? Choosing Help->Online Documentation... brings up a web browser (IE only, can't change it) with the following error: > > "WebPACK Online Help. Please invoke the online help system from the Help and Technical Support icon in the Xilinx WebPACK program group." That's annoying. > > So, Choosing the "Help and Technical Support icon" in my WebPACK program group launches the HTML-based Help system. OK, hmmm..I'm doing a 9500XL design in VHDL, but I have no idea what XST supports and does not support. Where are the synthesis tool details? > > Oh, here they are: not under CPLD WebPACK ISE, but rather under FPGA WebPACK ISE->Tools->Synthesis. > > But wait -- there's only one simple page here. First line: "XST is a Xilinx tool that synthesizes HDL designs to create EDIF netlists. For detailed information about XST, refer to the XST User Guide." that's rather useless, so I click the "XST User Guide" hyperlink. > > That apparently runs the web browser within the help browser, connects to the Xilinx web site's "software Manuals Online" section, where I am NOT brought right to the XST User Guide -- which is what any reasonable person would EXPECT -- but rather, the top level of the Xilinx docs. Which still say 3.1i, but aren't they up to 3.3i SP8 or something? > > I click on the Design Entry icon. Wow -- looks like some outdated documentation. > > Ah -- waaaay down on the bottom of the "Docscan" frame, there's an XST link. Ah-ha! There it is. And there's VHDL Support, too. Where's Generate? > > Hmmm...it's under Combinatorial Circuits. Your guess is as good as mine as to why. > > Ah, here's something: I have the keyword BEGIN right after my generate statement (foo : for ff in 0 to 2 generate begin) which is required in VHDL'93 if we include any declarations, but can be omitted if there are none. Emacs seems to put them there, and I like my ENDs balanced by BEGINs. > > But the example in the docs does NOT have the BEGIN, and the synth is happy if I remove it from my code. But I'm not happy, since I have to modify my code to satisfy the quirks of a non-compliant tool. > > OK, so the tools are FREE. What should I expect? > > Well, I expect compliance with the language. Whom does Xilinx think they are, anyway? Synopsys? > > I also expect the documentation to be correct, and it and the tool should be OBVIOUS. If a menu item says, "Online help..." it should bring me directly to online help, not to a static HTML page with no links that says, "find something somewhere else." > > If a link says, "XST User's Guide," I expect it to take me DIRECTLY to the XST user's guide -- not to the top level of docs for everything. > > Xilinx: are you listening? > > --andy -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 32003
Austin Franklin wrote: > > > I don't agree that schematics substitute for a block diagram. They are > > often so full of details that you can't see the flow for the gates! > > It all depends on how well you know how to use the tools! Obvioulsy, you're > not a schematic guy ;-) You certainly shouldn't have many, if any at all, > gates on your schematics, except at the lowest levels, or a random gate here > and there...for simplicity of drawing... > > > Using heirarchical schematics start causing some of the same problems > > that HDLs have. The signal names get complicated by the heirarchy path > > and even renamed as one wire that traverses several levels will have > > several names. The back end tool will want to pick just one name for the > > whole net, but which one? > > This is not a problem. The names are deterministic, unlike HDLs, which are > NOT deterministic. The signal names will be what ever is the topest level > signal name is. If you name your heirarchical elements, then the signal > name is very easy to follow. I'm really not trying to continue the HDL vs Schematic debate. I am addressing the one point that was made about block diagrams. My point is that schematics are hard to use as block diagrams because they contain far too much detail if done flat. If they are done as a heirarchy, which makes them look more like a block diagram, they have some problems with signal names. I have had to deal with this problem before, so I know it exists. The fact that at any given level a net has a well defined name does not change the fact that you don't know which of the several names will be used in the end for this net. I seem to have noticed lately that the backend tools are using the name that is highest in the heirarchy. In the past I have seen the tool pick the name from the driver output or sometimes it seems to be just random. Regardless, until the tool vendor tells me what that name is, I have to guess from the many levels of the heirarchy. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 32004
"Chaudhry" <Imran@acronman.com> wrote in message news:9fsb6h$o2n$1@dahlia.singnet.com.sg... > Have anybody used FPGA device to control STN LCD panels either 16 bit or 24 > bit? We have designed an IP core, logiCVC - Compact Video Controller for Xilinx FPGA. Please visit http://www.logicbricks.com , or contact me directly for more info. Best Regards Gordan Galic gordan.galic@xylon.hr > > What is the possibility to do it ? we have a lots of stock of 6" STN panels > so we want to make standalone monitor for Video or VGA interface or both. > All the controllers for STN LCD's are either ISA or PCI based which is not > suitable for our application. > > Any comments will be appreciated. > > Regards, > > -- > *********************** > Chaudhry > ICQ# 11502664 > Singapore > *********************** > >Article: 32005
> > > This is not a problem. The names are deterministic, unlike HDLs, which are > > NOT deterministic. The signal names will be what ever is the topest level > > signal name is. If you name your heirarchical elements, then the signal > > name is very easy to follow. If I were doing schematic entry, I would still want my tools to perform logic optimizations. Doing something like running a SIS script over the netlist wont leave many of your signals intakt except in datapaths. Kolja SulimmaArticle: 32007
Set syn_useioff=1 as a global attribute in your constraint file. This will lead to replication of tristate enable FF's automatically. It will also put IOB=TRUE on your registers for you. hamish@cloud.net.au wrote: > > fred <x@y.z> wrote: > > With my toolset you also have top tell the synth tool _and_ the placement > > tool to set "use IOB regs = true" or "push regs into IOBs" or whatever > > equivalent to make this work. > > Isn't "-pr b" on MAP supposed to do this? > > BTW, Synplify always warns me that the option to pack FFs into IOBs > hasn't been specified. I could never work out how to specify it though. > I see to get IOB=TRUE on the relevant flip flops anyway. > > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 32008
> This > points out that all FPGA's (from different companies) are not created equal and > logic elements in FPGA's are non portable. If one tries to use features common > to all FPGA's you are 50% slower and 50% less dense in most designs. Not true. Differences can be made up for in libraries, such as, say counters. You can impalement a generic symbol for an N bit counter of a particular flavor, and change the underlying schematic to switch to an entirely different technology. I've been doing this for 10 years! You can easily isolate the low level implementation from the high level functionality, and with a well developed library for each technology, this is not an issue.Article: 32009
> I'm really not trying to continue the HDL vs Schematic debate. I am > addressing the one point that was made about block diagrams. My point is > that schematics are hard to use as block diagrams because they contain > far too much detail if done flat. If they are done as a heirarchy, which > makes them look more like a block diagram, they have some problems with > signal names. I have had to deal with this problem before, so I know it > exists. > > The fact that at any given level a net has a well defined name does not > change the fact that you don't know which of the several names will be > used in the end for this net. I seem to have noticed lately that the > backend tools are using the name that is highest in the heirarchy. In > the past I have seen the tool pick the name from the driver output or > sometimes it seems to be just random. Regardless, until the tool vendor > tells me what that name is, I have to guess from the many levels of the > heirarchy. It is entirely deterministic, unlike HDLs, it is absolutely not random. I really don't know what problem you are talking about, and I've been doing schematic based designs for over a decade... Perhaps you could elaborate on what you think the problem is???Article: 32010
> The other missing issue, heavily related to the above, is portability. Schematics are pretty much just as portable as a language. You pick your schematic tool, just like you pick your language. VHDL or Verilog, ViewDraw or OrBAD. I haven't tried it, but isn't there EDIF? I also believe "portability" is entirely over-rated. Even though it is touted as one of the reasons to use HDLs, I know of almost no one who has actually takes advantage of this purported "portability". Some do, so I'm not poo-pooing it, but I just don't believe it is as prolific as the proponents of "portability" make the claim it is.Article: 32011
Hi, I found all the information by looking at the help file for the scfifo, and the notes in the scfifo implementation. Russell Shaw wrote: > > Hi, > > What other signal gates the clock in a 'gated clock' design? > > For LPM_FIFO_DC, to write data, is this correct: > > 1) Apply data to input port > 2) Assert wrreq if not full > 3) Apply a low-to-high edge at wrclock > > How much delay should there be between 2 and 3? A small delay? or whole > clock cycles? > > bob elkind wrote: > > > > Many FPGA/ASIC designers (myself included) avoid gated clocks like the plague. > > The preferred alternative is what is commonly called the "clock enable". > > > > For the LPM_FIFO_DC (we're talkin' MAX+2 here), the rdreq and wrreq are the > > clock enables for the read clock and the write clock, respectively. In the case > > of the LPM_FIFO_DC, these inputs are not optional. If you prefer/insist on using > > gated clocks for read and write, then tie the rdreq and wrreq inputs to 'VCC'. > > > > Hope this helps, Russell! > > > > -- Bob Elkind, the e-team (fpga consulting, etc.) > > > > Russell Shaw wrote: > > > > > To clock data in and out, you just need inclock, outclock, empty, full. > > > Why then rdreq, wrreq? > > > -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 32012
> I suggest that you don't purchase an old technology > development board, when you can buy a brand new > one for < US$120! > > The B3-SPARTAN2+ board from Burch Electronic > Designs has a modern 200K gate Spartan2 device. > http://www.burched.com.au/bedspartan2.html Shameless plug ;-)Article: 32013
The answer is yes, but you'll want to floorplan the tristate drivers. The automatic placement does an exceptionally poor job placing the tristates. There is a limitation, in that only half of the tristates in a particular row can drive a give tristate bus line because of the chip architecture. The tristate bus is 4 bits wide, and is rotated by one bit as it passes each CLB. Each CLB can only get onto the two of the wires in the bus, so you end up having to pattern your drivers to account for this. If you don't floorplan, it makes a ratsnest that is both slow and unnecessarily uses extra resources. Simon Bacon wrote: > Yes. Look at the HDL design guide on the Xilinx Web site. > > > >> is it possible within the Spartan-II devices to instantiate - Verilog - >> tristate busses, as it was possible in earlier Xilinx FPGA's. Actually >> we are near 100% of the largest Spartan-II device, and maybe we could >> get rid off the readback multiplexer for the internal registers using this >> appraoch ... >> >> Any hints help would be appreciated ... >>Article: 32014
> How can I force tristate enable registers into IOBs (xilinx Spartan II) > ? > > The synthesis tool (XST) makes one register out of the following 16 > registers. But I want 16 registers directly in the IOBs ! How can I code > this without using the IOBUFs in the VHDL code ! > > -- generate 16 tristate enable register > gen1: for i in 0 to 16-1 generate > process(clk, reset) > begin > if reset='1' then > ge_mem_oe_reg(i) <= '1'; > elsif rising_edge(clk) then > ge_mem_oe_reg(i) <= ge_mem_oe; > end if; > end process; > end generate; > > -- 16 tristate enable buffer > gen2: for i in 0 to 16-1 generate > GE_MEM_D(i) <= ge_mem_out_reg(i) when ge_mem_oe_reg(i)='0' else 'Z'; > end generate; Use: attribute IOB: string; attribute IOB of ge_mem_oe_reg : signal is "true"; This makes XST to replicate the FFs again after (!) having merged them into one in the final optimization phase. Works great ! TobiasArticle: 32015
Russell Shaw wrote: >Using the Quartus fitter in maxplus2 (for acex1k), it crashes at >28% when doing a simple 32x8 lpm fifo function and not much else >(pc has 256MB ram). By setting the option not to use quartus, the >compilation completes without error. Have you found the same bugginess? I switched off Quartus. After making some minor changes in an existing and working design compiled under older Max (without Quartus) some parts of the design stoped working. -- Pozdrowienia, Marcin E. Hamerla "The value of achievement lies in the achieving"Article: 32016
Burch Electronic Designs announces new monthly e-newsletter, featuring FPGA design tips. Subscribe at http://www.BurchED.com.au ...just type in your email address and press the Subscribe button. It's free. Contents this month: 1. Website news 2. Feature link: Koay Kah Hoe, 8051 Core 3. Feature kit: B3-FSET 4. FPGA tips (1): Synchronous Design - Why? Don't miss out on the FPGA tips! Subscribe now! http://www.BurchED.com.au Tony Burch http://www.BurchED.com.auArticle: 32017
syn_useioff - Is this an XST option ?
Ken McElvain wrote:
>
> Set syn_useioff=1 as a global attribute in your constraint file. This
> will lead to replication of tristate enable FF's automatically. It will
> also put IOB=TRUE on your registers for you.
>
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Article: 32018Austin Franklin wrote: > > The other missing issue, heavily related to the above, is portability. > > Schematics are pretty much just as portable as a language. You pick your > schematic tool, just like you pick your language. VHDL or Verilog, ViewDraw > or OrBAD. I haven't tried it, but isn't there EDIF? > The difference here is that ViewDraw et al are proprietary whereas the 2 major HDLs are public standards. Hence if you stick to the defined synthesisable subset you know that all the tools have to support your code. As to EDIF: Although its useful as a netlist exchange format for tools to pass information its opaque nature makes it no use as a design language [except for that small band of brothers who think LISP is the best thing since ASCII]. Its also *not* a schematic format. > > I also believe "portability" is entirely over-rated. Even though it is > touted as one of the reasons to use HDLs, I know of almost no one who has > actually takes advantage of this purported "portability". Some do, so I'm > not poo-pooing it, but I just don't believe it is as prolific as the > proponents of "portability" make the claim it is. One of the big uses of modern, large, FPGAs is for ASIC prototyping. This is either set explicitly at the start of a project or implicitly when your company suddenly finds its shipping 20K WonderWidgets per month instead of an assumed couple of K. Its an awful lot easier at that point to just throw the HDL at your Vendor & tell them to get on with it than to have to do the technology retargeting yourself. The second place where portability comes in is the entire IP arena. Portability takes some work but with effort its possible to reduce the technology changes to this list: o IO buffer selection. o Clock trees. o DP RAMs. o DLL/PLLs. o Choosing a cell for any clock domain synchronisers. I also notice that you haven't taken up the question re version control & the ability to do a diff between revisions.Article: 32019
This is a multi-part message in MIME format. --------------C77319C808A54D704FF0D5BE Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Stephane wrote: > > Hi, > > I'm studying the following architecture : > > I have an APEX200E with 1 embbeded NIOS microcontroller which runs his > program from an external flash. > The APEX's configuration file beeing contained in his 2 EPC2 > configuration flash PROM. > > My main problem is NIOS and FPGA software update. > > I intend to use JTAG. > > The FPGA's EPC2 would be programmed by their JTAG pins. > The flash memory has no JTAG pins. > So I was wondering if I could program it by driving the FPGA's pins ( > the address, data and control bus pins ) using the FPGA's JTAG > capabilities. > > Does anyone has already done such a thing ? > > Does it works ? > What is the consequence on the JTAG software on the host PC ? > > Thanks in advance. > > Stephane. > Thales Microelectronics. Hi Stephane, here at Rostock University we use such a system to update the configuration PROM of a Virtex-FPGA. We use the boundary scan cells of a CPLD normally used to boot the FPGA from the parallel FLASH to program the FLASH with a new configuration bitstream. Currently we use bit banging on the PC's parallel port as JTAG interface and, of course, it is awfully slow as it takes one LPT access per signal change on the JTAG lines and some fourty or so JTAG clock cycles for one signal change on the FLASH pins (depends on FLASH size). But if you have a more sophisticated JTAG-Interface (e.g. µC, special hardware device like National's SCANPSC100 or homegrown FPGA/CPLD solution) you can compensate for the high number of JTAG clocks per signal change on the FLASH pins with a higher JTAG clock rate. We are currently building such a parallel port - JTAG interface that should give us a 6 MHz JTAG clock, but IIRC higher clock rates up to 10...20 MHz should be possible with most JTAG devices (check the APEX data sheet). So, you see, what you want is possible an , according to the number of replies to your post, has been done many times before. Regards Jens --------------C77319C808A54D704FF0D5BE Content-Type: text/x-vcard; charset=us-ascii; name="jens.hildebrandt.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jens Hildebrandt Content-Disposition: attachment; filename="jens.hildebrandt.vcf" begin:vcard n:Hildebrandt;Jens tel;fax:+49 381 4983601 tel;work:+49 381 4983537 x-mozilla-html:FALSE org:University of Rostock;Dept. of Applied Microelectronics and Computer Science adr:;;Richard-Wagner-Str. 31;Rostock-Warnemuende;;18119;Germany version:2.1 email;internet:jens.hildebrandt@etechnik.uni-rostock.de x-mozilla-cpt:;23728 fn:Jens Hildebrandt end:vcard --------------C77319C808A54D704FF0D5BE--Article: 32020
First of all, thanks to you all for answering. So yes it's possible !! This time the question comes from the software team. As this will be controled by a PC, they would like to know what will be the amount of work to realize a software for programming the system flash, the EPC2 and for testing the APEX which will come in BGA. They argu that all the last experiences in other services were not successful because of the difficulty to create the JTAG sequences. So is it so complex to implement ? Stephane. Thales microelectronics.Article: 32021
Andy - Full support of VHDL'93 generate statements will be available in XST in the next release of the Xilinx tools, due the end of August. Brian. Andy Peters wrote: > OK, so I'm trying to synthesize some VHDL code that simulates fine. Nothing fancy, just some generates to create some registers. > > The synthesizer complains: ERROR : (VHP__0163). Where's the list of errors? Hitting F1 is no help. OK, look at the message: "Unexpected symbol read: BEGIN." > > Wait, this tool doesn't seem to understand the LRM. My generate statement looks like: > > foo: for ff in 0 to 2 generate > begin > bar: process (clk, rst) is > begin > if rst = '1' then > b(ff) <= '0'; > elsif rising_edge(clk) then > b(ff) <= c(ff); > end if; > end process bar; > end generate foo; > > Hmmm..Ashenden sez this is OK; so does ModelSim. So, what's wrong? Does XST support generates? > > Soooo... what's with the online help? Choosing Help->Online Documentation... brings up a web browser (IE only, can't change it) with the following error: > > "WebPACK Online Help. Please invoke the online help system from the Help and Technical Support icon in the Xilinx WebPACK program group." That's annoying. > > So, Choosing the "Help and Technical Support icon" in my WebPACK program group launches the HTML-based Help system. OK, hmmm..I'm doing a 9500XL design in VHDL, but I have no idea what XST supports and does not support. Where are the synthesis tool details? > > Oh, here they are: not under CPLD WebPACK ISE, but rather under FPGA WebPACK ISE->Tools->Synthesis. > > But wait -- there's only one simple page here. First line: "XST is a Xilinx tool that synthesizes HDL designs to create EDIF netlists. For detailed information about XST, refer to the XST User Guide." that's rather useless, so I click the "XST User Guide" hyperlink. > > That apparently runs the web browser within the help browser, connects to the Xilinx web site's "software Manuals Online" section, where I am NOT brought right to the XST User Guide -- which is what any reasonable person would EXPECT -- but rather, the top level of the Xilinx docs. Which still say 3.1i, but aren't they up to 3.3i SP8 or something? > > I click on the Design Entry icon. Wow -- looks like some outdated documentation. > > Ah -- waaaay down on the bottom of the "Docscan" frame, there's an XST link. Ah-ha! There it is. And there's VHDL Support, too. Where's Generate? > > Hmmm...it's under Combinatorial Circuits. Your guess is as good as mine as to why. > > Ah, here's something: I have the keyword BEGIN right after my generate statement (foo : for ff in 0 to 2 generate begin) which is required in VHDL'93 if we include any declarations, but can be omitted if there are none. Emacs seems to put them there, and I like my ENDs balanced by BEGINs. > > But the example in the docs does NOT have the BEGIN, and the synth is happy if I remove it from my code. But I'm not happy, since I have to modify my code to satisfy the quirks of a non-compliant tool. > > OK, so the tools are FREE. What should I expect? > > Well, I expect compliance with the language. Whom does Xilinx think they are, anyway? Synopsys? > > I also expect the documentation to be correct, and it and the tool should be OBVIOUS. If a menu item says, "Online help..." it should bring me directly to online help, not to a static HTML page with no links that says, "find something somewhere else." > > If a link says, "XST User's Guide," I expect it to take me DIRECTLY to the XST user's guide -- not to the top level of docs for everything. > > Xilinx: are you listening? > > --andyArticle: 32022
Brian Gogan <briang@xilinx.com> wrote: >Full support of VHDL'93 generate statements will be available in XST >in the next release of the Xilinx tools, due the end of August. Interesting (and welcome). Can you say anything about any other parts of VHDL'93 you're planning to tackle in the same release? -- IanArticle: 32023
The Atmel FPSLIC can definitely reconfigure itself. Contains AVR (nicer core) and 40k FPGA. 5k and 10 k FPGAs are out of the mask shop will be here "real soon". System Designer 2.0 with Win2k support will be shipping withing weeks. -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel Sweden "Miguel Arias" <ariasm@inaoep.mx> skrev i meddelandet news:ad5d52be.0106081408.63db47b7@posting.google.com... > Hello, > > I am planning an application where I need a remote FPGA based > architecture which I want to reconfigure using a microcontroller. The > Triscend E5 CSoc (8051 + FPGA) specifications seem very interesting > since all resides in a single chip but, is it possible to reconfigure > the FPGA part of the chip using a program in the internal > microcontroller? > > Based on the specifications, reconfiguration goes through the JTAG > input, which I could control using the PIOs of the E5, but for > security reasons, I would prefer to find out an internal way to do > this, is it possible? > > Thanks for any comments with a copy to my email. > > Miguel > FPGAs for Computer Vision > INAOE - Mexico
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