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Andy, It does a generate, but like you note, only without the begin statement, which means of course that you can't use any local signals, constants or attributes either. As far as I can see, that makes it just about useless (especially considering that I use generates to do placed structural construction). XST stands for Xilinx's Synthesis Toy, I do believe. I guess you haven't run into the deal with generics yet either...only integers. Sad part is there are customers out there who insist on using it because it is free. What they don't realize is the additional engineering time (for a non-hobby and non-academic application) required to work around all the unsupported stuff cost way more than the good tools such as Synplify or Leonardo cost (not that those are priced affordably, but thats another cup of tea). Andy Peters wrote: > > OK, so I'm trying to synthesize some VHDL code that simulates fine. Nothing fancy, just some generates to create some registers. > > The synthesizer complains: ERROR : (VHP__0163). Where's the list of errors? Hitting F1 is no help. OK, look at the message: "Unexpected symbol read: BEGIN." > > Wait, this tool doesn't seem to understand the LRM. My generate statement looks like: > > foo: for ff in 0 to 2 generate > begin > bar: process (clk, rst) is > begin > if rst = '1' then > b(ff) <= '0'; > elsif rising_edge(clk) then > b(ff) <= c(ff); > end if; > end process bar; > end generate foo; > > Hmmm..Ashenden sez this is OK; so does ModelSim. So, what's wrong? Does XST support generates? > > Soooo... what's with the online help? Choosing Help->Online Documentation... brings up a web browser (IE only, can't change it) with the following error: > > "WebPACK Online Help. Please invoke the online help system from the Help and Technical Support icon in the Xilinx WebPACK program group." That's annoying. > > So, Choosing the "Help and Technical Support icon" in my WebPACK program group launches the HTML-based Help system. OK, hmmm..I'm doing a 9500XL design in VHDL, but I have no idea what XST supports and does not support. Where are the synthesis tool details? > > Oh, here they are: not under CPLD WebPACK ISE, but rather under FPGA WebPACK ISE->Tools->Synthesis. > > But wait -- there's only one simple page here. First line: "XST is a Xilinx tool that synthesizes HDL designs to create EDIF netlists. For detailed information about XST, refer to the XST User Guide." that's rather useless, so I click the "XST User Guide" hyperlink. > > That apparently runs the web browser within the help browser, connects to the Xilinx web site's "software Manuals Online" section, where I am NOT brought right to the XST User Guide -- which is what any reasonable person would EXPECT -- but rather, the top level of the Xilinx docs. Which still say 3.1i, but aren't they up to 3.3i SP8 or something? > > I click on the Design Entry icon. Wow -- looks like some outdated documentation. > > Ah -- waaaay down on the bottom of the "Docscan" frame, there's an XST link. Ah-ha! There it is. And there's VHDL Support, too. Where's Generate? > > Hmmm...it's under Combinatorial Circuits. Your guess is as good as mine as to why. > > Ah, here's something: I have the keyword BEGIN right after my generate statement (foo : for ff in 0 to 2 generate begin) which is required in VHDL'93 if we include any declarations, but can be omitted if there are none. Emacs seems to put them there, and I like my ENDs balanced by BEGINs. > > But the example in the docs does NOT have the BEGIN, and the synth is happy if I remove it from my code. But I'm not happy, since I have to modify my code to satisfy the quirks of a non-compliant tool. > > OK, so the tools are FREE. What should I expect? > > Well, I expect compliance with the language. Whom does Xilinx think they are, anyway? Synopsys? > > I also expect the documentation to be correct, and it and the tool should be OBVIOUS. If a menu item says, "Online help..." it should bring me directly to online help, not to a static HTML page with no links that says, "find something somewhere else." > > If a link says, "XST User's Guide," I expect it to take me DIRECTLY to the XST user's guide -- not to the top level of docs for everything. > > Xilinx: are you listening? > > --andy -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32076
I made an Atmel carry-select adder macro for 16-bit operands for AT40K, speed -2, and it checked in at 25ns or so, just a couple of ns shy of the ripple adder's check-in time. My question is whether the 25ns check-in time is realistic, or is it based on some impossible signal path?Article: 32077
bob elkind wrote:
>
> Hmmm.... I had no probs with 10.0 (no patch). I wonder if the patch
> may be a problem. Maybe someone else listening in on this thread might
> have some data to help correlate our experiences. Also, I was targeting
> only 6K and Acex1K devices.
Hi,
I had the problem with maxplus2 10.0. I applied the latest patch to
get 10.01, but still get the same problem. The file that causes the
quartus fitter to crash when doing an auto acex1k device is:
INCLUDE "lpm_fifo_dc.inc";
SUBDESIGN fifo
(
data[7..0] : INPUT;
wrreq : INPUT;
rdreq : INPUT;
rdclock : INPUT;
wrclock : INPUT;
q[7..0] : OUTPUT;
rdempty : OUTPUT;
)
VARIABLE
lpm_fifo_dc_component : lpm_fifo_dc WITH (
LPM_WIDTH = 8,
LPM_NUMWORDS = 32,
LPM_WIDTHU = 5,
LPM_SHOWAHEAD = "OFF",
LPM_HINT = "USE_EAB=ON"
);
BEGIN
rdempty = lpm_fifo_dc_component.rdempty;
q[7..0] = lpm_fifo_dc_component.q[7..0];
lpm_fifo_dc_component.rdclock = rdclock;
lpm_fifo_dc_component.rdreq = rdreq;
lpm_fifo_dc_component.wrclock = wrclock;
lpm_fifo_dc_component.wrreq = wrreq;
lpm_fifo_dc_component.data[7..0] = data[7..0];
END;
--
___ ___
/ /\ / /\
/ /__\ / /\/\
/__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\ \ / Victoria, Australia, Down-Under \ \/\/
\__\/ \__\/
Article: 32078Ray Andraka wrote: > > Andy, > > It does a generate, but like you note, only without the begin statement, which > means of course that you can't use any local signals, constants or attributes > either. As far as I can see, that makes it just about useless (especially > considering that I use generates to do placed structural construction). XST > stands for Xilinx's Synthesis Toy, I do believe. I guess you haven't run into > the deal with generics yet either...only integers. > > Sad part is there are customers out there who insist on using it because it is > free. What they don't realize is the additional engineering time (for a > non-hobby and non-academic application) required to work around all the > unsupported stuff cost way more than the good tools such as Synplify or Leonardo > cost (not that those are priced affordably, but thats another cup of tea). I understand that XST came from a product that Xilinx bought a while back. I vaguely remember a compilier that came with Foundation before they started shipping FPGA Express. If I remember correctly, it was Metamore. Anyone know if this is correct? Is this the tool that became XST? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 32079
This is a multi-part message in MIME format. ------=_NextPart_000_0183_01C0F3F2.25A59E20 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi, I am using Altera PCI developement Kit (PCI-BOARD/A4E) but I can not manage to reconfigure it by FLASH or JTAG? Could you please help me how I can configure APEX device by JTAG? Regards Servan Uzun ------=_NextPart_000_0183_01C0F3F2.25A59E20 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 5.50.4616.200" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff>Hi,<BR><BR>I am using Altera PCI developement = Kit=20 (PCI-BOARD/A4E) but<BR>I can not manage to reconfigure it by FLASH or=20 JTAG?<BR><BR>Could you please help me how I can configure APEX device=20 by<BR>JTAG?<BR><BR><BR>Regards<BR>Servan Uzun<BR> <DIV><FONT face=3DArial size=3D2></FONT> </DIV></BODY></HTML> ------=_NextPart_000_0183_01C0F3F2.25A59E20-- -- Posted from [193.140.75.9] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 32080
In article <3B2498DD.1E08A0C5@xilinx.com>, briang@xilinx.com says... > Andy - > > Full support of VHDL'93 generate statements will be available in XST in the next release of > the Xilinx tools, due the end of August. > > Brian. > Could you add support for the 'range attribute too? Usually, someting like B <= (B'range => '0') is not accepted by XST. Thanks -- Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.itArticle: 32081
Brian Gogan wrote: > Andy - > > Full support of VHDL'93 generate statements will be available in XST in the next release of the Xilinx tools, due the end of August. > > Brian. > ... and support for Verilog-2000 ?Article: 32082
On Tue, 12 Jun 2001 13:35:21 +0200, Matthias Fuchs <matthias.fuchs@esd-electronics.com> wrote: >Tobias Stumber wrote: >> Use: >> attribute IOB: string; >> attribute IOB of ge_mem_oe_reg : signal is "true"; >> This makes XST to replicate the FFs again after (!) having merged them into >> one in the final optimization phase. >> Works great ! >> >> Tobias >Hi, > >I tried to attach the IOB attribute but it did not work ! Even if I >instanciate FlipFlop components(FD) by hand, they are optimized away and >a single flop drives 16 tristate signals. I also tried the max_fanout >attribute: > >attribute max_fanout : integer; >attribute max_fanout of ge_mem_tri_reg : signal is 1; > >.. same result ! > >What is wrong ? > I had a veariety of problems doing this same thing with Leonardo Spectrum: Solving only one of them didn't yield the result; I needed to fix all of them. From memory: the IOB tristate signal is active-low it has to be registered, explicitly (I used a generate statement) I had to apply "preserve_signal" attributes to it (Leonardo respects this attribute, under certain conditions; don't know about XST) (I think:) the registers had to have NO explicit "reset" signal One thing I found poor was the diagnostics. Leonardo would ignore constraints without giving a reason why it couldn't implement the constraint. Which meant more digging to find out why. - BrianArticle: 32083
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Hi, have a look in this manual. http://www.digilent.cc/XLAusersmanual.pdf You should use the tool Hardware debugger in the Foundation series to download to the FPGA. The difference between FPGA and CPLD (and other things about programmable logic) is explained in a good way here http://www.optimagic.com/faq.html Hope this helps. /Thomas Noddy wrote: > > Hi, > > I have reverse engineered the Digilab kit with the Spartan XL on it... does > not look like the normal Parallel schematic. Anyway, my basic question is > firstly, what is the difference between CPLD and FPGA, and secondly, since I > have the XCS10XL FPGA, must I only use the FPGA header on the parallel > cable? If so, can I still use the JTAG Programmer utility in the Xilinx > Foundation series because as of yet I cannot get my FPGA to program. > Otherwise, how do I do it? > > Thanks > > NewbieArticle: 32085
Hello, can someone tell me how to drive the clock input (wr_clk) of a Block Ram based FIFO without using GCLK inputs in Xilinx´s XC2S50. My design contains four FIFOs, each driven by an individual WR_CLK, and one RD_CLK that is common to all FIFOs. Therefore I have five clocks incoming directly from the outside, but only four GCLK inputs. The RD_CLK is fast and is also used in many other parts, so it should be supplied from one GCLK input, but all four WR_CLKs are much slower and drive only the FIFOs, so they could be supplied from other inputs. The Mapper of Xilinx Foundation 3.1i doesn´t accept clocks for the FIFOs incoming from other Pins than GCLK. Is there any method or trick for realizing these requirements? Thanks in advance for every hint. Heinrich Fonfara Fraunhofer IBMT 66386 St. Ingbert GermanyArticle: 32086
Russell,
bad news, it works for me.
report file excerpts below -- Bob Elkind
==================================================
here's an excerpt of the report file summary:
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
fifo EP1K10TC100-1 12 9 0 256 2 % 106 18 %
User Pins: 12 9 0
here's the compilation settings section of the report file:
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:03
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:01
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:10
Russell Shaw wrote:
> bob elkind wrote:
> >
> > Hmmm.... I had no probs with 10.0 (no patch). I wonder if the patch
> > may be a problem. Maybe someone else listening in on this thread might
> > have some data to help correlate our experiences. Also, I was targeting
> > only 6K and Acex1K devices.
>
> Hi,
>
> I had the problem with maxplus2 10.0. I applied the latest patch to
> get 10.01, but still get the same problem. The file that causes the
> quartus fitter to crash when doing an auto acex1k device is:
>
> INCLUDE "lpm_fifo_dc.inc";
>
> SUBDESIGN fifo
> (
> data[7..0] : INPUT;
> wrreq : INPUT;
> rdreq : INPUT;
> rdclock : INPUT;
> wrclock : INPUT;
> q[7..0] : OUTPUT;
> rdempty : OUTPUT;
> )
>
> VARIABLE
>
> lpm_fifo_dc_component : lpm_fifo_dc WITH (
> LPM_WIDTH = 8,
> LPM_NUMWORDS = 32,
> LPM_WIDTHU = 5,
> LPM_SHOWAHEAD = "OFF",
> LPM_HINT = "USE_EAB=ON"
> );
>
> BEGIN
>
> rdempty = lpm_fifo_dc_component.rdempty;
> q[7..0] = lpm_fifo_dc_component.q[7..0];
> lpm_fifo_dc_component.rdclock = rdclock;
> lpm_fifo_dc_component.rdreq = rdreq;
> lpm_fifo_dc_component.wrclock = wrclock;
> lpm_fifo_dc_component.wrreq = wrreq;
> lpm_fifo_dc_component.data[7..0] = data[7..0];
> END;
>
> --
> ___ ___
> / /\ / /\
> / /__\ / /\/\
> /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
> \ \ / Victoria, Australia, Down-Under \ \/\/
> \__\/ \__\/
Article: 32087As I mentioned in previous followup, your source code compiled without problems on my machine. One place to look for clues is the logic synthesis settings section of the report file, and another place to check would be pin assignments (in the .ACF file). -- Bob Elkind, the e-team fpga design, consulting Russell Shaw wrote: > bob elkind wrote: > > > > Hmmm.... I had no probs with 10.0 (no patch). I wonder if the patch > > may be a problem. Maybe someone else listening in on this thread might > > have some data to help correlate our experiences. Also, I was targeting > > only 6K and Acex1K devices. > > Hi, > > I had the problem with maxplus2 10.0. I applied the latest patch to > get 10.01, but still get the same problem. The file that causes the > quartus fitter to crash when doing an auto acex1k device is: > > INCLUDE "lpm_fifo_dc.inc"; > > SUBDESIGN fifo > ( > data[7..0] : INPUT; > wrreq : INPUT; > rdreq : INPUT; > rdclock : INPUT; > wrclock : INPUT; > q[7..0] : OUTPUT; > rdempty : OUTPUT; > ) > > -- rest of design source code snippedArticle: 32088
Hello to the group, I am currently working in FPGA designs. We are now investigating if is possible to upgrade a design. This is an old design which was implemented in a XC5215 FPGA and was built using schematics :-((, the schematics were done using Mentor Graphics tools. This tool generates the EDF file which you use for the build process, we will probably migrate this design to the Spartan II family. But my personal challenge will be to pass them to VHDL. It is a nightmare I know, os I would like to know if someone knows some software to convert to VHDL a EDF file o convert to VHDL a schematic using Mentor tools. There must be something, to pass it to Verilog will do but it much better to VHDL. Maybe the VHDL generated is quite poor but easier to modify than the schematics. Thank you to all in advance. Ulises Hernandez Design EngineerArticle: 32089
With the Xilinx Design Manager you will be able to convert easily your EDF file to a VHD file, but this VHDL file will be difficult to use, because it will perform the design in the technology primitives format (Lut ... FF ...). These vhd file are used to do post-simulation (after P&R). Laurent www.amontec.amontec Ulises Hernandez wrote: > Hello to the group, > > I am currently working in FPGA designs. We are now investigating if is > possible to upgrade a design. This is an old design which was implemented in > a XC5215 FPGA and was built using schematics :-((, the schematics were done > using Mentor Graphics tools. This tool generates the EDF file which you use > for the build process, we will probably migrate this design to the Spartan > II family. But my personal challenge will be to pass them to VHDL. It is a > nightmare I know, os I would like to know if someone knows some software to > convert to VHDL a EDF file o convert to VHDL a schematic using Mentor tools. > There must be something, to pass it to Verilog will do but it much better to > VHDL. Maybe the VHDL generated is quite poor but easier to modify than the > schematics. > > Thank you to all in advance. > > Ulises Hernandez > Design EngineerArticle: 32090
Heinrich Fonfara schrieb: > > Hello, > > can someone tell me how to drive the clock input (wr_clk) of a Block > Ram based FIFO without using GCLK inputs in Xilinx´s XC2S50. My design > contains four FIFOs, each driven by an individual WR_CLK, and one RD_CLK > that is common to all FIFOs. Therefore I have five clocks incoming > directly from the outside, but only four GCLK inputs. The RD_CLK is fast > and is also used in many other parts, so it should be supplied from one > GCLK input, but all four WR_CLKs are much slower and drive only the > FIFOs, so they could be supplied from other inputs. The Mapper of Xilinx > Foundation 3.1i doesn´t accept clocks for the FIFOs incoming from other > Pins than GCLK. > Is there any method or trick for realizing these requirements? > Thanks in advance for every hint. It is possible. Create a new version (or delete all old ones), when doing the systehesis (in the window where you choose your toplevel, FPGA type and package) click the box EDIT SYNTHESIS CONSTRAINTS, then OK. In the Synthesis constraints, go to PORTS. In the first line, set the colum Clock (dont know the aktuacl name, Iam at home now) select DONT USE. Then, select in the row of your read clock and the other clock that should be routed on global clock nets GCLK, leave the one slow write clock unchanged. Now you can drive the this clock signal from any pin without using a global clock net. You should add NET Slow_write_clock_name uselowskewlines; to the UCF of your design, to force the P&R to use low skew line (what else ;-) for this clock net. Good luck. -- MFG FalkArticle: 32091
"Heinrich Fonfara" <heinrich.fonfara@ibmt.fhg.de> wrote in message news:3B277DD3.A588C0A0@ibmt.fhg.de... > Hello, > > can someone tell me how to drive the clock input (wr_clk) of a Block > Ram based FIFO without using GCLK inputs in Xilinx´s XC2S50. My design > contains four FIFOs, each driven by an individual WR_CLK, and one RD_CLK > that is common to all FIFOs. Therefore I have five clocks incoming > directly from the outside, but only four GCLK inputs. The RD_CLK is fast > and is also used in many other parts, so it should be supplied from one > GCLK input, but all four WR_CLKs are much slower and drive only the > FIFOs, so they could be supplied from other inputs. The Mapper of Xilinx > Foundation 3.1i doesn´t accept clocks for the FIFOs incoming from other > Pins than GCLK. > Is there any method or trick for realizing these requirements? > Thanks in advance for every hint. I just did this. You don't need to use global clock lines for fifo clocks--any signal you want to use as a clock will work as long as you instantiate it to the proper clock line on the Block RAM. In my case, I had a CPU data bus reading or writing to a fifo, so I used the read and write lines (INVERTED because the blockRAM clock is active high as opposed to active low bus signals) as clocks. Works great, less filling. Xilinx also has a USELOWSKEWLINES attribute in the UCF that allows you to route these "clock" signals with better signal integrity and skew if speed is an issue. Save the Global clock line for "real" clocks and the mapper should not complain. Hope this helps, Jeff -- *********************************************** Jeffrey Vallier Sr. FW Engineer Gibson Guitar Corp. GMICS Division 1283 F Old Mtn View/Alviso Rd. Sunnyvale, CA 94089 408 734 4394 ***********************************************Article: 32092
I would suspect it is because using rising v. falling edges does not
guarantee exactly 50% of the cycle for each. I.e., there may be a
slightly different rise v. fall time. (When I use both edges, I try to
give myself a "little" more cushion.)
Jason
"Rémi SEGLIE" wrote:
>
> A very good question that I asking myself...
> Sorry, no response.
>
> "Meelis Kuris" <matiku@hot.ee> a écrit dans le message news:
> 3b0e6f9f$1@news.estpak.ee...
> > Hi,
> >
> > In Virtex-II, DCM has outputs clk180, clk2x180 and clkfx180.
> > Why should anybody need them if it's possible just to use falling
> > edge of clock? The same applies to clk270, I can
> > just use falling edge of clk90 instead of it. And this way only 1 clock
> > buffer is needed.
> >
> > Just curious,
> >
> > Meelis
> >
> >
--
Jason T. Wright
The opinions I express are my own ...
unless otherwise indicated!
Article: 32093Hi all, I'm used to XC4000E 5V FPGAs, they work fine near DSP and other 5V stuff in Power Electronics applications (10 Kw DC/AC at 2 kHz, for example). I'm looking for a DSP replacement, and I think that a FPGA integration could reduce space, cost and consume ... but newer FPGAs are 3.3 volts, or 2.5 volts, and so on. Has anyone experience in those lower voltages *near* such noisy environment? Must I isolate the control system with shields of any kind? Thanks in advance, Santiago (sanpab@eis.uva.es). ---- Looking for a DSP in FPGA? Try http://www.dte.eis.uva.es/OpenProjects/OpenDSP/index.htm.Article: 32094
I'm building a differential QPSK encoder using a Xilinx FPGA. I have looked at the data sheets of many off-the-shelf encoder chips, and each one is using a different encoding table. The Intel constelation and differential encoding table is like this : 01 | 11 ----------- 00 | 10 (Current Input) (Current Output) (Next Output) (Phase Shift) ------------------------------------------------------------------------------------------------- 00 00 00 0 00 01 01 -90 (CW) 00 10 10 90 (CCW) 00 11 11 180 01 00 01 -90 (CW) 01 01 11 180 01 10 00 0 01 11 10 90 (CCW) 10 00 10 90 (CCW) 10 01 00 0 10 10 11 180 10 11 01 90 (CCW) 11 00 11 180 11 01 10 90 (CCW) 11 10 01 -90 (CW) 11 11 00 0 The Analog Devices is like this : (Current Input) (Current Output) (Next Output) (Phase Shift) --------------------------------------------------------------------------------------------------- 00 11 11 0 00 01 01 0 00 00 00 0 00 10 10 0 01 11 01 90 01 01 00 90 01 00 10 90 01 10 11 90 11 11 00 180 11 01 10 180 11 00 11 180 11 10 01 180 10 11 10 270 10 01 11 270 10 00 01 270 10 10 00 270 If I use the encoding formula, next output = current input (xor) current output to verify the table data, the Intel table is totally wrong. But the AD table is not 100% correct. The two entries, (01- 11 - 01) and (10 - 11 - 10), should be, (01 - 11 - 10) and (10 - 11 - 01), according to the above formula. In addition, the phase shift part of the AD table is reasonable. But I cannot make any sense out of the Intel phase shift part. What should be the correct table (formula and phase shift) for encoding differential QPSK data ? Can someone shed me some light on this ? Thanks. EdwardArticle: 32095
Hello,
Most of digital scopes have ADCs that are working at a lower sampling
rate than the maximum sampling rate of the scope. This is the reason
why when you have a multichannel scope, you cannot have the same
sampling rate when you are looking at all the channels than when you
are looking at only one channel.
Lets assume you have a 500MS/s ADC (I dont speak about the analog
bandwidth here). This ADC is generating one word every 2ns. You
then have a DLL that has as much taps as your scope has channels
(eg. if you have 4 channels, your DLL will output 4 500MHz clocks
each delayed by 2ns/4=500ps from the previous one).
When you are looking at the 4 channels, all ADCs have the same
synchronous clock and thus you will have 500MS/s. But, when you are
looking at one channel, each ADC receive a delayed clock and their
analog inputs are connected together. This way, you have a kind of
pipeline:
0 500ps 1ns 1.5ns 2ns ...
|--------|--------|--------|---------| ...
ADC1 ADC2 ADC3 ADC4 ADC1
starts starts starts starts outputs data and
conv. conv. conv. conv. starts new conversion
Seen from the input, you have achieved a 2GS/s using 500MHz ADCs.
The ADC digital outputs can be fed to some FIFO to avoid the
need of a 2GHz acquisition system. This is also the reason why
digital scopes used to be so bad for noise analysis. Samples are
stored in FIFO and then during another time frame, the samples
are displayed on the screen. But, these two operation dont occur
at the same time.
Some scopes like the Lecroy ones, have an advanced sampling mode
that allow a higher sampling rate. It is called RIS (Random
Interval Sampling) but I dont know enough about it to be able to
explain it properly.
Hope this helps.
Regards,
Jean-Marie
--
_______________________________________
| |
| Jean-Marie Bussat |
| Lawrence Berkeley National Laboratory |
| 1 Cyclotron Road - MS 50A-6134 |
| BERKELEY, CA 94720 - USA |
| Email: JMBussat@lbl.gov |
| Phone: (510)-486-5687 |
| Fax: (510)-486-5977 |
|_______________________________________|
Article: 32097Rick Collins wrote: > I understand that XST came from a product that Xilinx bought a while > back. I wouldn't be surprised. I'd imagine that synthesis-tool software engineers are highly prized. > I vaguely remember a compilier that came with Foundation before > they started shipping FPGA Express. If I remember correctly, it was > Metamore. Anyone know if this is correct? Is this the tool that became > XST? XST doesn't look like the Metamor tool, which was probably little more than a stop-gap synthesis solution before Xilinx inked the deal with Synopsys for FPGA Express. I still don't get it: Xilinx supplies FPGA Express with their (purchased tools), so why also offer XST? Unless maybe the deal with Synopsys is about to end, and they still want to offer a low-cost synthesis tool. Anyways, I downloaded WebPACK because I'm doing an extracurricular project that needed some sort of PLD. (You know, separation of home and work -- don't work on home projects at work, etc.) -andyArticle: 32098
Laurent Gauch wrote: > > Dear all, > > For a new product, I want to have an USB 2.0 connection to my FPGA. > I am searching a transciever or transciever/controler chip. > Do you now the best way to build an USB 2.0 interface, thinking 'Time To > Market'? > > In the case where I use a transciever and an integrated Serial Interface > Engine do you know where can I find a SIE core for FPGA, or where can I > find some doc about it. My USB project uses a USB microcontroller to do all of the hard work. Quicker cheaper etc. Question for you: do you have a USB 2.0 card in your PC (and software to support it) so you can test your USB gizmo? --aArticle: 32099
"Andy Peters > Rick Collins wrote: > > I vaguely remember a compilier that came with Foundation before > > they started shipping FPGA Express. If I remember correctly, it was > > Metamore. Anyone know if this is correct? Is this the tool that became > > XST? > > XST doesn't look like the Metamor tool, which was probably little more > than a stop-gap synthesis solution before Xilinx inked the deal with > Synopsys for FPGA Express. > and stepped back from VHDL-93 (Metamor) to VHDL-1887 (Synopsys).
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