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Ray Andraka <ray@andraka.com> wrote: > Synplicity 6.2 is "optimizing" an instantiated design. In particular, I > have a design with instantiated Xilinx primitives including a carry > chain. The synthesis is apparently flattening the xilinx primitives and > doing its own optimization on them, which results in a multiplexer > placed between the xorcy and the flip-flop. When I instantiate We've had a terrible time using the startup_virtex component too. Synplify rips it out. Xilinx says don't use it in Virtex(,E,II), but it does save routing resources if you don't care about the speed of gsr. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 32301
Paul Smart wrote: > > Hi All, > > I am looking for a tool to generate fault simulated test vectors > (stuck-at faults) for FPGA devices from Xilinx (Virtex) and Altera > (Apex). Ideally the tool would give a brief analysis of testability > issues with the design when fault coverage is low. This would be to > show our customer that low fault coverage was due to the design. > > Our previous tool vendor for CPLD and smaller FPGA devices has been > Acugen Software (www.acugen.com). These tools accept Jedec, EDIF and > various other back end files. Acugen may eventually be able to provide > this capability for larger FPGA devices. > > We have evaluated TDX from Fluence (www.fluence.com) , but this tool > was designed for use in ASIC design flows. It accepts the Verilog > output files from the Xilinx and Altera tools, but does not currently > model the FPGA primitives and UDPs correctly. Fluence may eventually > provide capability for FPGA devices. > > Since FPGAs are non-scan for the purpose of ATPG, this further limits > the list of potential tools. > > These are our customer's designs, and we are not allowed to alter the > designs for testability purposes. For future designs, I may be able to > convince their designers to use DFT tools. > > Does anyone know of any tools that are suited to this problem? > > Thanks for your time, > Paul Paul, I don't understand, why ASIC ATPG or DFT tools won't work. Did you evaluate DFT Compiler or TetraMax (Synopsys)? With the correct library (I think there is one for Virtex) there should be no problem. Just my 2 Cents. Patrick -- Patrick R. Schulz (mailto:schulz@uni-mannheim.de) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://ra.ti.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 32302
Why is it that in the UK Altera Devices are not only difficult to acquire but are also very expensive? Is this the same in other countries? When you finally manage to find a supplier that'll stock them, you either have to buy them in their "Minimum Order Quantity" - MOQ or in their "Statutory Sub Multiples" - SSMs which represents a complete tube or pack of devices. I only need small quantities for single prototypes and undergraduate student projects. I've been submitting my requests to a company called: http://www.SmallBuys.co.uk They specialise in supplying small quantity orders of virtually ANY product requested. Integrated Circuits seem to dominate their site at present. "SmallBuys" say that they'll place an order themselves when the "total" quantity of devices requested exceeds the Minimum Order Quantity or Statutory Sub Multiple. So if there is anyone in the same predicament as me, PLEASE let's get together and place a composite order via "SmallBuys". Thanks. Bill. William Wallis w_f_wallis@yahoo.co.ukArticle: 32303
On Fri, 22 Jun 2001 08:21:29 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: > > >Allan Herriman wrote: > >> Hey Ray, >> >> I assume you are using Virtex, Virtex-E or Virtex-2. >> >> Did you use the unisim library, or the Synplify specific "virtex" >> library? >> >> In the past I've had problems (with 6.0.0 pro) getting the tool to >> correctly "black box" entities if I was using the virtex library. It >> seems that the names of the primitives are "special-cased" inside the >> tool. My fix was to change over to using the unisim library, which >> then forced synplify to treat the xilinx primitives as true black >> boxes, i.e. it doesn't mess with them. >> >> Regards, >> Allan. > >Did you have to hack the unisims lib in any way e.g. by adding ``syn_black_box'' or will >the `celldefine/`endcelldefine (or VHDL equivalent) get picked up by the synthesiser ? I didn't hack it at all. Every component in unisim_vcomp.vhd (the unisim.vcomponents source) already has the following attribute: attribute BOX_TYPE of <whatever> : component is "BLACK_BOX"; I'm not sure if all (any?) synthesis tools use that attribute though. I guess the only reason I haven't seen Ray's problem is that I'm using Synplify 6.2.3 pro, and I don't do all that much instantiation of xilinx primitives. Like Hamish, I've had problems with Synplify removing the startup block. I never found a portable workaround, and Synplify support suggested that it was a feature, not a bug. The non-portable workaround was to instantiate Synplify's STARTUP_VIRTEX_GSR component. At least I got the results I wanted, even though the code won't work with any other tools. Regards, Allan.Article: 32304
On Fri, 22 Jun 2001 03:44:50 GMT, Ray Andraka <ray@andraka.com> wrote: >It is using the Unisims. I had the same trouble with the synplicity virtex library. Using >the unisims also makes simulation easier. All the components are black-boxed and the >unisims library declaration is removed for synthesis using the pragmas. A snippet of the >code follows. This had worked until now (I just installed 6.2.4 before starting this >design, and the offending adder is part of an existing library I've been using for close to >2 years). Previously, the synthesizer left the black-boxed unisims alone, but now it >doesn't. [snip] One ugly, brute force way around this problem is to create your own library. Copy unisim, and prefix all the entity names with "andraka_" Synplify will definitely treat these as black boxes (at least in this release :) You could then use a script (Perl, etc.) to convert all the andraka_ components in the edif back to their original names. (Look out for duplicate names being created.) Another way would be to compile the entity that has the problem using a version of Synplify that works, save the edif, and then treat the entire entity as a black box. I think that ngdbuild will automatically read in the extra edif. (I haven't done that sort of thing since Xact 6 days, so I'm not sure if it still works.) Regards, Allan.Article: 32305
Hi, in my installation of Synopsys Simulation v2000.12 (sparcOS5) vhdlan can't find the design-ware libs. The settings in .synopsys_vss_setup seem to be correct but if I take a look in the directories where the settings point to I only see broken links. Normally I would ask Synopsys about that - but they don't want universities to do that - so if you have you any ideas... Thanks, AndreasArticle: 32306
On Fri, 22 Jun 2001 14:33:04 +0200, Patrick Schulz <schulz@uni-mannheim.de> wrote: >Paul Smart wrote: >> >> Hi All, >> >> I am looking for a tool to generate fault simulated test vectors >> (stuck-at faults) for FPGA devices from Xilinx (Virtex) and Altera >> (Apex). Ideally the tool would give a brief analysis of testability >> issues with the design when fault coverage is low. This would be to >> show our customer that low fault coverage was due to the design. >> >> Our previous tool vendor for CPLD and smaller FPGA devices has been >> Acugen Software (www.acugen.com). These tools accept Jedec, EDIF and >> various other back end files. Acugen may eventually be able to provide >> this capability for larger FPGA devices. >> >> We have evaluated TDX from Fluence (www.fluence.com) , but this tool >> was designed for use in ASIC design flows. It accepts the Verilog >> output files from the Xilinx and Altera tools, but does not currently >> model the FPGA primitives and UDPs correctly. Fluence may eventually >> provide capability for FPGA devices. >> >> Since FPGAs are non-scan for the purpose of ATPG, this further limits >> the list of potential tools. >> >> These are our customer's designs, and we are not allowed to alter the >> designs for testability purposes. For future designs, I may be able to >> convince their designers to use DFT tools. >> >> Does anyone know of any tools that are suited to this problem? >> >> Thanks for your time, >> Paul >Paul, > >I don't understand, why ASIC ATPG or DFT tools won't work. >Did you evaluate DFT Compiler or TetraMax (Synopsys)? >With the correct library (I think there is one for Virtex) there should >be no problem. > > >Just my 2 Cents. > >Patrick Hi Patrick, Thanks for your reply. I called Synopsys about a month ago and they said the Tetramax tool is not set up to work with FPGA, and they have no intention at this time of making it work with FPGAs. PaulArticle: 32307
I haven't done anything recently with the start-up component, but I have been
putting in the ROC component without problems (this is the one that does the
internal global reset). The trick here is that _all_ inferred registers have
to have a global reset term. Instantiated registers do not need the global
reset term, since synpicity doesn't know they are registers (at least not
before it started optimizing the primitive instantiations). Last time I tried
this with the startup component I had a bear of a time getting it to stick.
IIRC, the way I finally got it to work was to put in both the start-up and the
ROC, which is not the way it is supposed to work.
-- Component declaration of the "roc(roc_v)" unit
-- File name contains "roc" entity: .\src\unisim_vital.vhd
component roc
--synthesis translate_off
generic(
WIDTH : TIME := 100.0 ns);
--synthesis translate_on
port(
O : out std_ulogic);
end component;
attribute syn_black_box of ROC:component is true;
begin
POC:roc port map(
O=> global_reset);
process(clk,global_reset)
begin
if global_reset='1' then
adc_clk_iob<='0';
elsif clk'event and clk='1' then
adc_clk_iob<=adc_clk;
end if;
end process;
hamish@cloud.net.au wrote:
> Ray Andraka <ray@andraka.com> wrote:
> > Synplicity 6.2 is "optimizing" an instantiated design. In particular, I
>
> > have a design with instantiated Xilinx primitives including a carry
> > chain. The synthesis is apparently flattening the xilinx primitives and
>
> > doing its own optimization on them, which results in a multiplexer
> > placed between the xorcy and the flip-flop. When I instantiate
>
> We've had a terrible time using the startup_virtex component too.
> Synplify rips it out. Xilinx says don't use it in Virtex(,E,II),
> but it does save routing resources if you don't care about the
> speed of gsr.
>
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
Article: 32308I ended up having to put syn_black_box attributes on the component declarations in my code. I didn't have to hack the unisims. I specifically sought a solution that would not require hacking the unisims because I don't want the headaches that would bring with keeping a special version of unisims. Allan Herriman wrote: > On Fri, 22 Jun 2001 08:21:29 +0100, Rick Filipkiewicz > <rick@algor.co.uk> wrote: > > > > > > >Allan Herriman wrote: > > > >> Hey Ray, > >> > >> I assume you are using Virtex, Virtex-E or Virtex-2. > >> > >> Did you use the unisim library, or the Synplify specific "virtex" > >> library? > >> > >> In the past I've had problems (with 6.0.0 pro) getting the tool to > >> correctly "black box" entities if I was using the virtex library. It > >> seems that the names of the primitives are "special-cased" inside the > >> tool. My fix was to change over to using the unisim library, which > >> then forced synplify to treat the xilinx primitives as true black > >> boxes, i.e. it doesn't mess with them. > >> > >> Regards, > >> Allan. > > > >Did you have to hack the unisims lib in any way e.g. by adding ``syn_black_box'' or will > >the `celldefine/`endcelldefine (or VHDL equivalent) get picked up by the synthesiser ? > > I didn't hack it at all. Every component in unisim_vcomp.vhd (the > unisim.vcomponents source) already has the following attribute: > attribute BOX_TYPE of <whatever> : component is "BLACK_BOX"; > I'm not sure if all (any?) synthesis tools use that attribute though. > > I guess the only reason I haven't seen Ray's problem is that I'm using > Synplify 6.2.3 pro, and I don't do all that much instantiation of > xilinx primitives. > Like Hamish, I've had problems with Synplify removing the startup > block. I never found a portable workaround, and Synplify support > suggested that it was a feature, not a bug. > The non-portable workaround was to instantiate Synplify's > STARTUP_VIRTEX_GSR component. At least I got the results I wanted, > even though the code won't work with any other tools. > > Regards, > Allan. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32309
thanks ray for the reply i am not familiar with this algorithm, any reference please thanks H.S Ray Andraka <ray@andraka.com> wrote in message news:<3B31FE02.6CC1E8B0@andraka.com>... > The 16 bit FFT is a kernel that can be used for larger (powers of 16) > FFTs. If you look at the FFT, it can be decomposed into smaller FFTs > using the mixed radix algorithm. The decomposition consists of a data > reordering and a phase rotation of the intermediate results. We currently > are one of the vendors offering a shrink-wrapped 16 point core. We have > used that core for some very high speed 256 point and 4K point FFTs. For > those, the block RAM speed is the limiting factor. Our 16 point core is > more compact and faster than our competitor's cores because we do not use > radix 4 kernels to construct the core. > > We do have a phase rotator and reordering address generators available > too, but they are not in state for general sale yet. > > finish wrote: > > > hello, > > > > From my modest background, i know that for performing the FFT > > transform on an input signal, i have to extend it, if required, by > > zeros to 2^n. > > FFT is a global transform,i.e the whole input sequence should be > > available. > > > > In practise, most often we take 1024 or 512, but i see some commercial > > hardware implementation for just 16 input data. > > > > How far will this limited input size transform affect the overall > > performance ? > > > > thanks > > > > H.SArticle: 32310
William Wallis wrote: > > Why is it that in the UK Altera Devices are not only > difficult to acquire but are also very expensive? No they're not, they're about the same as Xilinx devices. I've been able to buy small quantities (<5 of) of EPM7128S and EP1K30 from Impact Memec (from the Altera distributors web page). This has been done through my company and personally before the company was set up. I was able to buy from Impact on a personal credit card. Altera have recently moved from Impact to Arrow and EBW as distributors in the, I _hope_ they will continue the same arrangement. Have you tried them? Nial. I wonder if this is a plug for 'small buys'?Article: 32311
I haven't been able to locate the CoolRunner libraries in neither my Synopsys FPGA Compiler II (FC2) or Alliance 3.2iSP8 installations (both Solaris). I assumed these filenames would contain any of the substrings xpla3, xcr3, or cool. But I did not find any files with these names (exept some cool names for some FC2 executable libraries). Are there any FC2 or Alliance libraries available for the CoolRunner? If yes, where can the be located or obtained? TIA Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 32312
> > what's wrong with, reg [7:0] ram[255:0]; ? > Nothing. Except the intermediate variable you need to take a slice of the slice of the RAM. Which is no big deal, just more convoluted. And that still does not allow variable indexing of the RAM. BrianArticle: 32313
Hi Matthias, > you should try the Xilinx WebPack Software. It's free and it supports > all Xilinx CPLDs and SpartanII FPGAs. It comes with full VHDL and > Verilog support. You can also use a special version of ModelSim. > > Matthias Virtex 300E and Virtex II ( up to 250k ) are also supported. michael strothjohannArticle: 32314
Lasse - haven't you ever wanted to just access one bit of a ram word? I think that's the issue here. lsbs <= ram[138][3:0]; msbs <= ram[138][7:4]; I'm loving what Verilog-2001 is bringing to the table. Lasse Langwadt Christensen wrote: > what's wrong with, reg [7:0] ram[255:0]; ? > > -Lasse > -- Lasse Langwadt Christensen, > -- A Dane in Phoenix, ArizonaArticle: 32315
I'm just starting off with Webpack ISE and want to implement a counter in an XC9572. I'm using the schematic editor and joining the blocks together, as it were, and this is a really elegant way of doing things, but I have some questions about how to accomplish certain things. I'm new at playing with this (try "just got it this afternoon and I've got one day to do all of this gee what fun") so please bear with me about what might seem obvious to you, but new ground to me: 1) With the ADD SYMBOL action (F2), I see a list of building blocks to choose from, but I can't seem to find exactly where the function and pin definitions are. For example, I can see that a CB8CE is a Counter Binary 8-bit with Clear and Enable by looking at the block diagram, but when I look at the TC and CEO pins, I'd feel more comfortable if I knew the exact definitions of their functions. I'm assuming TC is a carry input and CEO is the carry output, but that's an assumption. Doesn't seem to be any definitions file for these library objects anywhere, so can anyone point me in the right direction in this regard? How do I inspect the formal definitions? 2) One of the other chips on my test board is a 22V10, being used as an address decoder. I've done this the old fashioned way with WinCUPL and the equations below: /** Inputs **/ PIN [3..7,9..13,16,27,26] = [A0..A4,A16..A23]; /* System addresses A0 - A23 */ PIN 2 = !AES; /* Address Enable Strobe */ /** Outputs **/ PIN 17 = !CE0; /* SRAM BANK 0 */ PIN 18 = !CE1; /* SRAM BANK 1 */ PIN 19 = !CE2; /* SRAM BANK 2 */ PIN 20 = !CE3; /* SRAM BANK 3 */ PIN 21 = !ETH; /* ETHERNET CONTROLLER */ PIN 23 = LCD_EN; /* LCD ENABLE LINE */ PIN 24 = LATCHES; /* OUTPUT LATCHES */ PIN 25 = LCD_RS; /* LCD REGISTER SELECT */ /** Declarations and Intermediate Variable Definitions **/ /** IMPORTANT NOTE: Memory Bank sizes are for the CY62128L 128kx8 SRAM **/ field IOADDR = [A23..A16, A4..A0]; BANK0 = IOADDR:[200000..21FFFF]; BANK1 = IOADDR:[220000..23FFFF]; BANK2 = IOADDR:[240000..25FFFF]; BANK3 = IOADDR:[260000..27FFFF]; ETHERNET = IOADDR:[400000..40000E]; AUX_IO = IOADDR:[600000]; /** Logic Equations **/ CE0 = AES & BANK0; CE1 = AES & BANK1; CE2 = AES & BANK2; CE3 = AES & BANK3; ETH = AES & ETHERNET; LATCHES = AES & AUX_IO; As you can see, nothing much in it. Now what I'd like to do is throw away the 22V10, and instead "insert" this address decoder into a corner of the new XC9572 design. But I'd also like to extend the address space for it, so that the original output select lines still go to individual pins to the outside world as before, but now we also have some extra I/O decode lines covering more addresses, which go internally to the blocks I'm adding in the schematic editor. In other words, we still have the six original output decode lines strobing I/O devices outside, but also have say an extra 6 or 12 output decode lines controlling enable inputs or whatever, to the counter elements I'm designing in the main part of the XC9572 How do I do this? My hunch is that I can take the WinCUPL equations above and somehow create a library block or element which I then place into the Schematic Editor and run wires and buses to just like I'm doing with the blocks I'm taking from ECS_CPLD.lib. Is this the case? If so, how do I do this, and if not, what is the correct procedure? 3) How do I assign the chip's pins to the buses and wires I've got going into/coming out of the blocks? I've tried adding an I/O marker to the end of wires and buses which already have labels on them but it doesn't work. Due to my being thrown into the deep end on this as a rush job, I'm sure the answers to all the above are in the on-line help, but I don't have the luxury of time to read it from front to back, so I'm asking for any help to get me up and running quickly - just the stuff I need to know for now, as it were. Any help appreciated. I'll go into guru mode later - for now all I need is a simple counter for measuring +ve and -ve pulse widths, and some I/O decode to get at it all.Article: 32316
The mixed radix algorithm is described in most texts with discussion of the FFT. There is an on-line FFT demystified page, linked to from my website, that has a brief discussion of the algorithm and the math involved. For more complete discussion you might try an FFT text such as "Handbook of Realtime Fast Fourier Transforms" by Smith and Smith (available through the bookstore on my site). finish wrote: > thanks ray for the reply > i am not familiar with this algorithm, any reference please > thanks > > H.S > > Ray Andraka <ray@andraka.com> wrote in message news:<3B31FE02.6CC1E8B0@andraka.com>... > > The 16 bit FFT is a kernel that can be used for larger (powers of 16) > > FFTs. If you look at the FFT, it can be decomposed into smaller FFTs > > using the mixed radix algorithm. The decomposition consists of a data > > reordering and a phase rotation of the intermediate results. We currently > > are one of the vendors offering a shrink-wrapped 16 point core. We have > > used that core for some very high speed 256 point and 4K point FFTs. For > > those, the block RAM speed is the limiting factor. Our 16 point core is > > more compact and faster than our competitor's cores because we do not use > > radix 4 kernels to construct the core. > > > > We do have a phase rotator and reordering address generators available > > too, but they are not in state for general sale yet. > > > > finish wrote: > > > > > hello, > > > > > > From my modest background, i know that for performing the FFT > > > transform on an input signal, i have to extend it, if required, by > > > zeros to 2^n. > > > FFT is a global transform,i.e the whole input sequence should be > > > available. > > > > > > In practise, most often we take 1024 or 512, but i see some commercial > > > hardware implementation for just 16 input data. > > > > > > How far will this limited input size transform affect the overall > > > performance ? > > > > > > thanks > > > > > > H.S -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32317
Im sure this is probably the most basic of questions, but:
Im interested in using the unisim library withour Virtex and VirtexE
parts.
From what I understand, I need a vhdl file with the behavioral
description of each of the macros (for simulation) which I then disable
using pragmas in synplify. The black boxes then get caried down to the
foundation tools, and get mapped at that time. -- Let me know if Im
off base here,
Anyway, the question is: Where do I get the vhdl file(s) which contain
the library? I could not find them on the foundation CD, nor in my
synplify install (I wasnt expecting them in synplify but just for
completeness... ) Do I need to use coregen to make them? How is that
done? I seem to be snagged here.
Thanks!
--
_____ _____
___ | | __ |
|___| | --| -|
|_____|__|__|
Article: 32318This is not only simple, it's trivial: Just divide by 16. That takes a 4-bit binary counter. VHDL... :-( Peter Alfke, Xilinx Applications ====================================== mjd001 wrote: > Hi, > I am currently testing a VHDL design that derives a 2.048 MHz clock from > the 32.768 Mhz source. Below is a snippet of the code I am using. the part > is a Xilinx XC2S100: > > -- > -- 2.048 MHz clock generator > -- > process(clk_reset,cnt1,clk_32768khz) > begin > if (clk_32768khz'event and clk_32768khz='1') then > if (clk_reset='0') or (cnt1=7) then > cnt1<=0; > else > cnt1<=cnt1+1; > end if; > end if; > end process; > > process (clk_reset,cnt1,clk_32768khz,clk_2048khz) > begin > if (clk_32768khz'event and clk_32768khz='1') then > if (clk_reset='0') then > clk_2048khz<='0'; > elsif (cnt1=7) then > clk_2048khz<=not(clk_2048khz); > end if; > end if; > end process; > > I have done this many times before, is this the best way to create a clock? > Could some one comment on this and is there a better design that is > technology independent?Article: 32319
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Article: 32320John_H wrote: > Lasse - haven't you ever wanted to just access one bit of a ram word? I > think that's the issue here. > > lsbs <= ram[138][3:0]; > msbs <= ram[138][7:4]; > > I'm loving what Verilog-2001 is bringing to the table. > > ... but not necessarily the EDA vendors. Like Bob Elkind's Win2K thing I'd like to do a survey of which Verilog synth/simulator vendors have implemented V2K, how completely, and when they intend full compliance.Article: 32321
qlyus schrieb: > > > For four V3200Es and a V1000E, 10min is normal for Parallel Cable III, as I > figure. I did not record the time for our 4 V2000Es. But I think it is > close to about 5min. Hmm, my Spartan II 100 takes about 5.6 seconds (didnt measure it, just the feeling) for 780kbits. With the old MultiLinks (serial) cable, it takes about 16 seconds (did measure it) @115kbaud. > > > 1) Would the download time be any faster if I used the standard > > configuration chain (DIN/DOUT/CCLK/etc) vs. using the JTAG chain? > > I do not know, but one thing is sure, it would be much faster if the devices > are loading from EEPROMs, even in serial mode with default 4MHz. > > > > > 2) Would the download time be any faster if I used the USB-based > > Multilinx cable instead of the Parallel Cable? > > It would be 10 times slower than Parallel Cable III. ????????? Sure? Xilinx says that it runs full speed 12 Mbit/s (I hope they dont mean the burst data rate on USB) I would think the USB is MUCH faster (but I dont have one). -- MFG FalkArticle: 32322
mjd001 schrieb: > > Hi, > I am currently testing a VHDL design that derives a 2.048 MHz clock from > the 32.768 Mhz source. Below is a snippet of the code I am using. the part [VHDL stuff] Why dont you simply use the 3rd bit of your counter as your 2.048 MHz clock? The second process is useless. -- MFG FalkArticle: 32323
Hello folks, I have a xc95288-10 in a design and I would like to divide a 155.52 MHz (yes its STM-1) clock signal down to 38.88 MHz (just divide by four). The counter can be a ripple one. But the datasheet says, it is not possible, even if I go to speedgrade -6 (minimum pulse width 3.3 ns). The duty cycle of the 155.52 MHz signal is not perfectly 50%, but something like 40% can be guarantied I think. Do you think it is possible (AND reliable). The datasheet of the smalles device (9536XL) says something about 2.2 ns minimum pulse width, so I think if I just have 1 FF on the fast clock net, this 2.2ns can also be achieved with the big device?!! The XV family is no option, also another FPGA/CPLD family. Is there also a way to feed the 155.52 MHz signal, which is LVPECL, directly to the CPLD?. Why dont the CPLDs have the nice IOBs of the FPGAs (with LVPECL option)?? -- MFG FalkArticle: 32324
"Jeffrey Vallier" <jvallier@gibson.com> wrote in message news:<BH6V6.28 > Welcome to the world of Xilinx :) In an unusual defensive stance for Xilinx, > I should let you know I met with the team leader for the Webpack project a > few weeks ago to discuss my _long_ list of gripes with the tool. They were > sincerely interested in listening to customer comments, so we should see > some improvements down the road... > > cheers, > > Jeff I hope you also gave them an earful regarding the crippleware Testbench and simulation software they bundle with their software. My company purchased Foundation ISE for around a grand, I get my first project done, compiling cleanly, generally looking good. I go to write the testbench for it and, "Oh, sorry, I can't save that because your design is too big....time to pony up more $$$ for our real software." I suppose their version of Modelsim is similarly crippled. Coming from Max+Plus II land this was a real shock. More $ - Hmm, maybe it's time to consider Altera or Actel. Regards, Steve
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