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In article <3B3912E1.A228A7D4@xilinx.com>, Austin Lesea
<austin.lesea@xilinx.com> writes
>Gary,
>
>It may also be a signal integrity problem. Ground bounce causing double
>clocking, bad input value, etc.
This sounds like a good line of attack to me.
>This is obvious if you lower supply and it gets better, raise temperature and it
>gets better, or find out you have 1+ volts of overshoot and undershoot
Hard to measure - you need classy equipment, and choosing the right
place for oscilloscope ground is an art in itself. There's an
alternative way to nail it, which requires less skill...
>and add
>virtual ground pins
>(drive unused IO's to a '0' with the strongest IO output
>type and ground them externally, creating more ground pins and less ground
>inductance) and the problem also goes
>away.
Another way to alleviate ground bounce problems is to add some series
resistance on device outputs. This prevents the outputs from driving
huge currents into capacitive loads, and so dramatically reduces the
ground bounce. I've fixed many a problem on poorly laid-out or
breadboarded circuits like this. Two gotchas, though:
(1) it's not really a fix, because you have greatly slowed any
outputs that are driving significant capacitance;
(2) the resistance must be as non-reactive as possible (that means
0805 or smaller, surface mount) and positioned VERY close to
the device output pin.
Something like 150 ohms is usually about right.
>To those listening in (and I am not accusing Gary of such a thing): Please
>simulate your IO's with IBIS models and the pcb circuit extraction from layout
>before you build your boards --- it saves so much time later.
Again, you need non-trivial tools to do this!
>Sometimes you have to deal with poor SI (PCI is a good example of a nightmare
>compromise). In these cases, the virtual ground is a life saver.
That one is worth remembering, thanks. It would never have occurred
to me that the impedance through such pins would be low enough to help.
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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Article: 32451I took a look at the patent, and it does not look like a significant issue. The patent seems to cover specific configurations that allow you to combine two LUTs using a mux to implement AND and OR functions among others. But if I understand correctly, if you don't use a mux, then you have a different circuit. I also don't know if this is a valid patent. I have a data sheet from Lucent dated June '99 which clearly shows multiple LUTs connected by muxes. Certainly no one can say it is not obvious to program these muxes to make the two LUTs into a single AND or OR gate. Like, DUH! cyber_spook wrote: > > Being a Fan of Peter I don't wish to upset him... but these are my > views... > > Currently I see the two big guns of the FPGA world finding ways to block > or out do each other just to gain some ground. I don't see how this can > realy benifit us the engineers!? It would however be nice if these idears > were published so that everyone can take advantage for the benifit of the > design. Putting a Paten on the way a gate is implumented is like having a > paten on a type of nut and blot! these are the things we build with to > make our designs. If someone wishes to paten somthing then paten a PCI > funtion block that will do 66Mhz/64Bits in under 100 gates!!! In other > words paten something that is a major break though for the industre and > not the way a gate is implumented. > > Question: If I do this in a Altera chip - Do I have to pay Xilinx? > > I never liked Microsoft - but we were all puched into it - I hope Altera > and Xilinx continue to give us a choise as a monoply firm like Microsoft > will come under the microscope and have the finger pointed at *it* for > not suppling what *we* the designers want! I think compines should > remember that it is us and our pennys that put them up at the top and > things like this just make them look greedy and give a bad impresstion to > its users. > > Regards > > Cyber_Spook_Man -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 32452
cyber_spook wrote: > Being a Fan of Peter I don't wish to upset him... but these are my > views... I sincerely hope we can have contrary views in this newgroup without upsetting anybody. Besides: Peter is known for taking a lot of beating in this newsgroup for things that are not his fault And he still continues with his invaluable support. Kolja SulimmaArticle: 32453
Hi
Has anyone seen the Xilinx application note xapp268? There are several
references in the Virtex-II User guide, but I can't find the actual xapp
anywhere on the Xilinx site. There is also mention of synthesisable
VHDL/Verilog... I am familiar with the DCMs etc, but I'm simply
interested in the Xilinx view.
Thanks in advance
Ian Poole
--
Ian Poole
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: ian.poole@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
**********************************
** Developing design know-how **
**********************************
This e-mail and any attachments are confidential and Doulos Ltd. reserves
all rights of privilege in respect thereof. It is intended for the use of
the addressee only. If you are not the intended recipient please delete it
from your system, any use, disclosure, or copying of this document is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 32456Mike Fisher wrote: Mike, some details of what you want it for wouldn't go amiss. Do you want a compilation tool which would let you debug syntax? A simulation tool that would let you debug your designs functionally? http://www.synphonyeda.com might be of use. Nial.Article: 32458
Nial Stewart wrote: >> http://www.synphonyeda.com Sorry, typo. http://www.symphonyeda.com Nial.Article: 32459
In article <9hb26c$jav$1@slb6.atl.mindspring.net>,
austin@da98rkroom.com says...
>
> > The xilinx
> > mapper will push the FF's to the IOBs if you set the IOB FF's option
> > appropriately provided the rules are met for the IOB FFs.
>
> That's what I do. It is the "pr -b" option to map:
>
> map -pr b filename
I've tried all of the above and it still appears the flops aren't
getting pushed into the IOBs (this is a XCS40XL-BG256). Map reports:
Number of External IOBs 190 out of 224 92%
Flops: 0
Latches: 0
----
Keith
Article: 32460I'm not sure. I think those library elements are left over from schematics. They presume if you are working with an HDL, that you'll be doing this combinatorial stuff in your code rather than instantiating logic. The library elements for things like and2b1, m2_1b2 etc are not built out of xilinx BELs (BELs are the basic elements for the array), and they don't map directly to a LUT. With schematics, you mapped these to a LUT using FMAP components. Anyway, if you included a library that contained RTL code for these, they could be included in your design. Charles Ross wrote: > I see... I was wondering what the differance between Macros and Primitives were, > and now I know.. This helps a lot. For the sake of completeness (and at the risk of > beating a dead horse) I would like to explore many of these various options > (compiled edif, xc_map, using only primitives, etc..) so I can decide which is best > for us, and which results in the most readable designs. I dont see why there would > be any qualitative differance int he resulting bitstreams, so I assume this is all > about readibility and portability of the vhdl? > > I am unable to locate the macros themselves. Meaning that the string "M2_1B2" does > not seem to show up anywhere in any of the vhdl files that came with the foundation > tools... I assume it exists somwhere, otherwise it would be silly to inlude it in > the library guide descriptions. =) Any succestions of which rock to overturn to > find these? > > I am right in thinking that if I just include whatever vhdl file defines this macro, > that it will be expanded in synplify (or modelsim), and my design edif will then > contain the primitive(s) from which this unit is built, and the foundation tools > will then be able to synthesize it? > > -- > _____ _____ > ___ | | __ | > |___| | --| -| > |_____|__|__| -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32461
On Tue, 26 Jun 2001 14:26:09 -0400, "Austin Franklin" <austin@da98rkroom.com> wrote: (snip) > >Xilinx convinced the patent examiner that if was novel and not obvious to >HIM (or HER). Unfortunately, the patent examiners for electronics are NOT >very good. For fishing lures, they are top notch...but no EE who is worth >their salt is going to work for the patent office at $60k/year, when they >can be working in industry and making at least 2x that. Keep that in mind. > > I recently read an issued patent that included a specific claim on N-input OR gates used to accept data from N-sources. I wonder what OR gates were used before this inventor came up with this novel concept... =================================== Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 32462
I believe the macros in the unisim library are left overs from schematic entry. In order to instantiate them, you would have to have linked in the code for them. Use coregen or logiblox instead, as these are parameterized and are more flexible. ENapoli wrote: > Can anyone suggest how to > insert the ADD8 component from the > XilinX unified library in a VHDL design? > > Our target device is the XC4005XL fpga. > > The ADD8 component is a macro and not > a primitive for XC4005XL devices. > As a consequence the straightforward inclusion > of the component ADD8 doesn't work. > > Is it necessary to include the XilinX unified library explicitely? > > Thank you for your attention, > > E. Napoli > University of Napoli -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32463
Hi guys, I have been searching for possibilities to configure Altera devices via JTAG using a small command-line tool. I found something at www.jamisp.com (called jam-player) but this stuff is for win. They have also included the source code and some info about porting this stuff to unix, etc. I put out all my knowlegde about makefiles and managed to create the executable for linux. THE PROBLEM: --> the linux version does not support ByteBlaster, only the BitBlaster is useable!! So, has anyone an idea where to get a ByteBlaster capable linux-jam-player?? Regards, MuffiArticle: 32464
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3B339091.633A1FF8@gmx.de... > I have a xc95288-10 in a design and I would like to divide a 155.52 MHz > (yes its STM-1) clock signal down to 38.88 MHz (just divide by four). > The counter can be a ripple one. But the datasheet says, it is not > possible, even if I go to speedgrade -6 (minimum pulse width 3.3 ns). > The duty cycle of the 155.52 MHz signal is not perfectly 50%, but > something like 40% can be guarantied I think. Do you think it is > possible (AND reliable). > [...] I would suggest that you use a single external D-flop, configured as a T-flop to divide by two. For $0.50, and approximately 0.1 square-inch of PCB real estate (assuming SSOP14 package), your problem is solved. Given that a -6 is going to cost twice as much as a -10, (about $15 more in lower volumes, assuming TQ144), it wouldn't seem to make sense to go to the faster speed grade just to get one fast flip-flop. Just my $0.02. Regards, Erik Widding. -- Birger Engineering, Inc. -------------------------------- 781.481.9233 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.comArticle: 32465
I was told yesterday by a computer retailer that 3" CDROMs (such as the Xilinx Webpack ISE) can cause problems when used in 5" CDROM drives. He said that the 3" cdroms can damage the 5" drive, forcing a replacement and that some manufacturers (Apple) now state that using the 3" cdroms voids the manufacturer's warranty on CDROM drives. Since I just received the 3" Xilinx cdrom I thought I would ask about this potential problem before I tried using the 3" cdroms on my computer. Has anyone had any trouble with their cdrom drives after using them to read 3" cdroms? Thanks, Dave Feustel Fort Wayne, IndianaArticle: 32466
Main reason for this is that the 3" CD can move on the tray and the hole can become unaligned. If this happens, and because of the way the tray mechanism is built in most drives, the spindle axle will push very hard on the disk and break the delicate plastic tray / gear (and damage your disk). Risk is greatly reduced if the 3" plastic groove in the tray is high enough. Another problem with some cheap 3" CD is that some of them are very unbalanced and cause lots of vibrations as they fool some vibration preventing designs. Rectangular "business card" CD that are thicker than regular ones are the worst. However, if you use them with care, it should be Ok. Éric. Dave Feustel wrote: > I was told yesterday by a computer retailer that 3" CDROMs > (such as the Xilinx Webpack ISE) can cause problems when > used in 5" CDROM drives. He said that the 3" cdroms can > damage the 5" drive, forcing a replacement and that some > manufacturers (Apple) now state that using the 3" cdroms > voids the manufacturer's warranty on CDROM drives. Since I > just received the 3" Xilinx cdrom I thought I would ask about this > potential problem before I tried using the 3" cdroms on my computer. > > Has anyone had any trouble with their cdrom drives after using them > to read 3" cdroms? > > Thanks, > > Dave Feustel > Fort Wayne, IndianaArticle: 32467
I have broad shoulders, (but thin skin). So, I can take it, even when it hurts. And I can also admit when I am wrong. This should always remain an open and frank newsgroup. As long as we can keep the weirdos out. Ciao Peter A ======================== Kolja Sulimma wrote: > cyber_spook wrote: > > > Being a Fan of Peter I don't wish to upset him... but these are my > > views... > > I sincerely hope we can have contrary views in this newgroup without > upsetting anybody. > > Besides: > Peter is known for taking a lot of beating in this newsgroup for things that > are not his fault > And he still continues with his invaluable support. > > Kolja SulimmaArticle: 32468
Rick Collins wrote: > > I took a look at the patent, and it does not look like a significant > issue. The patent seems to cover specific configurations that allow you > to combine two LUTs using a mux to implement AND and OR functions among > others. But if I understand correctly, if you don't use a mux, then you > have a different circuit. > > I also don't know if this is a valid patent. I have a data sheet from > Lucent dated June '99 which clearly shows multiple LUTs connected by > muxes. Certainly no one can say it is not obvious to program these muxes > to make the two LUTs into a single AND or OR gate. Like, DUH! > Everyone here seems to think that owning the patent means that you invented the idea. That is not the case in MOST patents. This patent is probably specfic to FPGAs. Sure people have been using this logic construct for a long time, but have they been doing it in an FPGA? I don't know the answer to that, but my point is that a lot of patents are based on well known technology that is applied in novel ways. I'm sure Xilinx would not claim to own the rights to a wide input OR function, but they might be able to claim that their *FPGA* was the first of its kind to contain such a circuit.Article: 32469
I have an application consisting of about 20 SSI/MSI packages using the Cypress CY37000 family and their WARP compiler. So far I have not seen the thing work. Does anyone know if Cypress CPLD, their compiler are any good? Are there some logic designs that just cannot work in anything but discrete packages? David dwright@srtorque.comArticle: 32470
Carrier synchronization and tracking is a huge task. Normally a DSP companion to the ASIC or FPGA is used for this task. There are usually two feedback loops: a course and fine loop. If there is any difference between the transmit carrier and the receive mixing freq, (and there will be), the received constellation will "spin" at a rate of this difference, making decoding impossible. A DSP looking at the received data will attempt to slow the spin by adjusting the PLL generating the receive mixing freq. This is the slow, coarse loop. The DSP will also, in a faster fine loop, adjust the sampling phase of the ASIC/FPGA so that the four samples are centered about the constellation point. If continuous phase changes are made to the fine loop, the slow loop will be adjusted accordingly. The reason there are four receive samples instead of one is so that the synchronizer can work. Without these feedback loops, your receive samples are of little use. "Edward" <edlee@gpetech.com> wrote in message news:3b38eebb.79007306@news.bctel.net... > I'm working on a differential qpsk encoding and decoding system. I > can manage the portions for symbol encoding/decoding, fifo, cpu > interface. However, I am confused on the front end portions of the > receiver, namely the mixing/multiplying, filtering, and symbol > detection of the received digitized baseband rf data. > > The receiver is digitized the rf signal with a 4x clock. There will > be four data samples per symbol for each of I and Q. The previous > symbol is mutliplied with the current symbol for differential > detection. But how do I determine the boundaries of the received > symbols ? I could be using the last data sample of the previous > symbol and the first three data samples of the current symbol and > incorrectly treat the four as one single symbol. With four data > samples per symbol for each of I and Q, how can I level detect the > decision ? Which three samples shall I discard ? > > Thanks. > > > >Article: 32471
> I'm certainly no Guru, but I will try to help you. Thanks, its always nice to hear comments from other people, regardingless of ther GURU-factor ;-) > For the XC95xxXL family of CPLDs all the feedback signals (Output of FFs) > are routed through the FastConnectSwitch Matrix at the center of the > CPLD. > For bigger CPLDs (288 FF) this network is slower than for smaller ones, > since it has to be larger. > A smaller XC9572XL can therefore run at a higher system speed than the > XC95288XL. I know, BUT AFAIK you can configure the FFs in the cells as toggle FFs. That is all I need. Will this work? Even with speed grade -10? > I think you should consider an external prescaler. In this case That is the actual solution (ECL prescaler), but the guys working on the board would like to (have to) reduce power consumption. > you can also connect the clock to the faster Global Clock Net, > which is surely recommendable. Yes, this is an option. > Or you are going to look at CPLD from other vendors. This is NO option for this design. -- MFG FalkArticle: 32472
Erik Widding schrieb: > I would suggest that you use a single external D-flop, configured as a > T-flop to divide by two. For $0.50, and approximately 0.1 square-inch of I hope this is possible with one FF configured as a T-FF. > PCB real estate (assuming SSOP14 package), your problem is solved. > > Given that a -6 is going to cost twice as much as a -10, (about $15 more in > lower volumes, assuming TQ144), it wouldn't seem to make sense to go to the We have TQ144. > faster speed grade just to get one fast flip-flop. Would be really expensive ;-) But here the price is not so critical, size ans power consumption are MUCH more critical. Just a idea about a dirty-low cost LVPECL-> CMOS converter. How about to use a voltage divider to set the bias on an input near the switching point (1.4 V for TTL) and then capacitiv couple the LVPECL signal into the pin. Since this signal is a clock signal, no problems with low frequency components. Will this work? -- MFG FalkArticle: 32473
It might help to look at the big picture: America's economy is largely based on a technology lead over the rest of the world (we certainly are not going to compete with China on wage rates). Patents are a key part of protecting our technology edge. Are there dumb, obvious, bizare and ridiculous patents? Of course, but we have a legal system for sorting that out (those poor, destitute lawyers have to make a living some how, God knows that they don't have any useful skills). Tom Seim Kolja Sulimma <kolja@sulimma.de> wrote in message news:<3B399C0B.2A2CAA4@sulimma.de>... > cyber_spook wrote: > > > Being a Fan of Peter I don't wish to upset him... but these are my > > views... > > I sincerely hope we can have contrary views in this newgroup without > upsetting anybody. > > Besides: > Peter is known for taking a lot of beating in this newsgroup for things that > are not his fault > And he still continues with his invaluable support. > > Kolja SulimmaArticle: 32474
hi sorry newbie question! I have written some vhdl code around a counter logibox produced by Xilinx's Foundation software. anyway I have a top level entity that calls the logibox component, and then port maps the signals, and this syntax is fine. However when I come to synthesis the design, it gives me a warning saying that the logibox module is not linked to anything! Can you think where my problem might be? Any pointers, or things to check would be much appreciated! cheers tim -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Tim Nicolson Department of Electronic Engineering Sheffield University UK -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
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