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Curious, I tried this with FPGA express and it doesn't work so how would you do it out of FPGA express back into MaxPlus2? Leon de Boer ldeboer@attglobal.net "Iwo Mergler" <Iwo.Mergler@soton.sc.philips.com> wrote in message news:3B6AAC1C.A3691D44@soton.sc.philips.com... > > Martin Schoeberl wrote: > > > > > > A never ending problem! Trying to get RAMs in my design so that there is > > > not to much vendor specific code. > > > For Altera I'm using Leonardo and Max+plus, for Xilinx WebPack. > > > > > > I need a RAM with rgistered rd and wr address and unregistered data (in/out) > > > ports. > > > One version works: > > > Generate a .tdf file with Altera wizard and declare the component in the > > > VHDL > > > code. But now I have .tdf files. I want only VHDL. > > > > > Sorry, missed the original message... > > MaxPlus2 can recognize 'magic names'. To implement any of the LPM memories > in EABs, just instantiate the right component. In your case (assuming 256x8 bits): > > entity syn_ram_256x8_irou is > port ( Data : in std_logic_vector(7 downto 0); > Address : in std_logic_vector(7 downto 0); > WE : in std_logic; > Q : out std_logic_vector(7 downto 0); > Inclock : in std_logic > ); > > Copy this name & portmap into your design. Leonardo will complain > and generate EDF with a empty 'black box'. MaxPlus2 spots this and > fills the gap with the right thing (TM). > > I guess you want to know how this magic works... Here we go: > > If you dig deep enough into your MaxPlus2 installation, you'll find > a little DOS program called genmem.exe. This program generates a > VHDL (or Verilog) component with the right name. The component itself > is a handy simulation model for the memory, but make sure you don't > try to synthesize it. > > Have a nice day, > > IwoArticle: 33826
Hi, everybody out there. Thanks for your postings, they proved useful to me. I used once ALTERA's software MX+PLUSII, but I am not implementing anything at all on ALTERA's devices, and, why to switch to AHDL, when you have VHDL and/or Verilog? About tools like Renoir and Foundation, which would be better for a design on Xilinx devices? Cheers! "tb" <primax@jubiipost.dk> wrote in message news:<9klker$15ss$1@news.cybercity.dk>... > Forget Xilinx's Foundation and Mentor and all that. > > go to www.ALTERA.COM > > And use the free software it's easy > and powerfull > > regards > tb > > "Jaime Andres Aranguren Cardona" <jaime.aranguren@ieee.org> wrote in message > news:14a86f87.0108050942.7de276c0@posting.google.com... > > Hi, everybody. > > > > Want to generate opinions, from diverse kind of professionals, about > > the Design Tools used for FPGA/CPLD/ASIC designs. > > > > What is the industry-standard method for design? Is it text based > > VHDL/Verilog entry, text based test benches generation and graphical > > simulation? Or do professionals prefer alternate ways, such Finite > > State Machines (graphical entry), Block Diagrams, Truth Tables and/or > > Schematics? > > > > And what can be considered more "universal" and "standard", between > > tools like Xilinx's Foundation and Mentor Graphics' Renoir, ModelSim > > and Leonardo Spectrum? > > > > I expect to generate an instructive discussion topic, invlolving > > people from industry and academic spheres. > > > > Best regards, > > > > Jaime Andres Aranguren Cardona > > jaime.aranguren@ieee.org > > jaime.aranguren@computer.orgArticle: 33827
Frankly, I find it is easier to just use a generate and build the RAM that you need rather than using the coregen or inference. The added benefits are that you can 1) place the RAM, and 2) duplicated address and controls in a controlled manner for performance 3) you can get at any configuration. The placement is important because the automatic placement does not do so well with BRAMs (it won't put pieces that share address and control in adjacent locations, or even necessarily on the same column). Initializing instantiated RAMs is a bit of a pain though, unless you are happy with the default of all zeros. Erik Widding wrote: > "Andy Peters <andy [@] exponentmedia com >" <".> wrote in message > news:VGga7.1228$B.115611@newsread1.prod.itd.earthlink.net... > > Manoj K Krishnan wrote: > > > > > > Iam trying to build a ROM and RAM module using Xilinx Foundation > > > series 3.1i (VHDL coding) I tried using Core Generator > > > > Get a Real synthesis tool (Synplify or Leonardo) and infer the RAMs. > > The Core Generator simulation models are broken. > > > > -andy > > I swear by Synplify.... but it will not (yet) infer the RAM that I use most > often, the true dual port ram with two different port sizes, in Xilinx > Virtex/Spartan-II architecture. In the signal processing designs that I > have done this part is invaluable, as memories are a really good place to > change data bus widths for free in the Virtex architecture. You have to > build it yourself, or use the core generator, as it is not inferable through > Synplify. > > Regards, > Erik Widding. > > -- > Birger Engineering, Inc. -------------------------------- 781.481.9233 > 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33828
Antonio wrote: > Good Morning, I'm producing a CORDIC NCO and I've the following > problems/ question, could you help me on some of this ??? > > 1) The sine and cosine produced spans between -1 and +1 , it is the > case to use an additional bit for the integer part only to represent > -1 and +1 , may I trascure this and use only bits for the fractional > part ?? Not sure I understand your question here. When using the CORDIC as a sine/cosine generator, you set the scale by the constant you put on the I input. The CORDIC simply rotates the input vector by the specified angle. It has a gain of 1.64675. You can get the unscaled sine/cosine by using 1/1.64675 as the input value, or you can change that to get a different scaling. > > > 2) For the accumulator whose values spans between 0 and 6.28 I use 32 > bit, it is better to represent 6.28 as all ones and 0 as all zeroes or > I've to use 3 bit for the integer part and 29 bits for the fractional > part, what you suggest ?? Instead of trying to visualize it in radians, consider it in fractional revolutions. The accumulator value is then the fractional part of a revolution. If you have bits in the accumulator above those whch you take out as your phase angle, these would represent integer revolutions. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33829
I assume you wish to apply a different constraint to each block. Yes this can be done through the UCF file. First look at the libraries guide in the on-line documentation. What you need to do is create a TNM for each group. There are several ways to specify the TNM. Again refer to the on-line docs. Once you have the TNMs defined, then you can apply different timing specs to and between each one. You can also do this through the constraints editor, which in turn generates a UCF. Manjunathan wrote: > Hello everybody, > > i would like to know how to give timing constraint in an hierarchy design ? > > i have top level module as TOP.VHD. > > inside the toplevel i have component like BLOCK1,BLOCK2 and BLOCK3. > > how to give timing contraint INSIDE block1, block2 and block three when we are implementing the TOP level? > > is it possible to give constraint through UCF file? > > Thanks in Advance, > > Regards, > > Manjunath -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33830
glen herrmannsfeldt wrote: > > I need a saturable adder like the ALU in DSPs. > > I thought maybe you could just sign-extend the two input > > busses, add them, then detect if the result has overflowed > > the input bus width. If so, the result could be saturated > > to max-neg or max-pos. > > > > AHDL seems a bit limited for handling signed numbers. I'm > > learning some VHDL because it seems to have more constructs > > and knows about signed/unsigned numbers. > > I once did a Xilinx design with a saturating adder. In most cases, > I only had to worry about underflow, not overflow. At the end > of the carry chain, with one FG I could detect the underflow, and > then use the otherwise unused input on the rest of the FG to > generate the saturated value. In the one case with an overflow, > the I passed the signal on to the following stage, which had an > extra input available. > > That was a max(a,b), the maximum of two inputs, also done by using > the value at the end of the carry chain as an input to the other FG's. > > I had these as Xilinx macros that were substituted after the varilog > was compiled. Either the underflow saturating adder, or max(a,b) > would do 2n bits in n+1 CLB's, using the fact that the carry chain > works independently of the FG lookup values. This is true for the 4K series where the carry chain inputs come from the LUT inputs. In VIrtex and VIrtexII architectures, the carry chain is after the LUT, so the LUT is not free for anything else if you use the carry chain. The 4K series allowed you to use the carry chain to do a compare against a limit. The carry out and a sign bit could operate a limit mux implemented in the LUTs of the same CLBs. If you could accept an odd limit value, you get bipolar 2's complement limiting to an arbitrary odd value, or to full scale +/1 in a single column of CLBs. The virtex structure requires 2 layers to do the same because of the way the carry chain is structured. > > > -- glen -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33831
The problem is that unused pins are usually left floating at the board level. The 10K doesn't have internal pull-ups, so rather than leave the unused pins as floating inputs, Altera chose to drive them as a default. This prevents high power consumption, and possible latch-up problems do to floating inputs. This way, unused pins do not have to be connected on the board. The Xilinx parts have internal weak pullups on all pins which allow unused pins to be configured as inputs without worrying about whether the user connected them to external pullups or not. Lasse Langwadt Christensen wrote: > Paul Teagle wrote: > > > > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > > news:3B6E5599.31971F18@gmx.de... > > > vr schrieb: > > > > > > > > > the behaviour of the undefined pins (DRIVING a signal) fooled us a > > lot. > > > > > :-( > > > > > > > > Bit me too. Who expected such weirdness? > > > > > > > > Perhaps this was explained some place else but is there an easy way to > > > > tell Max+Plus II to make unused I/Os tri-stated(inputs)? Or an easy way > > to > > > > assign un-used I/Os to VCC/GND? > > > > > > Altera suggest to define all unused pins as inputs. Then, if you dont > > > use them in your VDHL, the will be tristated. > > > It works, but its still weird. > > > > > > > I think the reason as to why the Max+Plus defines unused pins as outputs is > > that otherwise you would have floating CMOS inputs - and they would tend to > > half rail and consume excessive currents, low noise immunity etc etc. The > > Hi-Z refers to the output pins. Inputs are by nature high impedance. > > > > That's the case on the 10K devices. Maybe the 20K family (I've never used > > them) has internal bus keeper resistors and thus they are pulled up/down > > internally, and the Quartus s/w knows this and thus defaults to the safer > > "input" configuration. > > why not just default to a tristate output, possibly with pullup, > no floating inputs and no risk of driving something unintensionally > > -Lasse > -- Lasse Langwadt Christensen, > -- A Dane in Phoenix, Arizona -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33832
I want to read out the Xilinx Virtex. Therefore from configuration options I have selected: Enable Readback and Configuration Generate Readback Bitstream After executing bitgen -l -w -g ConfigRate:4 -g CclkPin:PULLUP -g TdoPin:PULLNONE -g M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:JTAGCLK -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g M0Pin:PULLUP -g M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TmsPin:PULLUP -g UserID:12345678 -g DonePipe:No -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:NONE -m -g Readback core3.ncd WARNING:Bitgen:151 - Generating a readback bitstream, but the Persist option is set to "No" in the configuration bitstream. Readback will not be possible unless the Persist option is set to "Yes". What does this warning mean? Is readback really disabled? If yes: How and where can I set the persist option "yes"? MichaelArticle: 33833
"Michael Boehnel" <boehnel@iti.tu-graz.ac.at> wrote in message news:3B6EB17D.BB370064@iti.tu-graz.ac.at... > What does this warning mean? Is readback really disabled? If yes: How > and where can I set the persist option "yes"? Persist is one of the options to bitgen. Get help via bitgen -help virtexeArticle: 33834
On Wed, 01 Aug 2001 13:48:37 GMT, Ray Andraka <ray@andraka.com> wrote: > > >Rick Filipkiewicz wrote: > >> Ray Andraka wrote: >> >> > Paul Smart wrote: >> > >> > > Hi Ray, >> > > >> > > In principle, I agree with much of what you have said. >> > > >> > > On Tue, 31 Jul 2001 01:47:49 GMT, Ray Andraka <ray@andraka.com> wrote: >> > > >> > > > >> > > >It is behavioral in the sense that you can't go back and run that vhdl >> > > >through the tools to regenerate the design (wrong library). It doesn't >> > > >map directly back into the unisim primitives. >> > > > >> > > > >> > > Is there any way to take a modified verilog simulation file and put it >> > > back through to create a modified design? >> > >> > not any easy paths that I am aware of. You can remap the simprims into >> > unisims, but it is a very painful process. Probably less work starting on a >> > fresh design. >> >> I think its actually impossible to do this since there is a lot of information loss >> in the process of creating a Xilinx post-route sim netlist. e.g. all the various >> 2-way muxes, MUXF5, MUXF6, MUXCY, get turned into a single simprim X_MUX2. At least >> this is true for the flattened output from NGD2VER that I use. The ``re-create >> hierarchy'' mode might be better but a lot of that is still flattened. > >THis is why I said is is a very painful process. You can get to something that is >functional but may not map very well into the architecture fairly easily. Like you >point out, you lose all the architectural features like the carry chain stuff. You >also lose any placement you might have had. > >I suspect part of the reason for using different libraries is a (misguided?) attempt to >retain design security. > >> >> >> Parenthetically I've always wondered why Xilinx don't follow standard ASIC practice >> here and use the same lib for the design's EDIF netlist and the port-route sim one >> ? My - guessed - answer is that post-route sim is done much less frequently for >> FPGAs so the effort is not worth it, the unisims lib is far bigger than simprims. Can anyone confirm if this problem also exists for Altera (regarding the .vo simulation output)? Thanks, PaulArticle: 33835
Is there a way to install/remove the entire Xilinx Webpack using only a .cmd file (ie no console interaction during the install/remove of the software)?Article: 33836
Hello Michael, The warning message applies only to readback through the SelectMap port. If readback is to be performed through the JTAG port, then this warning can be ignored as the Persist option is not required for JTAG readback. I hope this helps. Best regards, Kamal Patel Michael Boehnel wrote: > I want to read out the Xilinx Virtex. Therefore from configuration > options I have selected: > > Enable Readback and Configuration > Generate Readback Bitstream > > After executing > > bitgen -l -w -g ConfigRate:4 -g CclkPin:PULLUP -g TdoPin:PULLNONE -g > M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:JTAGCLK -g > DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g M0Pin:PULLUP -g > M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g > TmsPin:PULLUP -g UserID:12345678 -g DonePipe:No -g GWE_cycle:6 -g > LCK_cycle:NoWait -g Security:NONE -m -g Readback core3.ncd > > WARNING:Bitgen:151 - Generating a readback bitstream, but the Persist > option is > set to "No" in the configuration bitstream. Readback will not be > possible > unless the Persist option is set to "Yes". > > What does this warning mean? Is readback really disabled? If yes: How > and where can I set the persist option "yes"? > > MichaelArticle: 33837
I have already got an answer from a Xilinx employee. In case of JTAG readback (as it is in my case) I can ignore the warning. Michael > > WARNING:Bitgen:151 - Generating a readback bitstream, but the Persist > option is > set to "No" in the configuration bitstream. Readback will not be > possible > unless the Persist option is set to "Yes". >Article: 33838
I have done most of my work with Xilinx devices using the Xilinx FPGA editor. I would like to get some advice on selecting a single verilog synthesis tool that works well with both Altera and Xilinx. Thanks, PaulArticle: 33839
http://echo.gmu.edu/shannon/survey/memories.php AustinArticle: 33840
Hello Michael, The warning message applies only to readback through the SelectMap port. If readback is to be performed through the JTAG port, then this warning can be ignored as the Persist option is not required for JTAG readback. I hope this helps. Best regards, Kamal Patel Michael Boehnel wrote: > I want to read out the Xilinx Virtex. Therefore from configuration > options I have selected: > > Enable Readback and Configuration > Generate Readback Bitstream > > After executing > > bitgen -l -w -g ConfigRate:4 -g CclkPin:PULLUP -g TdoPin:PULLNONE -g > M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:JTAGCLK -g > DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g M0Pin:PULLUP -g > M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g > TmsPin:PULLUP -g UserID:12345678 -g DonePipe:No -g GWE_cycle:6 -g > LCK_cycle:NoWait -g Security:NONE -m -g Readback core3.ncd > > WARNING:Bitgen:151 - Generating a readback bitstream, but the Persist > option is > set to "No" in the configuration bitstream. Readback will not be > possible > unless the Persist option is set to "Yes". > > What does this warning mean? Is readback really disabled? If yes: How > and where can I set the persist option "yes"? > > MichaelArticle: 33841
tb wrote: > > Forget Xilinx's Foundation and Mentor and all that. > > go to www.ALTERA.COM > > And use the free software it's easy > and powerfull That's not at all helpful when you want to target a different vendor's devices. --aaaArticle: 33842
Just to note, This message has been made clearer in the new version of the software, so it specifically mentions the SelectMAP port. Sorry for the confusion Michael. Best regards, Kamal Patel Kamal Patel wrote: > Hello Michael, > > The warning message applies only to readback through the SelectMap > port. If readback is to be performed through the JTAG port, then this > warning can be ignored as the Persist option is not required for JTAG > readback. > > I hope this helps. > > Best regards, > Kamal Patel > > Michael Boehnel wrote: > > > I want to read out the Xilinx Virtex. Therefore from configuration > > options I have selected: > > > > Enable Readback and Configuration > > Generate Readback Bitstream > > > > After executing > > > > bitgen -l -w -g ConfigRate:4 -g CclkPin:PULLUP -g TdoPin:PULLNONE -g > > M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:JTAGCLK -g > > DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g M0Pin:PULLUP -g > > M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g > > TmsPin:PULLUP -g UserID:12345678 -g DonePipe:No -g GWE_cycle:6 -g > > LCK_cycle:NoWait -g Security:NONE -m -g Readback core3.ncd > > > > WARNING:Bitgen:151 - Generating a readback bitstream, but the Persist > > option is > > set to "No" in the configuration bitstream. Readback will not be > > possible > > unless the Persist option is set to "Yes". > > > > What does this warning mean? Is readback really disabled? If yes: How > > and where can I set the persist option "yes"? > > > > MichaelArticle: 33843
Paul Smart wrote: > > I have done most of my work with Xilinx devices using the Xilinx FPGA > editor. I would like to get some advice on selecting a single verilog > synthesis tool that works well with both Altera and Xilinx. Get a coin. Flip it. One side: choose Leonardo. The other: choose Synplify. Note that absence of a three-sided coin prevents you from choosing FPGA Express. -andyArticle: 33844
Antonio wrote: > > Good Morning some question about VHDL : > > 1) In a project I've to use always the same clock edge ??? For a > XCV1000 BG560 -4 which is better , the negative or the positive ?? Shouldn't matter. > 2) Xilinx suggest to use the positional associations in the port map > and not the named association, why ?? Huh? Any book on VHDL will tell you to use named associations. It removes a lot of ambiguity that'll bite you in the tuchus later on. I'm sure the Xilinx docs are still recommending two-process state machines and std_logic_arith, too. > 3) The "IF" structure produce a more speed design respect to the > "case" structure ?? Depends on the complexity of the statement, and whether you want priority or not. -andyArticle: 33845
chris wrote: > > i can't give you hard numbers for synthesis and place and route > speeds, but when comparing my co-workers athlon with 512 MB PC133 > SDRAM and my Pentium 4, 1.7 GHz with 1 GB RDRAM, i noticed that there > was significant improvement in synthesis and place and route times. How big was the design? What OS? What else were you running at the time? The P4/RDRAM system has twice the memory of the PC133 system. If you're into swap space on the PC133 box, you're hosed. A fairer test would be boxes with equivalent processors, one with RDRAM, the other with DDR or PC133 or what have you. Of course, I don't think Athlon boxes support RDRAM, and I haven't kept up with Intel's attempts at SDRAM on P4s. -andyArticle: 33846
Manjunathan wrote: > > Hello everybody, > > i would like to know, how to replicate the logic through VHDL attributes in Xilinx foundation series 3.1i tool. Read the docs that came with the synth tool. There will be something along the lines of syn_keep or dont_optimize. Synplify also lets you specify max fanout on nets, and will replicate the registers for you, so you don't have to put the replication in your code. -aArticle: 33847
300% ? That's so high it's not realistic. Either there is a problem with the way you made the measurements or your Athlon is not optimally configured or you're not using the same software version/settings on both machines. Another possibility is that your design exceeds your Athlons's main memory size (512 MB) and it starts swapping data in & out of the hard drive when it fits in your P4's 1Gig RDRAM, thus you somehow compare apples & oranges. The idea that commonly used benchmarks would be useless because "in our industry, i think we push the memory bandwidth of our PCs" also seems quite baseless. I really can't see how the industry sector of the application's purpose would impact execution speed in any way, except for marketing purpose. Other applications such as video stream encoding or 3D rendering also push the memory bandwidth, yet the results are not at all what you report, by far. According to most peoples both in this NG and elsewhere, Athlon 1.4 with DDR is the way to go from a performance perspective, and that's before you enter price in the equation. As usual, your mileage may vary, but not by 300%. You can search the newsgroup for the "Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim? " thread or get it here : http://groups.google.com/groups?hl=en&safe=off&th=f6db386ca8a266e3,10&seekm=9kalp6%24onc%40news.or.intel.com Eric chris wrote: > i can't give you hard numbers for synthesis and place and route > speeds, but when comparing my co-workers athlon with 512 MB PC133 > SDRAM and my Pentium 4, 1.7 GHz with 1 GB RDRAM, i noticed that there > was significant improvement in synthesis and place and route times. we > actually benchmarked the simulation times which was what we were > interested in and the P4 1.7 with rambus outperformed the athlon 1 Ghz > by about 300%. originally, i thought the difference would only be > around 50% or so since the athlon chip 1GHz performance is not that > far away from a pentium 1.7GHz performance. the benchmarks on toms > hardware say that the fast memory only improves performance by about > 10% or so, but in our industry, i think we push the memory bandwidth > of our PCs. i pretty much believe that the big boost in simulation > performance was not that my processor was faster, but that my memory > was much faster than the PC133. i am pretty sure that place and route > and synthesis are very memory intensive also, since i always run out > of ram on my laptop whenever i try to synthesize my design. > chris wangArticle: 33848
>> i can't give you hard numbers for synthesis and place and route >> speeds, but when comparing my co-workers athlon with 512 MB PC133 >> SDRAM and my Pentium 4, 1.7 GHz with 1 GB RDRAM, i noticed that there >> was significant improvement in synthesis and place and route times. we >> actually benchmarked the simulation times which was what we were >> interested in and the P4 1.7 with rambus outperformed the athlon 1 Ghz >> by about 300%. Also, don't forget that some of the CAD problems tend to be fairly random access in the memory patterns. This strongly punishes things when the working set exceeds available memory. This also tends to be memory latency, not memory bandwidth bound. The P4 has great bandwidth, but fairly bad latency. Memory is cheap right now. THere is no excuse for having a cad machine which has to swap. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 33849
jaime.aranguren@ieee.org (Jaime Andres Aranguren Cardona) wrote in message news:<14a86f87.0108050942.7de276c0@posting.google.com>... > Hi, everybody. > > Want to generate opinions, from diverse kind of professionals, about > the Design Tools used for FPGA/CPLD/ASIC designs. > Jaime, If we are talking about tools (vendors and products they are selling) you have to look at them and check which ones feel good fot YOU. Just look for the following features: 1. Silicon vendor independent. Contrary to what Xilinx or ALTERA fans and salesmen may tell you, those vendors (and any others) are NOT the only ones... AHDL was very successful attempt to tie customers to ALTERA chips and should be avoided if there is even the slightest possibility of non-ALTERA implementation in the future. 2. Even if you know/use just one language (VHDL or Verilog), look for the tool that supports both. You never know what will happen in the future... 3. Text editor which is VHDL/Verilog conscious (syntax highlighting, autocompletion, autoindenting, etc.) is a must and the only entry tool you really need. However, if you plan to do hierarchical designs, plain VHDL/Verilog text will be very difficult to enter and hard to manage, so decent Block Diagram Editor may be very helpful. Always check if it generates plain VHDL/Verilog from the diagram, so that you can port your design to the pure text environment whenever it is required. 4. Check debugging features - a little experience with debugging C,Pascal, or assembler programs will help you check debugging features. 5. Look for easy way of integrating design entry, synthesizers and implementation tools. Recently it is done via Tcl/Tk scripts, so both tool vendors and more experienced users can modify interfaces quickly. 6. VHDL simulator should be fully compliant with the most recent version of IEEE 1076 standard (currently 1993, by the end of the year new release should be approved). Verilog standard exists, but tool compliance is totally different story... Good luck, Jerry
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