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Dave Feustel wrote: > > "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B5FBD21.C2575779@algor.co.uk... > > > > > > David Wright wrote: > > > > > (2) ModelSim XE Starter is free if you limit your code to 500 lines or less. > > > > Don't bother with it. My advice is to just bite the bullet & get the full-fat PE > > NT version, its only ~$4.5K. Put it on a fast DDR Athlon box and you really > > won't regret it. > > Is this a one-time or annual expense? It costs about $4.5K to obtain the license, and ~$700 (I don't remember exactly) per year "maintenance," which gets you the free updates. You probably want to bite the bullet and get the maintenance, since they always seems to break things when updating. They do release updates frequently, tho'. I agree with the sentiment, "don't bother with the starter." You have to convince the boss that your TIME (and the schedule) cost more than using a crippled freeware tool. --aArticle: 33451
I suspect that this project is pointless, because the postcode is sent out during Power On Self Test, and the I think you will find that the PCI bus does not become active until most of the self test is completed. This is why debug boards with the 2 digit display are ISA boards. ISA is always active. Philip On Thu, 26 Jul 2001 16:50:18 +0200, Wilfried Philippi <wph@gmx.net> wrote: >hello, >i want to develop a PCI Interface that read from i/o Adress 80hex as i/o >read and then stores >the data for displaying with 2 7seg display's. The function of this is >do show the postcode while >system is booting. because the interface must work wen power ist >switching on, a fpcga with >sram can not work. has anyone Ideas or can tell me what chip is the best >reason >many Thanks. >best regards >wilfried Philip Freidin FliptronicsArticle: 33452
Greg Neff wrote: > On Thu, 26 Jul 2001 10:17:01 +0100, Rick Filipkiewicz > <rick@algor.co.uk> wrote: > > >I know this is a bit off topic but there's a lot of general h/w > >expertise in this NG so here goes: > > > >What's the general view of PQFP sockets that mount on the same SMT > >footprint as the component itself ? > > > >o As test sockets ? > > > >o For production ? > > > >My experience of these this things is that they are as flakey as a bad > >case of dandruff but maybe there are better ones than those I've had to > >deal with. If so which ones are best ? > > I don't know about surface mount PQFP sockets. The only PQFP test > sockets that we have used are Yamaichi through-hole clam shells: > > http://www.yeu.com/index_tb.html > > These have worked fairly well for us. The only place we have used > these is on engineering evaluation boards to qualify ASICs in place of > FPGAs. I would not use these in production. I don't even like > socketing QFPs for programming (we use in-circuit programming). Why > would you want to socket a PQFP on a production board? I don't. I'm trying to convince one of my colleagues that SMT QFP sockets come in the ``Don't go there'' [I'd put it more strongly - ``Don't even walk past there''] category or, failing that, to come up with the least unreliable one.Article: 33453
Hi Rick, Putting IC's in sockets is generally a bad idea. The faster you want you logic to run the more problems you will have. Lead inductance is a major headache, decoupling the power supply can be a real problem! Hope this helps your cause. Dave <--Just putting something back into the system--> ---------------------------------------------------------- "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B606568.43A71310@algor.co.uk... > > > Greg Neff wrote: > > > On Thu, 26 Jul 2001 10:17:01 +0100, Rick Filipkiewicz > > <rick@algor.co.uk> wrote: > > > > >I know this is a bit off topic but there's a lot of general h/w > > >expertise in this NG so here goes: > > > > > >What's the general view of PQFP sockets that mount on the same SMT > > >footprint as the component itself ? > > > > > >o As test sockets ? > > > > > >o For production ? > > > > > >My experience of these this things is that they are as flakey as a bad > > >case of dandruff but maybe there are better ones than those I've had to > > >deal with. If so which ones are best ? > > > > I don't know about surface mount PQFP sockets. The only PQFP test > > sockets that we have used are Yamaichi through-hole clam shells: > > > > http://www.yeu.com/index_tb.html > > > > These have worked fairly well for us. The only place we have used > > these is on engineering evaluation boards to qualify ASICs in place of > > FPGAs. I would not use these in production. I don't even like > > socketing QFPs for programming (we use in-circuit programming). Why > > would you want to socket a PQFP on a production board? > > I don't. I'm trying to convince one of my colleagues that SMT QFP sockets > come in the ``Don't go there'' [I'd put it more strongly - ``Don't even walk > past there''] category or, failing that, to come up with the least > unreliable one. >Article: 33454
Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:<3B602E8C.61511212@iprimus.com.au>... > Hi all, > > If i leave out the second "LIBRARY ieee" and "USE" statement, i get > an error about undeclared types in the second entity (wave). It seems > that the scope of the first library statement ends at the first > entity. Is this normal, or a leonardo quirk? > > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > > ENTITY traffic IS port( > de : IN std_ulogic; > ab : OUT std_ulogic); > END; > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > > ENTITY wave IS port( > d: IN std_ulogic; > clk: IN BIT; > clear: IN BIT; > outa: OUT BIT); > END wave; It should be easier to remember that LIBRARY / USE statements are the part of DESIGN UNIT HEADER, not your VHDL file header. Design units you know for sure are entities and architectures, but package, package body and configuration declaration are also design units. If you have more than one unit in your VHDL file, each unit MUST have its own header (=LIBRARY / USE section). Hope it helps. JerryArticle: 33455
John_H <johnhandwork@mail.com> wrote:
: Rather than going for the generic processor approach with a boatload of ALU
: capability, perhaps an "integer convolution coprocessor" would be a more
: manageable design task? FPGA designs excel at attacking very specific
: problems without the overhead of a generic approach. For instance there are
: FFT cores that allow very high speed transforms compared to the processor
: counterparts. Lots of computational horsepower and cost effective at the same
: time. Your specific tasks might be implemented with blinding speed if you put
: the hardware toward only the task you need.
When the convolutions involved are very large, the techniques involved
get extremely complicated; rather than coding up a complicated program
in hardware it would be easier, I think, to have a processor which can
execute the primitives an integer FFT would need and nothing else.
As an example, most of an integer FFT can be built if you have
a vectorized instruction which can do
{a,b} <-- { (a+b) mod p, (a-b)*w mod p }
where p is 2^64-2^32+1, a and b are vectors of 64-bit words and w is
a 64-bit scale factor. The fastest I can manage for this operation is
10 clocks on an Alpha 21264 (using really ugly pipelined assembly code).
Given hardware that can pump out 4 of these per clock cycle, an FPGA
at 100 MHz would be 5x faster than an Alpha at 800MHz. Of course, this
would mean your register file would have to move a kilobit of data per
clock!
The point is that even having a primitive like this is just the tip of the
iceberg for implementing a complete solution, and just this would likely
involve a *lot* of hardware real estate.
But you're right that perhaps the hardest part of the job would be
deciding exactly what the hardware should be capable of doing, and
forgetting about any bells and whistles.
jasonp
Article: 33456Hong wrote: > > Hi, > It works fine without the networking card, you will need the Disk Serial Number, of course! > Here is an example, just simply follow the installed instruction, there is an optional for it (HD S/N)! You could get free trial license in 30-day then determine the needs. It's pretty cool! > More info: > http://www.mentor.com/fpga-advantage/ > > Example: > Product ID : FA4.0 (FA5.0) > Eval Host ID : xxxxxxxxxxxxxxxxxxxxx > Ethernet Address : -X > Hostname : yourhost > Disk Serial Number : xxxxxxxx > Internet Address : xxx.0.0.x > > You wrote: > >>>I couldn't try Leonardo Spectrum until i get an old network > card with NIC. Will it work without a network connected? (using > win2k)<<< > > Hope this helps, > > Hong Hmm, i was really talking about leonardo (i have a *much* lower opinion of them now that i've contacted the exemplar support). Leonardo wouldn't work with the network card and licence file i got. However, i found that installing the IPX/SPX protocol in windows made it work (even tho i'm not on a network). -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33457
Speedy Zero Two wrote: > Hi Rick, > > Putting IC's in sockets is generally a bad idea. The faster you want you > logic to run the more problems you will have. > > Lead inductance is a major headache, decoupling the power supply can be a > real problem! > > Hope this helps your cause. > > Dave > <--Just putting something back into the system--> > I'm more worried that I won't even get to these problems because the physical issues, i.e. soldering, will kill me first. The part being considered has its leads underneath the socket plastic and its a 208QFP so any open or short is going to be *HARD* to fix. There's a plastic frame inside the socket at the bottom that could be removed for access but my experience with PLCC sockets tells me that once you've done this its very difficult to get the chip to seat properly. The other class of SMT socket I've seen looks more like a normal chip but the leads have been extended downwards & the socket sits up off the board. The killer with these is that wicking can lead to shorts behind the wall of IC pins which are impossible to fix.Article: 33458
Hi all, How's the cypress warp 6.1 ($99) compare to other cheap/free VHDL editors/synthesizers? I'm interested in the delta39k devices which have internal ram. A particularly attractive feature of the delta39k parts (which seem to be in a similar area to the altera acex 1k parts), is that they have internal flash and internal (as well as external) boot option. The acex 1k parts don't have flash, so you always need an external configuration device, which takes up space, inventory, and is more exposed to copying... http://www.cypress.com/pld/warp.html?homeadwarp -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33459
Hi everyone, I have a problem in my Altera 7000S design. All my outputs are limited to 3.5V. Both the VCCIO and VCCINT are 5V. I have tried compiling with the 'auto open drain' and the 'multivolt i/o' options both on and off but the result is always the same: 3.5V out. Both connected (to cmos) and unconnected pins limits to 3.5V. Does anyone have a clue or idea what might be wrong??? Thanx in advance... Kind Regards, Frode Undseth Tel: +47 33 30 42 26 Mail: fun.arctic@heating.no ---------------------------------------------------------------------------- -------------- Arctic Heating AS P.O.Box 164 Teie, N-3106 Tønsberg - Norway Tel, +47 33 30 42 20 Fax, +47 33 32 29 02 E-mail:arctic@heating.noArticle: 33460
Just to let you know, the Xilinx PCI core for Spartan II costs about $5000,- (I have one). A PLX9052 is about $10,-. ClemensArticle: 33461
TTL compatible outputs. You might even go as high as 3.7V. Open drain should even be worse. Try pull-up resistors (e.g. 4k7 to VCC), especially when your pin fans out to active high inputs. Remember that the TTL high level is about 2.4V and that it should work in most cases. True CMOS outputs will pull the signal high, close to rail voltage. TTL(bipolar style) has a weak pull-up resistor in the form of a small semi-switched on resistor. Most designers have come this stage where they (usually one day long after the first designs) measure the outputs and say "oops something is wrong". If you want to try something confusing try working with 1.8V (APEX-20KE), 2.5V (APEX-20K), 3.3V I/O, 5V memory, 3 different types of opto-isolators and 12V outputs to drive relays all on the same PCB. Here is the big electronic tip: Most ICs (especially TTL) can usually sink much more current than it can source. Many TTL circuits can only source 0.5mA where as it can sink about 20mA. Many CMOS ICs can source 20mA compared to about 25mA that it can sink. Get your hands on the digital library CD on browse their web site and have a look at the construction on the output section as well as the I/O standards the IC supports. Victor "Frode Undseth" <fun.arctic@heating.no> wrote in message news:na787.4567$em.165883@juliett.dax.net... > Hi everyone, > > I have a problem in my Altera 7000S design. All my outputs > are limited to 3.5V. Both the VCCIO and VCCINT are 5V. > I have tried compiling with the 'auto open drain' and the 'multivolt i/o' > options both on and off but the result is always the same: 3.5V out. > Both connected (to cmos) and unconnected pins limits to 3.5V. > > Does anyone have a clue or idea what might be wrong??? > > Thanx in advance... > > Kind Regards, > Frode Undseth > Tel: +47 33 30 42 26 > Mail: fun.arctic@heating.no > > -------------------------------------------------------------------------- -- > -------------- > Arctic Heating AS P.O.Box 164 Teie, N-3106 Tønsberg - Norway > Tel, +47 33 30 42 20 Fax, +47 33 32 29 02 E-mail:arctic@heating.no > >Article: 33462
Russell Shaw <rjshaw@iprimus.com.au> writes: > How's the cypress warp 6.1 ($99) compare to other cheap/free > VHDL editors/synthesizers? I've used it for their 340-series and 37000 series PLDs, and had pretty good results. > I'm interested in the delta39k devices which have internal ram. I was able to fit one of my designs that formerly took a 37512 and a 37256 into under 1/4 of a 39K100. Last time I checked, about two months ago, 39K samples weren't yet available except perhaps to really big customers. So I haven't done anything serious with it. > A particularly attractive feature of the delta39k parts (which > seem to be in a similar area to the altera acex 1k parts), is > that they have internal flash and internal (as well as external) > boot option. Note that the flash is NOT on the Delta39K die, it's just an extra flash part optionally put into the same package, at higher cost. I don't know the prices, but I'd suspect that supplying your own flash is probably cheaper than buying it "integrated". The integrated part might be advantageous if you're concerned about bitstream security. My recent and current projects use Cypress 37K PLDs for small designs, Xilinx Spartan-II for medium to medium-large designs, and Xilinx Virtex-E or Virtex-II for large to very large designs. The Spartan-II pricing is very agressive, nearly enough to replace small CPLDs, except that you still need a config PROM. I tend to find that my medium size and larger designs are too register-intensive for CPLDs.Article: 33463
Eric Smith wrote: > My recent and current projects use Cypress 37K PLDs for small designs, > Xilinx Spartan-II for medium to medium-large designs, and Xilinx > Virtex-E or Virtex-II for large to very large designs. The Spartan-II > pricing is very agressive, nearly enough to replace small CPLDs, except > that you still need a config PROM. > > I tend to find that my medium size and larger designs are too > register-intensive for CPLDs. Given that you are using Xilinx for FPGAs what advantages have you found using Cypress CPLDs over the Xilinx XC95K series parts ?Article: 33464
Hi, When using CoreGenerator for a SRL16 based shif register, say, a 32x1 shfit register, I found the result was 3 LUT, 2 for SRL16, 1 for mux. Does anyone know why CoreGen doesn't use MUXF5/6/7/8 for a more resource efficient result? ThanksArticle: 33465
Clocks should always be routed on the global clock nets to achieve low skew. Are your 3 clocks on global clock nets? The clocks should be feed via the global clock input buffers. If you dont have a location constraint on this nets, Foundation will do this automatically. When you run out of clock nets (there are only 4) instruct the P&R tools to use low skew nets with this instuction in the UCF NET my_net_name uselowskewlines; What do you mean with phase inversion?? The phase of the 6 MHz makes instaneous jumps? How did you measure this? With a scope? Did you trigger on the 6 MHz clock? How did you design the divide by 2 circuit? (Yes, its just a toggeling FF, but . . .) Regards FalkArticle: 33466
It turns out that the modelsim licence I received for Verilog actuallly was for VHDL. Verilog compiles still don't work since I still don't have a license for that compiler (No idea why) I decided to uninstall all the FPGA-related software on my computer (except that which came from Atmel) and then reinstall the Xilinx Foundation software. I also deleted all registry entries and directory subtrees that seemed relevant. Well, now the Xilinx Foundation ISE evaluation software won't install at all. The error message is still "This program cannot be installed on a computer with other Xilinx software". No clues offered by the setup program as to what it is on the computer that offends the Xilinx install program. So now its on to Webpack as soon as I can get digital cable installed so I can download the software (~75 MB minimum only available from the web as far as I can tell). "Dave Feustel" <dfeustel@mindspring.com> wrote in message news:9jmk18$33l$1@slb3.atl.mindspring.net... > Xilinx Support resolved this problem by giving me a different registration > number which apparently makes the install ignore whatever caused the > conflict. > > "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B5E1D05.A6CD1528@algor.co.uk... > > > > > > Dave Feustel wrote: > > > > > I am attempting to install the Xilinx Foundation Software eval package > > > On Windows 2000 Pro. When I enter the required registration id, the setup program > > > displays a message saying that this software won't install with any other Xilinx > > > software installed. Unfortunately the error message includes absolutely no > > > information as to which other software package (or where it is on the disk) > > > that the setup program finds offensive > > > . > > > I have checked the start programs menu, the top level C directory and the > > > registry and I can find no sign of any software identified as from Xilinx. > > > > > > There is installed on this machine some software licenced from Atmel. > > > There also is something from Mentor Graphics installed. > > > > > > Does anyone have any idea what software it is that the Xilinx setup program > > > is complaining about? > > > > > > Thanks, > > > > > > Dave Feustel > > > Fort Wayne, Indiana > > > > In theory you can install 3.3i with various other Xilinx packages (there's a solution > > record somewhere in the answers database). I think this restriction is purely for > > the eval version. What I did was to copy my 2.1i & WebPACK installations somewhere > > else > > and then uninstall them. The 3.3i eval installs fine & I can still get to the other > > stuff, at least from the command line, by setting the ``XILINX'' env variable to > > point to whichever toolset I want to use. > > [It helps to have Cygwin installed and use the ``bash'' shell]. > > > > However this was on NT-SP6a. > > > > > > > >Article: 33467
Re Saga of Installing Xilinx Foundation ISE evaluation software on my computer: It turns out that the modelsim licence I received for Verilog actuallly was for VHDL. Verilog compiles still don't work since I still don't have a license for that compiler (No idea why) I decided to uninstall all the FPGA-related software on my computer (except that which came from Atmel) and then reinstall the Xilinx Foundation software. I also deleted all registry entries and directory subtrees that seemed relevant. Well, now the Xilinx Foundation ISE evaluation software won't install at all. The error message is still "This program cannot be installed on a computer with other Xilinx software". No clues offered by the setup program as to what it is on the computer that offends the Xilinx install program. So now its on to Webpack as soon as I can get digital cable installed so I can download the software (~75 MB minimum only available from the web as far as I can tell). If I seem confused, dazed and disoriented, it's because I am. And I thought Microsoft installs were bad. "Andy Peters <andy [@] exponentmedia com >" <".> wrote in message news:yIY77.2415$nS1.340368@newsread1.prod.itd.earthlink.net... > Dave Feustel wrote: > > > > "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B5FBD21.C2575779@algor.co.uk... > > > > > > > > > David Wright wrote: > > > > > > > (2) ModelSim XE Starter is free if you limit your code to 500 lines or less. > > > > > > Don't bother with it. My advice is to just bite the bullet & get the full-fat PE > > > NT version, its only ~$4.5K. Put it on a fast DDR Athlon box and you really > > > won't regret it. > > > > Is this a one-time or annual expense? > > It costs about $4.5K to obtain the license, and ~$700 (I don't remember > exactly) per year "maintenance," which gets you the free updates. You > probably want to bite the bullet and get the maintenance, since they > always seems to break things when updating. They do release updates > frequently, tho'. > > I agree with the sentiment, "don't bother with the starter." You have > to convince the boss that your TIME (and the schedule) cost more than > using a crippled freeware tool. > > --aArticle: 33468
I just got done using the Cypress Warp 6 on my project. It was a no go. After fighting problems a couple of weeks, tech-support left me holding the bag. Evidently, split-busses do not work on CPLD's (no compile). Can't use /x/ identifiers in VHDL on some compilers. Other problems. Cost $175 for Warp plus $300 for parts. Not sure if Cypress or their distributor will take them back. Russell Shaw wrote in message <3B60D8E1.1ECB1D9D@iprimus.com.au>... >Hi all, > >How's the cypress warp 6.1 ($99) compare to other cheap/free >VHDL editors/synthesizers? > >I'm interested in the delta39k devices which have internal ram. > >A particularly attractive feature of the delta39k parts (which >seem to be in a similar area to the altera acex 1k parts), is >that they have internal flash and internal (as well as external) >boot option. The acex 1k parts don't have flash, so you always >need an external configuration device, which takes up space, >inventory, and is more exposed to copying... > >http://www.cypress.com/pld/warp.html?homeadwarp > >-- > ___ ___ > / /\ / /\ > / /__\ / /\/\ >/__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ >\ \ / Victoria, Australia, Down-Under \ \/\/ > \__\/ \__\/Article: 33469
--------------E7AA0996C61C3C690F426023 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Huang, It may be slower. That is usually why a resource is not used. Not every combination of new resources (eg f8) results in a faster implementation. One curious thing we see over and over, is as the CLB's get faster and faster, it is incredibly hard to make a special feature result in any improvement at all. Now we work closely with the synthesis vendors to ensure that the realizations of the functions use the fastest resources possible. We also try not to add some widget feature unless we can prove to ourselves that it is going to really be faster than the general realization of the same function with existing resources. Austin XILINX ICDES, FPG (our new name -- FPGA Products Group!) Huang wrote: > Hi, > > When using CoreGenerator for a SRL16 based shif register, say, a 32x1 shfit register, I found the result was 3 LUT, 2 for SRL16, 1 for mux. > > Does anyone know why CoreGen doesn't use MUXF5/6/7/8 for a more resource efficient result? > > Thanks --------------E7AA0996C61C3C690F426023 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Huang, <p>It may be slower. That is usually why a resource is not used. Not every combination of new resources (eg f8) results in a faster implementation. <p>One curious thing we see over and over, is as the CLB's get faster and faster, it is incredibly hard to make a special feature result in <i>any improvement at all.</i> <p>Now we work closely with the synthesis vendors to ensure that the realizations of the functions use the fastest resources possible. <p>We also try not to add some widget feature unless we can prove to ourselves that it is going to really be faster than the general realization of the same function with existing resources. <p>Austin <br>XILINX ICDES, FPG (our new name --<b> F</b>PGA <b>P</b>roducts <b>G</b>roup!) <p>Huang wrote: <blockquote TYPE=CITE>Hi, <p>When using CoreGenerator for a SRL16 based shif register, say, a 32x1 shfit register, I found the result was 3 LUT, 2 for SRL16, 1 for mux. <p>Does anyone know why CoreGen doesn't use MUXF5/6/7/8 for a more resource efficient result? <p>Thanks</blockquote> </html> --------------E7AA0996C61C3C690F426023--Article: 33470
Wilfried Philippi schrieb: > > hello, > i want to develop a PCI Interface that read from i/o Adress 80hex as i/o > read and then stores > the data for displaying with 2 7seg display's. The function of this is > do show the postcode while > system is booting. because the interface must work wen power ist > switching on, a fpcga with > sram can not work. has anyone Ideas or can tell me what chip is the best > reason First, there are many PCI ICs, nice one-chip solutions to connect user logic to the PCI bus. Look for PCI 9030 in a search engine. Second, why not using a FPGA? They can be configured via FLASH. In 8 bit mode, @50 MHz, a medium size FPGA (lets say a Spartan II 100, XC2S100) can get configured in 1.9 ms (780 kbit config file) Not too bad. If this is still too slow, use a CPLD. -- MFG FalkArticle: 33471
Here is the simple rule for 5-V parts: If Voh min is specified as 2.4 V, then it is a TTL-like "totem-pole" structure with an n-channel pull-up transistor, and the real Voh will be one threshold below Vcc, i.e. around 3.7 V. To get a higher Voh, use an external pull-up resistor. If Voh min is specified as 3.5 to 4.0 V, then it really is a true CMOS output with a p-channel pull-up, and the unloaded Voh is identical with Vcc. Lower-Vcc standards ( 3.3, 2.5, 1.8, 1.5 V) have always true CMOS outputs ( unless they are open-"collector", like GTL.) PECL and differential standards like LVDS are a different matter. Peter Alfke, Xilinx Applications ==================================================== Victor Schutte wrote: > TTL compatible outputs. You might even go as high as 3.7V. Open drain should > even be worse. Try pull-up resistors (e.g. 4k7 to VCC), especially when > your pin fans out to active high inputs. Remember that the TTL high level is > about 2.4V and that it should work in most cases. >Article: 33472
Hi All, I was wondering if anyone can shed some light on this: The Xilinx and Altera tools seem to produce a behavioral verilog file for simulation. Is there any way I can get a structural verilog file? There are some (ASIC) tools I want to use with these files that only support structural verilog (the tools are for ATPG, DFT, and fault simulation (ultimate goal is device testing)). Examples of this type of tool are: - IBM: TestBench (DFT, ATPG) - Synopsys: DFT Compiler and TetraMax ATPG Is this something that Xilinx or Altera will provide someday? I know a lot of ASIC related tools cannot work with current FPGA design methodologies, but do we really expect to work with multi million gate FPGAs without access to DFT, ATPG, and fault simulation tools as are used in the ASIC world? Thanks for your time, PaulArticle: 33473
Gonzalo, The edif netlist flow is currently only available for the CPLD families. To add a netlist for these families: -In the Project Properties dialog box, change the Synthesis Tool to 'external netlist' -In the Processes for Current Source window, right click on Implement design and select Properties... -Under the Design tab, specify the file in the 'External Netlist File' box. I hope this helps, Dylan Buli Xilinx Applications Gonzalo Arana wrote: > Hi, > > I am using Xilinx WebPACK and trying to add an edif file to a project > (written in vhdl). > May I? How? Should I be able to? (I mean, Does it make any sense?) > > Thank you very much in advance, > > Gonzalo AranaArticle: 33474
Rick Filipkiewicz <rick@algor.co.uk> writes: > Given that you are using Xilinx for FPGAs what advantages have you found > using Cypress CPLDs over the Xilinx XC95K series parts ? I haven't tried the Xilinx CPLDs.
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