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Hello: I need an advice on which fpga board buy. Somebody could tell me which one has best software, documentation support, etc. Thanks Yoram Rovner yoram@puc.clArticle: 33851
Have a look at www.cmosexod.com for a start. "Yoram Rovner" <yoram@puc.cl> wrote in message news:62ef4351.0108061133.cab3562@posting.google.com... > Hello: > > I need an advice on which fpga board buy. Somebody could tell me which > one has best software, documentation support, etc. > > Thanks > > > Yoram Rovner > yoram@puc.clArticle: 33852
Yoram Rovner wrote: > Hello: > > I need an advice on which fpga board buy. Somebody could tell me which > one has best software, documentation support, etc. Which FPGA manufacturer? Which FPGA family? What price range? What level (beginner, intermediate, advanced)? What types of interface (PCI, parallel port, video, audio,...)? etc, etc, etc Without more requirements, you will get many pointers from this group that don't match your needs. That said, you could get a lot of appropriate references by using google to search comp.arch.fpga for messages in the past year that refer to FPGA Boards. Or visit www.optimagic.com and look at their list of FPGA boards. Finally, you could look at www.xess.com for a list of Xilinx-based boards manufactured by my company. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 33853
Ich bin Hardwareentwickler und suche nach einer Stelle. Vielleicht kann jemand mir zeigen. Wo sind im Internet Job WWW für ASIC, FPGA, VHDL. -- Andrew Buckin ipm_grp@yahoo.com AndrewBuckin@aol.com http://www.geocities.com/ipm_grp/Article: 33854
No, only if it remains balanced on the edge. Otherwise select which ever one it falls on. Synplicity supports a wider range of devices, but then if you aren't going to be using things like Atmel, then that advantage is gone. Ben Franchuk wrote: > "Nope - if the coin rolls on its edge then take FPGA Express. :-) > > -- > Standard Disclaimer : 97% speculation 2% bad grammar 1% facts. > "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk > Now with schematics. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33855
Does anyone have a copy of the book listed below that they would be willing to sell? VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design By Golze, Ulrich (other contributor) Published by Springer-Verlag New York, Incorporated (February 1996) ISBN: 3540600329 Number of pages: 358 Binding: Weight: 1.57 lbs. Dimensions: 9.53 in. by 6.39 in. by 1.19 in.Article: 33856
Ray Andraka <ray@andraka.com> writes: >glen herrmannsfeldt wrote: >> I once did a Xilinx design with a saturating adder. In most cases, >> I only had to worry about underflow, not overflow. At the end >> of the carry chain, with one FG I could detect the underflow, and >> then use the otherwise unused input on the rest of the FG to >> generate the saturated value. In the one case with an overflow, >> the I passed the signal on to the following stage, which had an >> extra input available. (snip) >This is true for the 4K series where the carry chain inputs come from the >LUT inputs. In VIrtex and VIrtexII architectures, the carry chain is >after the LUT, so the LUT is not free for anything else if you use the >carry chain. >The 4K series allowed you to use the carry chain to do a compare against a >limit. The carry out and a sign bit could operate a limit mux implemented >in the LUTs of the same CLBs. If you could accept an odd limit value, you >get bipolar 2's complement limiting to an arbitrary odd value, or to full >scale +/1 in a single column of CLBs. The virtex structure requires 2 >layers to do the same because of the way the carry chain is structured. Yes, that was 4K series. I have the new book, but I hadn't yet figured that this ability was gone. Still, it seems that the Virtex are enough larger to make up the difference, at least in price/CLB. thanks, -- glenArticle: 33857
Or you could get FinSim Developer for only $2500. Alex Fintronic USA http://www.fintronic.com Dan Notestein wrote: > VeriLogger Pro is available on PC for $3000. You can download an eval > copy from the location below: > > -- > For a FREE evaluation of Timing Diagrammer, WaveFormer, VeriLogger, or > TestBencher Pro, visit our web site: http://www.syncad.com > ****************************************************************** > SynaptiCAD, Inc. Sales: (800) 804-7073 > P.O. Box 10608 Support: (540) 953-3390 > Blacksburg, VA 24062-0608 Fax: (540) 953-3078 > ftp: www.syncad.com email: sales@syncad.com > > "Dave Feustel" <dfeustel@mindspring.com> wrote in message > news:9jugr9$5vr$1@slb4.atl.mindspring.net... > > Modelsim licensing refuses to work on my computer. > > > > What alternatives to Modelsim are there for Verilog simulation > > on Windows 2000? > > > > Thanks. > > > >Article: 33858
I appreciate the suggestion, but I can't afford *any* Verilog software that costs more than a few hundred dollars at most. Also, if it doesn't do synthesis for Xilinx Spartan-II and Virtex-II chips, it doesn't provide me with the essential capability I need. "Alexandru Seibulescu" <alex@fintronic.com> wrote in message news:3B6F45FE.F5C0479@fintronic.com... > Or you could get FinSim Developer for only $2500. > > Alex > Fintronic USA > http://www.fintronic.com > > Dan Notestein wrote: > > > VeriLogger Pro is available on PC for $3000. You can download an eval > > copy from the location below: > > > > -- > > For a FREE evaluation of Timing Diagrammer, WaveFormer, VeriLogger, or > > TestBencher Pro, visit our web site: http://www.syncad.com > > ****************************************************************** > > SynaptiCAD, Inc. Sales: (800) 804-7073 > > P.O. Box 10608 Support: (540) 953-3390 > > Blacksburg, VA 24062-0608 Fax: (540) 953-3078 > > ftp: www.syncad.com email: sales@syncad.com > > > > "Dave Feustel" <dfeustel@mindspring.com> wrote in message > > news:9jugr9$5vr$1@slb4.atl.mindspring.net... > > > Modelsim licensing refuses to work on my computer. > > > > > > What alternatives to Modelsim are there for Verilog simulation > > > on Windows 2000? > > > > > > Thanks. > > > > > > >Article: 33859
This is a multi-part message in MIME format. ------=_NextPart_000_0005_01C11F2E.60877010 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: base64 SGksDQogICBJIG5vdyB3YW50IHRvIGdlbmVyYXRlICoudmZlIGZpbGUgZnJvbSB2aWV3ZHJhdz8N Cg0K ------=_NextPart_000_0005_01C11F2E.60877010 Content-Type: text/html; charset="gb2312" Content-Transfer-Encoding: base64 PCFET0NUWVBFIEhUTUwgUFVCTElDICItLy9XM0MvL0RURCBIVE1MIDQuMCBUcmFuc2l0aW9uYWwv L0VOIj4NCjxIVE1MPjxIRUFEPg0KPE1FVEEgY29udGVudD0idGV4dC9odG1sOyBjaGFyc2V0PWdi MjMxMiIgaHR0cC1lcXVpdj1Db250ZW50LVR5cGU+DQo8TUVUQSBjb250ZW50PSJNU0hUTUwgNS4w MC4zMzE1LjI4NzAiIG5hbWU9R0VORVJBVE9SPg0KPFNUWUxFPjwvU1RZTEU+DQo8L0hFQUQ+DQo8 Qk9EWSBiZ0NvbG9yPSNmZmZmZmY+DQo8RElWPjxGT05UIHNpemU9Mj5IaSw8L0ZPTlQ+PC9ESVY+ DQo8RElWPjxGT05UIHNpemU9Mj4mbmJzcDsmbmJzcDsgSSBub3cgd2FudCB0byBnZW5lcmF0ZSAq LnZmZSBmaWxlIGZyb20gDQp2aWV3ZHJhdz88L0ZPTlQ+PC9ESVY+DQo8RElWPiZuYnNwOzwvRElW PjwvQk9EWT48L0hUTUw+DQo= ------=_NextPart_000_0005_01C11F2E.60877010-- -- Posted from seic8.seu.edu.cn [202.119.24.18] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 33860
Ulf Samuelsson wrote: > > > One thought about simulation times, I have used Modelsim and noticed > > that they have several different versions with claimed speed > > differences. It occurred to me that it would be very expensive for them > > to offer two or more different lines of code in the different products. > > So it is very likely that they are running the exact same code core in > > all of their products. The difference is in a switch which tells the > > software how fast to run. This kicks in a speed reduction routine in the > > slower versions of the code. Depending on how they implement the speed > > reduction, you will see very different results in benchmarks on > > different machines. This is just my theory, I have not tested this or > > asked Modelsim if this is true. But it only makes sense since there > > would be no advantage to them to maintaining two lines of distinct code. > > > > > > AFAIK, the more advanced/expensive versions will apply more optimization > to the simulation algorithm, which will make them run faster. > > -- > Best regards, > ulf at atmel dot com > The contents of this message is intended to be my private opinion and > may or may not be shared by my employer Atmel Sweden That is what they say, but why would they spend extra money to maintain multiple lines of code when they could have one line of code with full optimizations and just use a switch to slow down the "less expensive" versions. Having multiple lines of code gives them no advantage and costs them extra money. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 33861
Wo suchen Sie Job-- in Deutschland oder USA? In Amerika es ist jetzt schwer. Vielleicht suche ich Job in D-land. "Buckin" <ipm_grp@freenet.de> wrote in message news:9kn1mo$5g5d3$1@ID-63439.news.dfncis.de... > > Ich bin Hardwareentwickler und suche nach einer Stelle. > > Vielleicht kann jemand mir zeigen. > > Wo sind im Internet Job WWW für ASIC, FPGA, VHDL. > > -- > Andrew Buckin > ipm_grp@yahoo.com > AndrewBuckin@aol.com > http://www.geocities.com/ipm_grp/ > > >Article: 33862
Some responses: - For best speed, make sure the inputs and outputs of the commutator are registered. That includes the select inputs. Also, if the output is registered, then you can have the output asynchronously reset to zero without using the reset as a combinational input. - Don't use one-hot for the select lines. The decoder will require fewer levels of logic if the selects are encoded. - I think the CIC is a comb filter, which means all the coefficients are 1. It's small and fast since there's no multipliers, but has a poor response. I think in order to use it you would have to predistort the SRRC to compensate for the CIC distortion. I don't know if this cascade would be configurable for different interpolation rates, because the SRRC would have to predistort differently for each interpolation rate. I don't know if using a CIC would help. -Kevin "Antonio" <dottavio@ised.it> wrote in message news:fb35ea96.0108060040.21723a4@posting.google.com... > Good Morning , > here are some question concerning a polyphase filter I'm realizing, > could you help me on this ?? > > 1) At the output of the polyphase there is a mux that choise one of > the six fir output (..this polyphase interpolate 6) , it is supplied > with a counter modulo 6, I've the clock only on the counter and not on > the mux, is this right by your point of view ?? > > 2) this is the code for the mux : > > library ieee; > use ieee.std_logic_1164.all; > > entity commutatore_6 is > port(in_0, in_1, in_2, in_3, in_4, in_5 : in std_logic_vector(11 > downto 0); > sel : in std_logic_vector(2 downto 0); > out_comm : out std_logic_vector(11 downto 0)); > end commutatore_6; > > architecture comm_arch of commutatore_6 is > begin > with sel select > out_comm <= in_0 when "000", > in_1 when "001", > in_2 when "010", > in_3 when "011", > in_4 when "100", > in_5 when "101", > "XXXXXXXXXXXX" when others ; > end comm_arch ; > > > > how I can insert a reset that produce out_comm = "000000000000" when > reset = 1 ?? > > 3) for the counter output corrisponding to the sel of the multiplier, > it is better to use one hot encoding like in state machine or it is > correct in the way I made, three bits for 6 states ??? > > 4) To insert the coefficients in the polyphase is better to use the > function conv_std_logic or directly to map the binary rappresentation > of the coefficient in the VHDL code ?? > > 5) Last and strong question : > with this polyphase I interpolate and produce also SRRC filtering but > someone told me that this is not a flexible architecture, it is better > to add also a CIC that it's a programmable interpolator, but how I can > interpolate 3 , 4 , and 6 using a cascade of a polyphase filter > (..that must interpolate at least 2 and ) and a CIC filter ?? >Article: 33863
My opinion on flow:
-use your own text editor (emacs for NT)
-Modelsim for simulation
-Synplify for synthesis (with HDL analyst option)
-Alliance for P&R
Using each of these tools independently is much better than trying to use a
"development environment". Foundation and Renoir will just muck up
everything with an excess of files and wrappers and will waste your time.
-Kevin
"Jaime Andres Aranguren Cardona" <jaime.aranguren@ieee.org> wrote in message
news:14a86f87.0108041640.566095ab@posting.google.com...
> Hi all!
>
> Thanks a lot for the replies, gurus. Yuu are right, I was confused.
> The compiler should "translate" from an assembly file to the
> programmable .hex file.
>
> But the new question is, perhaps more general, and regarding the
> design tools.
> What represents the best choice for a development environment: Xilinx
> Foundation 3.1i or Renoir 99? The first one is vendor specific, and
> the second one is perhaps more industry standard, as long as I know.
>
> Would you please give suggestions about which one to use?
>
> Thanks a lot
>
>
> "Andy Peters <andy [@] exponentmedia" <".> com"> wrote in message
news:<sDCa7.1826$cd1.226381@newsread1.prod.itd.earthlink.net>...
> > Jaime Andres Aranguren Cardona wrote:
> >
> > > - Should write our own compiler ("our" assembler -> bitsteram)
> >
> > Your assembler won't be able to write out a Xilinx bitstream. Why not
> > do what the single-chip micros do, and have a program EPROM (or EEPROM,
> > or whatever)? The "program" should exist independent of the FPGA
> > implementation of the processor. Just make sure your CPU accesses the
> > EPROM when reset. :)
> >
> > The neat thing about rolling the CPU into an FPGA is that your "CPU" can
> > have external-device chip selects that do exactly what you want them to,
> > and as many as you want (within reason, of course). And you can tailor
> > external bus cycles to whatever hardware you're talking to: slow EPROM,
> > fast SRAM, whatever.
> >
> > -andy
>
Article: 33864The CIC is a recursive implementation of a boxcar filter. It is physically an integrator (accumulation of signal samples) cascaded with a comb filter (subtraction of delayed signal from signal). Its response is the sinc function with the positions of the nulls defined by the delay of the subtracted signal. It can be made into a high order interpolator or decimator by inserting a zero stuffing (for interpolation) or sampling stage between the integrator and comb sections. The nice thing about this particular filter is that the response referred to the lower sampling rate side is relatively constant regardless of the amount of decimation/interpolation as long as the ratio is greater than about 16. That means your compensating / cutoff filter can be a constant filter even though you can support a wide range of decimation ratios. Also, if you limit the output passband to a small portion of the area before the first null (with that constant compensation filter), the aliases from the rate change fall into the nulls when you fold the spectrum, so you get much better than the 13 dB rejection of the top of the first lobe. If you are using a small portion of the area around DC, the compensation for the sinx/x can be easily applied before or after the CIC, so a predistortion is not needed. Kevin Neilson wrote: > Some responses: > - For best speed, make sure the inputs and outputs of the commutator are > registered. That includes the select inputs. Also, if the output is > registered, then you can have the output asynchronously reset to zero > without using the reset as a combinational input. > - Don't use one-hot for the select lines. The decoder will require fewer > levels of logic if the selects are encoded. > - I think the CIC is a comb filter, which means all the coefficients are 1. > It's small and fast since there's no multipliers, but has a poor response. > I think in order to use it you would have to predistort the SRRC to > compensate for the CIC distortion. I don't know if this cascade would be > configurable for different interpolation rates, because the SRRC would have > to predistort differently for each interpolation rate. I don't know if > using a CIC would help. > > -Kevin > > "Antonio" <dottavio@ised.it> wrote in message > news:fb35ea96.0108060040.21723a4@posting.google.com... > > Good Morning , > > here are some question concerning a polyphase filter I'm realizing, > > could you help me on this ?? > > > > 1) At the output of the polyphase there is a mux that choise one of > > the six fir output (..this polyphase interpolate 6) , it is supplied > > with a counter modulo 6, I've the clock only on the counter and not on > > the mux, is this right by your point of view ?? > > > > 2) this is the code for the mux : > > > > library ieee; > > use ieee.std_logic_1164.all; > > > > entity commutatore_6 is > > port(in_0, in_1, in_2, in_3, in_4, in_5 : in std_logic_vector(11 > > downto 0); > > sel : in std_logic_vector(2 downto 0); > > out_comm : out std_logic_vector(11 downto 0)); > > end commutatore_6; > > > > architecture comm_arch of commutatore_6 is > > begin > > with sel select > > out_comm <= in_0 when "000", > > in_1 when "001", > > in_2 when "010", > > in_3 when "011", > > in_4 when "100", > > in_5 when "101", > > "XXXXXXXXXXXX" when others ; > > end comm_arch ; > > > > > > > > how I can insert a reset that produce out_comm = "000000000000" when > > reset = 1 ?? > > > > 3) for the counter output corrisponding to the sel of the multiplier, > > it is better to use one hot encoding like in state machine or it is > > correct in the way I made, three bits for 6 states ??? > > > > 4) To insert the coefficients in the polyphase is better to use the > > function conv_std_logic or directly to map the binary rappresentation > > of the coefficient in the VHDL code ?? > > > > 5) Last and strong question : > > with this polyphase I interpolate and produce also SRRC filtering but > > someone told me that this is not a flexible architecture, it is better > > to add also a CIC that it's a programmable interpolator, but how I can > > interpolate 3 , 4 , and 6 using a cascade of a polyphase filter > > (..that must interpolate at least 2 and ) and a CIC filter ?? > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33865
glen herrmannsfeldt wrote: > Ray Andraka <ray@andraka.com> writes: > > >glen herrmannsfeldt wrote: > > >> I once did a Xilinx design with a saturating adder. In most cases, > >> I only had to worry about underflow, not overflow. At the end > >> of the carry chain, with one FG I could detect the underflow, and > >> then use the otherwise unused input on the rest of the FG to > >> generate the saturated value. In the one case with an overflow, > >> the I passed the signal on to the following stage, which had an > >> extra input available. > (snip) > >This is true for the 4K series where the carry chain inputs come from the > >LUT inputs. In VIrtex and VIrtexII architectures, the carry chain is > >after the LUT, so the LUT is not free for anything else if you use the > >carry chain. > > >The 4K series allowed you to use the carry chain to do a compare against a > >limit. The carry out and a sign bit could operate a limit mux implemented > >in the LUTs of the same CLBs. If you could accept an odd limit value, you > >get bipolar 2's complement limiting to an arbitrary odd value, or to full > >scale +/1 in a single column of CLBs. The virtex structure requires 2 > >layers to do the same because of the way the carry chain is structured. > > Yes, that was 4K series. I have the new book, but I hadn't yet > figured that this ability was gone. > > Still, it seems that the Virtex are enough larger to make up the > difference, at least in price/CLB. and enough new features to offset the loss in most cases. Most notably the SRL16, block rams, and ability to double the clock with DLLs > > > thanks, > > -- glen -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33866
i have a working prototype of something i think is pretty cool based on a microcontroller and a small fpga. without resorting to the "venture funding...hire a bunch of staff...burn through a lot of money...and fold cycle" what kind of step should i take next? i am currently in the bay area and i would really like to just market my product on a small scale, where i don't need any funding except something i can afford...very little with the market downturn here. i have heard that some companies will buy designs directly...is there any kind of a broker for this? the last thing i want to get into is manufacturing. i just enjoy the design aspect. also, how about if i just want to design things for other companies... i believe both my hardware and software skills are up to par, and with my partner, we can crank out designs quite swiftly. does anyone know how to go about entering this area? thanks all. chrisArticle: 33867
I've the following accumulator :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity accumulatore is
port ( clk, load, clear : in std_logic;
theta : inout std_logic_vector(31 downto 0)
);
end accumulatore;
architecture acc_arch of accumulatore is
signal reg_theta : std_logic_vector(31 downto 0);
begin
process(load, clear, theta)
begin
if load='1' then
reg_theta <= "01000000000000000011000000000000";
else if clear='1' then
reg_theta <= "00000000000000000000000000000000";
else
reg_theta <= "01000000000000000011000000000000" + theta;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
theta <= reg_theta;
end if;
end process;
end acc_arch;
It doesn't respect my constrain on timing of 6.05ns for the clock, in
fact this is the report
that I've from XST at the end of the implementation :
--------------------------------------------------------------------------------
Xilinx TRACE, Version D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
trce -e 3 -l 3 accumulatore.ncd -o accumulatore.twr accumulatore.pcf
Design file: accumulatore.ncd
Physical constraint file: accumulatore.pcf
Device,speed: xcv1000,-4 (FINAL 1.115 2001-04-07)
Report level: error report
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 6.700 nS HIGH
50.000 % ;
222 items analyzed, 17 timing errors detected.
Minimum period is 7.959ns.
--------------------------------------------------------------------------------
Slack: -1.259ns path theta_13_OBUF to theta_28_OBUF relative to
7.928ns total path delay
0.031ns clock skew
6.700ns delay constraint
Path theta_13_OBUF to theta_28_OBUF contains 10 levels of logic:
Path starting from Comp: CLB_R62C7.S0.CLK (from clk_BUFGP)
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
CLB_R62C7.S0.XQ Tcko 1.372R theta_13_OBUF
I_theta_13
CLB_R62C7.S1.G1 net (fanout=2) 1.417R theta_13_OBUF
CLB_R62C7.S1.COUT Topcyg 1.579R I1_inst_sum_0
I1_inst_inv_13
I1_inst_cy_l_1
CLB_R61C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_1/O
CLB_R61C7.S1.COUT Tbyp 0.109R I1_inst_sum_2
I1_inst_cy_l_2
I1_inst_cy_l_3
CLB_R60C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_3/O
CLB_R60C7.S1.COUT Tbyp 0.109R I1_inst_sum_4
I1_inst_cy_l_4
I1_inst_cy_l_5
CLB_R59C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_5/O
CLB_R59C7.S1.COUT Tbyp 0.109R I1_inst_sum_6
I1_inst_cy_l_6
I1_inst_cy_l_7
CLB_R58C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_7/O
CLB_R58C7.S1.COUT Tbyp 0.109R I1_inst_sum_8
I1_inst_cy_l_8
I1_inst_cy_l_9
CLB_R57C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_9/O
CLB_R57C7.S1.COUT Tbyp 0.109R I1_inst_sum_10
I1_inst_cy_l_10
I1_inst_cy_l_11
CLB_R56C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_11/O
CLB_R56C7.S1.COUT Tbyp 0.109R I1_inst_sum_12
I1_inst_cy_l_12
I1_inst_cy_l_13
CLB_R55C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_13/O
CLB_R55C7.S1.Y Tciny 0.590R I1_inst_sum_14
I1_inst_cy_l_14
I1_inst_sum_15
CLB_R54C7.S0.G4 net (fanout=1) 0.817R I1_inst_sum_15
CLB_R54C7.S0.CLK Tick 1.499R theta_28_OBUF
I_reg_theta_27
I_theta_27
-------------------------------------------------
Total (5.694ns logic, 2.234ns route) 7.928ns (to clk_BUFGP)
(71.8% logic, 28.2% route)
--------------------------------------------------------------------------------
Slack: -1.213ns path theta_13_OBUF to theta_3_OBUF relative to
7.879ns total path delay
0.034ns clock skew
6.700ns delay constraint
Path theta_13_OBUF to theta_3_OBUF contains 11 levels of logic:
Path starting from Comp: CLB_R62C7.S0.CLK (from clk_BUFGP)
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
CLB_R62C7.S0.XQ Tcko 1.372R theta_13_OBUF
I_theta_13
CLB_R62C7.S1.G1 net (fanout=2) 1.417R theta_13_OBUF
CLB_R62C7.S1.COUT Topcyg 1.579R I1_inst_sum_0
I1_inst_inv_13
I1_inst_cy_l_1
CLB_R61C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_1/O
CLB_R61C7.S1.COUT Tbyp 0.109R I1_inst_sum_2
I1_inst_cy_l_2
I1_inst_cy_l_3
CLB_R60C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_3/O
CLB_R60C7.S1.COUT Tbyp 0.109R I1_inst_sum_4
I1_inst_cy_l_4
I1_inst_cy_l_5
CLB_R59C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_5/O
CLB_R59C7.S1.COUT Tbyp 0.109R I1_inst_sum_6
I1_inst_cy_l_6
I1_inst_cy_l_7
CLB_R58C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_7/O
CLB_R58C7.S1.COUT Tbyp 0.109R I1_inst_sum_8
I1_inst_cy_l_8
I1_inst_cy_l_9
CLB_R57C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_9/O
CLB_R57C7.S1.COUT Tbyp 0.109R I1_inst_sum_10
I1_inst_cy_l_10
I1_inst_cy_l_11
CLB_R56C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_11/O
CLB_R56C7.S1.COUT Tbyp 0.109R I1_inst_sum_12
I1_inst_cy_l_12
I1_inst_cy_l_13
CLB_R55C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_13/O
CLB_R55C7.S1.COUT Tbyp 0.109R I1_inst_sum_14
I1_inst_cy_l_14
I1_inst_cy_l_15
CLB_R54C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_15/O
CLB_R54C7.S1.Y Tciny 0.590R I1_inst_sum_16
I1_inst_cy_l_16
I1_inst_sum_17
CLB_R54C6.S1.G2 net (fanout=1) 0.659R I1_inst_sum_17
CLB_R54C6.S1.CLK Tick 1.499R theta_3_OBUF
I_reg_theta_29
I_theta_29
-------------------------------------------------
Total (5.803ns logic, 2.076ns route) 7.879ns (to clk_BUFGP)
(73.7% logic, 26.3% route)
--------------------------------------------------------------------------------
Slack: -1.150ns path theta_15_OBUF to theta_28_OBUF relative to
7.819ns total path delay
0.031ns clock skew
6.700ns delay constraint
Path theta_15_OBUF to theta_28_OBUF contains 9 levels of logic:
Path starting from Comp: CLB_R61C7.S0.CLK (from clk_BUFGP)
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
CLB_R61C7.S0.XQ Tcko 1.372R theta_15_OBUF
I_theta_15
CLB_R61C7.S1.G1 net (fanout=2) 1.417R theta_15_OBUF
CLB_R61C7.S1.COUT Topcyg 1.579R I1_inst_sum_2
theta_15_OBUF_rt
I1_inst_cy_l_3
CLB_R60C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_3/O
CLB_R60C7.S1.COUT Tbyp 0.109R I1_inst_sum_4
I1_inst_cy_l_4
I1_inst_cy_l_5
CLB_R59C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_5/O
CLB_R59C7.S1.COUT Tbyp 0.109R I1_inst_sum_6
I1_inst_cy_l_6
I1_inst_cy_l_7
CLB_R58C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_7/O
CLB_R58C7.S1.COUT Tbyp 0.109R I1_inst_sum_8
I1_inst_cy_l_8
I1_inst_cy_l_9
CLB_R57C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_9/O
CLB_R57C7.S1.COUT Tbyp 0.109R I1_inst_sum_10
I1_inst_cy_l_10
I1_inst_cy_l_11
CLB_R56C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_11/O
CLB_R56C7.S1.COUT Tbyp 0.109R I1_inst_sum_12
I1_inst_cy_l_12
I1_inst_cy_l_13
CLB_R55C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_13/O
CLB_R55C7.S1.Y Tciny 0.590R I1_inst_sum_14
I1_inst_cy_l_14
I1_inst_sum_15
CLB_R54C7.S0.G4 net (fanout=1) 0.817R I1_inst_sum_15
CLB_R54C7.S0.CLK Tick 1.499R theta_28_OBUF
I_reg_theta_27
I_theta_27
-------------------------------------------------
Total (5.585ns logic, 2.234ns route) 7.819ns (to clk_BUFGP)
(71.4% logic, 28.6% route)
--------------------------------------------------------------------------------
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src/Dest| Src/Dest| Src/Dest| Src/Dest|
Source Clock |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|
---------------+---------+---------+---------+---------+
clk | 7.959| | | |
---------------+---------+---------+---------+---------+
Table of Timegroups:
-------------------
TimeGroup clk:
BELs:
I_theta_0 I_theta_1 I_theta_10 I_theta_11 I_theta_12
I_theta_13 I_theta_14 I_theta_15 I_theta_16 I_theta_17
I_theta_18 I_theta_19 I_theta_2 I_theta_20 I_theta_21
I_theta_22 I_theta_23 I_theta_24 I_theta_25 I_theta_26
I_theta_27 I_theta_28 I_theta_29 I_theta_3 I_theta_30
I_theta_31 I_theta_4 I_theta_5 I_theta_6 I_theta_7
I_theta_8 I_theta_9
Timing summary:
---------------
Timing errors: 17 Score: 11434
Constraints cover 222 paths, 0 nets, and 142 connections (81.6%
coverage)
Design statistics:
Minimum period: 7.959ns (Maximum frequency: 125.644MHz)
Analysis completed Mon Aug 06 21:07:33 2001
--------------------------------------------------------------------------------
My question is :
1) If I don't want to change the vhdl but just to obtain the best from
this code, what I've to
do, Xilinx suggest to use the timing analyzer but how ??
2) it is a good idea to use the floorplanner ?? if yes how ???
3) what about FPGA editor, I know how to use it only to see the result
of implementation, but
how I can use it to better fit the VHDL code ???
4) Which of the one million option of the synthesis and of the
implementation do you suggest me to use ??
Thanks ...
Antonio D'Ottavio
Article: 33868How do I build a 28 bit wide counter that runs at 200MHz, in Spartan ii?Article: 33869
What is the best reconfigurable PCI processor board to use as a computation accelerator? Jason MorrisArticle: 33871
200 MHz is just beyond what the native 28 bit carry chain will do in the SpartanII-6. You'll have to resort to pipelining or using a carry lookahead, probably in 3-4 sections. "L. Heijnen" wrote: > How do I build a 28 bit wide counter that runs at 200MHz, in Spartan ii? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33872
I agree on these arguments but my problem is always how to design the
cascade of Polyphase and CIC , now I say a stupid thing, for example
(remember that the interpolation rates I need are 3 , 4, and 6) I can
have a fixed interpolation of 24 with the Polyphase and then decimate
8 or 6 or 4 with the CIC , but this don't seems to me a good solution
how to have three different polyphase filters or also one with
variable coefficients, do you agree on this ???
Bye & Thanks ...
Antonio D'Ottavio
Article: 33873I've been trying to work out a vhdl design flow in the last few weeks after using maxplus2 ahdl for a while. The thing i found most irritating with ahdl (if i haven't missed something) is that you can only have one subdesign per file. Also, simulations are kind of limited to a gui waveform simulator, which gets messy when you want to see what happens after a few thousand states or clock cycles. AHDL is well suited for smaller designs, if portability doesn't matter. I'm now using ultra-edit + vhdl-simili, to simulate. When the simulation testbench works, i'll synthesize using altera-leonardo, then generate the device file with maxplus2. All the tools are free except the editor, which is cheap, but not crap (its really quite excellent;) Jaime Andres Aranguren Cardona wrote: > > Hi, everybody. > > Want to generate opinions, from diverse kind of professionals, about > the Design Tools used for FPGA/CPLD/ASIC designs. > > What is the industry-standard method for design? Is it text based > VHDL/Verilog entry, text based test benches generation and graphical > simulation? Or do professionals prefer alternate ways, such Finite > State Machines (graphical entry), Block Diagrams, Truth Tables and/or > Schematics? > > And what can be considered more "universal" and "standard", between > tools like Xilinx's Foundation and Mentor Graphics' Renoir, ModelSim > and Leonardo Spectrum? > > I expect to generate an instructive discussion topic, invlolving > people from industry and academic spheres. > > Best regards, > > Jaime Andres Aranguren Cardona > jaime.aranguren@ieee.org > jaime.aranguren@computer.org -- ___ ___ / /\ / /\ / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ /__/ / Victoria, Australia, Down-Under /__/\/\/ \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ \__\/ \__\/Article: 33874
The timing is agressive for a -4 speed grade part and a 32 bit wide accumulator. It does however
appear that the synthesis is only generating a 15 bit accumulator. It would be helpful to see what it
is producing...something like HDL analyst in synplicity is invaluable here. Looking at your timing
report, it looks like you have an additional layer of logic between the carry chain and the register,
which is consistent with your load and clear. Just by changing the design description so that it can
be done without logic after the carry chain will shave better than a ns off the path time.
The sync clear on the flip-flop can achieve the clear function, and a good synthesizer will do that,
however the clear has to be the highest priority for that to work. I think you may be getting a mux
between the carry chain and the register though because of the load signal. Note that your load value
is the same as the increment value, so you could do the same thing by gating the feedback. By doing it
this way, the structure is already in a form that maps into the virtex architecture so the mux between
the carry and the register is eliminated. That said, you also need to look at why you are not getting
your full accumulator. Part of it is because the 12 lsbs are always '0', so you really have a 20 bit
accumulator. Twenty bits is probably going to fall a little short of your 6.05 ns cycle in a -4 part.
You may need to pipeline the accumulator. Pipelining breaks the accumulator into tow segments.
Register the carry out from the lower segment and use that registered carry as carry in to the upper
segment. You'll have to delay the output bits from the lower segment (if you are using them) to
time-align them with the upper half, and you'll have to delay the inputs to the upper half (load,
clear) to get them aligned. Your alternatives are using a faster speed grade part or accepting a
smaller accumulator. A 20 bit carry chain in the -4 part is good to about 150 MHz if everything is
perfect in the design and layout.
library ieee;
use ieee.std_logic.1164.all;
use ieee.numeric_std.all; --use this rather than std_logic_arith and signed. It is standard across
tools unlike the std_logic stuff
entity accumulatore is
port ( clk, load, clear : in std_logic;
theta : inout std_logic_vector(31 downto 0)
);
end accumulatore;
architecture acc_arch of accumulatore is
signal increment : std_logic_vector(31 downto 0);
signal feedback : std_logic_vector(31 downto 0);
signal reg_theta : std_logic_vector(31 downto 0);
begin
feedback<= reg_theta when load='1' else (others=>'0');
increment<= (others=>'0') when clear='1' else "01000000000000000011000000000000";
reg_theta<= feedback + increment;
process(clk)
begin
if clk'event and clk='1' then
theta <= reg_theta;
end if;
end process;
end acc_arch;
Antonio wrote:
> I've the following accumulator :
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_signed.all;
>
> entity accumulatore is
> port ( clk, load, clear : in std_logic;
> theta : inout std_logic_vector(31 downto 0)
> );
> end accumulatore;
>
> architecture acc_arch of accumulatore is
> signal reg_theta : std_logic_vector(31 downto 0);
> begin
> process(load, clear, theta)
> begin
> if load='1' then
> reg_theta <= "01000000000000000011000000000000";
> else if clear='1' then
> reg_theta <= "00000000000000000000000000000000";
> else
> reg_theta <= "01000000000000000011000000000000" + theta;
> end if;
> end if;
> end process;
>
> process(clk)
> begin
> if clk'event and clk='1' then
> theta <= reg_theta;
> end if;
> end process;
> end acc_arch;
>
> It doesn't respect my constrain on timing of 6.05ns for the clock, in
> fact this is the report
> that I've from XST at the end of the implementation :
>
> --------------------------------------------------------------------------------
> Xilinx TRACE, Version D.27
> Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
>
> trce -e 3 -l 3 accumulatore.ncd -o accumulatore.twr accumulatore.pcf
>
> Design file: accumulatore.ncd
> Physical constraint file: accumulatore.pcf
> Device,speed: xcv1000,-4 (FINAL 1.115 2001-04-07)
> Report level: error report
> --------------------------------------------------------------------------------
>
> ================================================================================
> Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 6.700 nS HIGH
> 50.000 % ;
> 222 items analyzed, 17 timing errors detected.
> Minimum period is 7.959ns.
> --------------------------------------------------------------------------------
> Slack: -1.259ns path theta_13_OBUF to theta_28_OBUF relative to
> 7.928ns total path delay
> 0.031ns clock skew
> 6.700ns delay constraint
>
> Path theta_13_OBUF to theta_28_OBUF contains 10 levels of logic:
> Path starting from Comp: CLB_R62C7.S0.CLK (from clk_BUFGP)
> To Delay type Delay(ns) Physical Resource
> Logical Resource(s)
> ------------------------------------------------- --------
> CLB_R62C7.S0.XQ Tcko 1.372R theta_13_OBUF
> I_theta_13
> CLB_R62C7.S1.G1 net (fanout=2) 1.417R theta_13_OBUF
> CLB_R62C7.S1.COUT Topcyg 1.579R I1_inst_sum_0
> I1_inst_inv_13
> I1_inst_cy_l_1
> CLB_R61C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_1/O
> CLB_R61C7.S1.COUT Tbyp 0.109R I1_inst_sum_2
> I1_inst_cy_l_2
> I1_inst_cy_l_3
> CLB_R60C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_3/O
> CLB_R60C7.S1.COUT Tbyp 0.109R I1_inst_sum_4
> I1_inst_cy_l_4
> I1_inst_cy_l_5
> CLB_R59C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_5/O
> CLB_R59C7.S1.COUT Tbyp 0.109R I1_inst_sum_6
> I1_inst_cy_l_6
> I1_inst_cy_l_7
> CLB_R58C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_7/O
> CLB_R58C7.S1.COUT Tbyp 0.109R I1_inst_sum_8
> I1_inst_cy_l_8
> I1_inst_cy_l_9
> CLB_R57C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_9/O
> CLB_R57C7.S1.COUT Tbyp 0.109R I1_inst_sum_10
> I1_inst_cy_l_10
> I1_inst_cy_l_11
> CLB_R56C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_11/O
> CLB_R56C7.S1.COUT Tbyp 0.109R I1_inst_sum_12
> I1_inst_cy_l_12
> I1_inst_cy_l_13
> CLB_R55C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_13/O
> CLB_R55C7.S1.Y Tciny 0.590R I1_inst_sum_14
> I1_inst_cy_l_14
> I1_inst_sum_15
> CLB_R54C7.S0.G4 net (fanout=1) 0.817R I1_inst_sum_15
> CLB_R54C7.S0.CLK Tick 1.499R theta_28_OBUF
> I_reg_theta_27
> I_theta_27
> -------------------------------------------------
> Total (5.694ns logic, 2.234ns route) 7.928ns (to clk_BUFGP)
> (71.8% logic, 28.2% route)
>
> --------------------------------------------------------------------------------
> Slack: -1.213ns path theta_13_OBUF to theta_3_OBUF relative to
> 7.879ns total path delay
> 0.034ns clock skew
> 6.700ns delay constraint
>
> Path theta_13_OBUF to theta_3_OBUF contains 11 levels of logic:
> Path starting from Comp: CLB_R62C7.S0.CLK (from clk_BUFGP)
> To Delay type Delay(ns) Physical Resource
> Logical Resource(s)
> ------------------------------------------------- --------
> CLB_R62C7.S0.XQ Tcko 1.372R theta_13_OBUF
> I_theta_13
> CLB_R62C7.S1.G1 net (fanout=2) 1.417R theta_13_OBUF
> CLB_R62C7.S1.COUT Topcyg 1.579R I1_inst_sum_0
> I1_inst_inv_13
> I1_inst_cy_l_1
> CLB_R61C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_1/O
> CLB_R61C7.S1.COUT Tbyp 0.109R I1_inst_sum_2
> I1_inst_cy_l_2
> I1_inst_cy_l_3
> CLB_R60C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_3/O
> CLB_R60C7.S1.COUT Tbyp 0.109R I1_inst_sum_4
> I1_inst_cy_l_4
> I1_inst_cy_l_5
> CLB_R59C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_5/O
> CLB_R59C7.S1.COUT Tbyp 0.109R I1_inst_sum_6
> I1_inst_cy_l_6
> I1_inst_cy_l_7
> CLB_R58C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_7/O
> CLB_R58C7.S1.COUT Tbyp 0.109R I1_inst_sum_8
> I1_inst_cy_l_8
> I1_inst_cy_l_9
> CLB_R57C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_9/O
> CLB_R57C7.S1.COUT Tbyp 0.109R I1_inst_sum_10
> I1_inst_cy_l_10
> I1_inst_cy_l_11
> CLB_R56C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_11/O
> CLB_R56C7.S1.COUT Tbyp 0.109R I1_inst_sum_12
> I1_inst_cy_l_12
> I1_inst_cy_l_13
> CLB_R55C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_13/O
> CLB_R55C7.S1.COUT Tbyp 0.109R I1_inst_sum_14
> I1_inst_cy_l_14
> I1_inst_cy_l_15
> CLB_R54C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_15/O
> CLB_R54C7.S1.Y Tciny 0.590R I1_inst_sum_16
> I1_inst_cy_l_16
> I1_inst_sum_17
> CLB_R54C6.S1.G2 net (fanout=1) 0.659R I1_inst_sum_17
> CLB_R54C6.S1.CLK Tick 1.499R theta_3_OBUF
> I_reg_theta_29
> I_theta_29
> -------------------------------------------------
> Total (5.803ns logic, 2.076ns route) 7.879ns (to clk_BUFGP)
> (73.7% logic, 26.3% route)
>
> --------------------------------------------------------------------------------
> Slack: -1.150ns path theta_15_OBUF to theta_28_OBUF relative to
> 7.819ns total path delay
> 0.031ns clock skew
> 6.700ns delay constraint
>
> Path theta_15_OBUF to theta_28_OBUF contains 9 levels of logic:
> Path starting from Comp: CLB_R61C7.S0.CLK (from clk_BUFGP)
> To Delay type Delay(ns) Physical Resource
> Logical Resource(s)
> ------------------------------------------------- --------
> CLB_R61C7.S0.XQ Tcko 1.372R theta_15_OBUF
> I_theta_15
> CLB_R61C7.S1.G1 net (fanout=2) 1.417R theta_15_OBUF
> CLB_R61C7.S1.COUT Topcyg 1.579R I1_inst_sum_2
> theta_15_OBUF_rt
> I1_inst_cy_l_3
> CLB_R60C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_3/O
> CLB_R60C7.S1.COUT Tbyp 0.109R I1_inst_sum_4
> I1_inst_cy_l_4
> I1_inst_cy_l_5
> CLB_R59C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_5/O
> CLB_R59C7.S1.COUT Tbyp 0.109R I1_inst_sum_6
> I1_inst_cy_l_6
> I1_inst_cy_l_7
> CLB_R58C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_7/O
> CLB_R58C7.S1.COUT Tbyp 0.109R I1_inst_sum_8
> I1_inst_cy_l_8
> I1_inst_cy_l_9
> CLB_R57C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_9/O
> CLB_R57C7.S1.COUT Tbyp 0.109R I1_inst_sum_10
> I1_inst_cy_l_10
> I1_inst_cy_l_11
> CLB_R56C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_11/O
> CLB_R56C7.S1.COUT Tbyp 0.109R I1_inst_sum_12
> I1_inst_cy_l_12
> I1_inst_cy_l_13
> CLB_R55C7.S1.CIN net (fanout=1) 0.000R I1_inst_cy_l_13/O
> CLB_R55C7.S1.Y Tciny 0.590R I1_inst_sum_14
> I1_inst_cy_l_14
> I1_inst_sum_15
> CLB_R54C7.S0.G4 net (fanout=1) 0.817R I1_inst_sum_15
> CLB_R54C7.S0.CLK Tick 1.499R theta_28_OBUF
> I_reg_theta_27
> I_theta_27
> -------------------------------------------------
> Total (5.585ns logic, 2.234ns route) 7.819ns (to clk_BUFGP)
> (71.4% logic, 28.6% route)
>
> --------------------------------------------------------------------------------
>
> 1 constraint not met.
>
> Data Sheet report:
> -----------------
> All values displayed in nanoseconds (ns)
>
> Clock to Setup on destination clock clk
> ---------------+---------+---------+---------+---------+
> | Src/Dest| Src/Dest| Src/Dest| Src/Dest|
> Source Clock |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|
> ---------------+---------+---------+---------+---------+
> clk | 7.959| | | |
> ---------------+---------+---------+---------+---------+
>
> Table of Timegroups:
> -------------------
> TimeGroup clk:
> BELs:
> I_theta_0 I_theta_1 I_theta_10 I_theta_11 I_theta_12
> I_theta_13 I_theta_14 I_theta_15 I_theta_16 I_theta_17
> I_theta_18 I_theta_19 I_theta_2 I_theta_20 I_theta_21
> I_theta_22 I_theta_23 I_theta_24 I_theta_25 I_theta_26
> I_theta_27 I_theta_28 I_theta_29 I_theta_3 I_theta_30
> I_theta_31 I_theta_4 I_theta_5 I_theta_6 I_theta_7
> I_theta_8 I_theta_9
>
> Timing summary:
> ---------------
>
> Timing errors: 17 Score: 11434
>
> Constraints cover 222 paths, 0 nets, and 142 connections (81.6%
> coverage)
>
> Design statistics:
> Minimum period: 7.959ns (Maximum frequency: 125.644MHz)
>
> Analysis completed Mon Aug 06 21:07:33 2001
> --------------------------------------------------------------------------------
>
> My question is :
> 1) If I don't want to change the vhdl but just to obtain the best from
> this code, what I've to
> do, Xilinx suggest to use the timing analyzer but how ??
> 2) it is a good idea to use the floorplanner ?? if yes how ???
> 3) what about FPGA editor, I know how to use it only to see the result
> of implementation, but
> how I can use it to better fit the VHDL code ???
> 4) Which of the one million option of the synthesis and of the
> implementation do you suggest me to use ??
>
> Thanks ...
>
> Antonio D'Ottavio
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
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