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Hi, I trying to implement an BUS LVDS interface with Virtex-II, but I am getting a little confused. In the document http://www.xilinx.com/products/virtex/handbook/ug002_ch2_lvds.pdf it is said that you still have to use the IOBUF_LVDS primitive (I have used this in Virtex-E) for blvds. BUT this is not recognized by ngbuild. I have seen some documentation that points to other primitives like IOBUFDS together with an IOSTANDARD attribute. My questions is as follows: 1. What primitive should I use for buslvds applications? 2. Is the voltage swing on the bus still +/- 350mV with 2 x 100 Ohms terminations using blvds? (The datasheet confuses me and have spec's on LVDS, not BLVDS.) Thank you for reading! Regards Hakon LisleboArticle: 34351
"Philip Freidin" <philip@fliptronics.com> wrote in message news:chu5otc4n394qaklkj21e0kisubphc5ng4@4ax.com... > On 21 Aug 2001 20:43:17 GMT, gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote: > >What is the maximum clock speed for Virtex-II, FF, through one LUT, > >to another FF? > > In a V-II , -5 speed grade, M3.3.08i speed files, with careful placement, > about 666MHz . > The mark of the beast. See alt.conspiracy.fpgaArticle: 34352
"Michael Boehnel" <boehnel@iti.tu-graz.ac.at> wrote in message news:3B835877.71635D2A@iti.tu-graz.ac.at... > Are there any significant differences between a logic emulated version > (implemented in an FPGA) and an ASIC version. > > I could imagine that at least some timing differences should occure. Are > these timing differences important? Raw speed is usually higher in ASIC, at a given process level. > Are there any other differences? ASICs are a generation or more ahead in density, if you can afford it No tri-states in ASICs (going away in FPGAs) Wierd RAM/ROM configurations in ASICs, regular in FPGAs Embedded DRAM in ASICs Gated clocks in ASICs, less common in FPGAs ASICs are usually lower power > > Can anybody tell practical experiences? > > Michael > > >Article: 34353
I had a look at Celoxica as well, but they want $11,000 for the board... Robin > At this point I'm going to use a board from Celoxica (has a Xilinx FPGA) > pretty nice.. programming it in Handel-C... > > peace, > - MarkArticle: 34354
Joey Oravec <joey@sun.science.wayne.edu> wrote: > partitioning. Synplify Pro is great for many projects, but if you're > doing a serious design you need their higher end tools. They really > need to integrate Amplify and Certify though; right now they seem to > be seperate products. Do you see much advantage with Amplify? Do you see it doing anything which you couldn't do yourself with Synplify Pro and the Xilinx floorplanner? I have access to an Amplify license at work and in my brief experience with it, it just seems to be a way to enter your floorplan and have it appear in an NCF. So I just enter it into the UCF myself, with floorplanner or by hand. I'd like to be proven wrong though. What does the tool itself actually do with the floorplanning information? What optimisations can it make at synthesis time given the floorplan? Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 34355
Celoxica have a couple of cool FPGA protoyping boards, a lower end one (RC100) with a Xilinx SpartanII 200 device on and a load of I/O (video in/out, ps2 ports, parallel ports, leds, 7 segment displays) which comes with a great board support package written in Handel-C, and a high end platform (RC1000) which is a PCI based board designed specifically for data processing operations. The RC1000 features Xilinx Virtex chips (upto V3200E) and four independent RAM banks of up to 8 MB each plus FPGA side and Host side libraries for DMA to memory, host to FPGA communication and memory arbitration. Check them out @ http://www.celoxica.com/products/boards/index.htm Sanjay Maniku Senior Applications Engineer Celoxica Limited 20 Park Gate Milton Park, Abingdon Oxon OX14 4RT Tel: 01235 863656 Fax: 01235 863648 sanjay.maniku@celoxica.com http://www.celoxica.com No. 3209209 This email and any files transmitted with it are confidential and may be legally privileged. It is intended solely for the use of the individual or entity to whom it is addressed. If you have received this in error, please contact the sender and delete the material immediately. Whilst this email has been swept for viruses, you should carry out your own virus check before opening any attachment. Celoxica Ltd accepts no liability for any loss or damage which may be caused by software viruses or interception or interruption of this email. _____________________________________________________________________ This message has been checked for all known viruses by Star Internet delivered through the MessageLabs Virus Scanning Service. This email and any files transmitted with it are confidential and may be legally privileged. It is intended solely for the use of the individual or entity to whom it is addressed. If you have received this in error, please contact the sender and delete the material immediately. Whilst this email has been swept for viruses, you should carry out your own virus check before opening any attachment. Celoxica Ltd accepts no liability for any loss or damage which may be caused by software viruses or interception or interruption of this email. -- Posted from mail17.messagelabs.com [62.231.131.67] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 34356
"Mark" <m.smulders@philips.com> wrote in message news:<3b827206$0$14114$4d4ebb8e@read-nat.news.nl.uu.net>... > Alrite! > thanks for answering my question :-)) > > At this point I'm going to use a board from Celoxica (has a Xilinx FPGA) > pretty nice.. programming it in Handel-C... > > peace, > - Mark > Surely this is an expensive route to take. Verilog or VHDL would be better than Handel-C and more portable. Also use a cheaper board - I've heard the Celoxica gear costs a lot. LArticle: 34358
Dave, I have had problems too. I am using the Xilinx version of Modelsim. The problem is with the Flexlm software recognizing the Ethernet card MAC under windows 2000. There are several programs associated with the licensing software. lmutil, lmtools, lmgrd and lmgrdxxx.dll where xxx can be 326b for instance. Also, every vendor who uses this software protection scheme will provide these utilities with there distribution. So you end up with a half a dozen copies of these utilities all over your system. The real problem is getting someone to admit it is their problem. Frankly IMO it is a Flexlm problem. However, they will not give support to end users, so trying to contact them is sort of useless. I suspect the problem lies in the lmgr326b.dll. Here is what I did to solve it for myself. I got real desperate and "rename" the lmgr326b.dll..... It worked! Although this worked for me, in general it will not work. And I would not suggest you try it unless you are really desperate. I am not sure what the Flexlm software does, and like I said, they will not support end users. Oh, they allow you to ask one question, so make it a good one. Their (www.globetrotter.com) FAQ and end user stuff gives some common solutions to this problem. However, they do not say anything about the dll in their FAQ concerning this problem. Maybe you can convince someone at Model tech to resolve this problem. Hope this helps a little Dave Colson Dave Feustel wrote: > Modelsim licensing refuses to work on my computer. > > What alternatives to Modelsim are there for Verilog simulation > on Windows 2000? > > Thanks.Article: 34360
James Lee wrote: > > I reviewed the book. It was quite interesting, I did not fully > understand it untill I spoke with the authors. The focus is on > picking a set of tools and libraries that work consistently with a > style of verilog. > That sounds bad for the state of hardware development. Bugs in my code/schematics I can correct, yet with the fact that the final output of logic synthesizers is totally hidden from the public how do I know if there are no bugs in the system. Ben. - Standard Disclaimer : 97% speculation 2% bad grammar 1% facts. "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics.Article: 34361
gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote in message news:<9luh55$jak@gap.cco.caltech.edu>... > bryan@srccomp.com (Bryan) writes: > > >> The path through CLBs and routing to make an oscillator like that > >> shown should be long enough to keep the frequency relatively low, > >> compared to discrete logic. > >> > >> -- glen > > >The LUT oscillator that I created had 25% of the chip running at > >.45ns(lut) + .5ns(route) or ~ 512Mhz and 75% of the chip running at > >.45ns + .9ns or > >~ 740Mhz. That is a Virtex-II 1000 speed 4. This of course is by > >the book delays, which we have found actual routes to be 80% of the > >delay > > What is the maximum clock speed for Virtex-II, FF, through one LUT, > to another FF? Can Virtex-II run a design where most of the logic > runs at that clock speed? > > -- glen I didn't say anything about using FFs. This is a design using nothing but LUTs. This design is not clocking latches. It is simpling toggling LUTs as fast as they will toggle. BryanArticle: 34362
yes... I need DATA cuz, i have to serailly output data_word[21..0]( just a DFFE) out thru DATA (output pin & DFFE) and i really don't wanna put lb_word[] = data_word[] .... i only did that cuz DATA = data_word[i] was not working properly...otherwise i would have made lb_word[i] = LB where LB = DATA ( they are interconected on the synth chip) So, how serial output work ..... is there some rule to follow for it?? Abhimanyu Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:3B831807.1A01DE25@iprimus.com.au... > IIRC, this should work: > > lb_word[]=data_word[] > > Do you really need DATA ? > > Abhimanyu Rastogi wrote: > > > > hello, > > > > How does a for loop executes the statements in AHDL .... > > > > for instance...: > > > > FOR i IN 0 to 21 GENERATE > > DATA.d = data_word[i]; > > lb_word[i] = data_word[i]; --assuming DATA is connected to LB > > END GENERATE; > > > > where... we have data_word[21..0] DFFE; lb_word[21..0] DFFE and DATA DFFE; > > > > so now on simulation lets say i provide data_word[] = (H"38CCAA") then wat > > should be the result in DATA n lb_word[] > > > > Also, does it have sequentially or concurrently..?? > > > > Thx > > > > Abhimanyu rastogi > > -- > ___ ___ > / /\ / /\ > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > /__/ / Victoria, Australia, Down-Under /__/\/\/ > \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ > \__\/ \__\/Article: 34363
John, Make, model number, and where to buy the IR temp sensor? I get sooo many questions, and it would be worth its weight in gold to publicize this info! Austin John Larkin wrote: > On Mon, 20 Aug 2001 19:10:26 +0100, Rick Filipkiewicz > <rick@algor.co.uk> wrote: > > >Peter, > > > >On top of all the other useful stuff you contribute to CAF you have just answered a > >long-standing (or burning ?) question of mine regarding the calibration of heat > >sensing fingertips. > > Peter, > > my right forefinger is calibrated as follows: > > 50C - ok for infinite duration contact > > 52C - 10 seconds to pullaway > > 60C - 1 second to pullaway > > Interpolate linearly between points. Your digits may vary. > > We just got a cheap ($79) infrared temp sensor, which is cool (no pun, > really) for scanning FPGAs on a board. > > John > > > > >To go further and get another data point: Last summer I was wondering why our new > >board wasn't doing anything from power-on. I, very briefly, put my finger on it & > >came away with a large & painful blister that was still very sore 2 days later. > > > >Cause = BGA chip pinout mirrored (not by me I hasten to add). > > > >What temp do you think the package would have reached ?Article: 34365
The FOR GENERATE does't do anything for you serially. All you're doing is implementing 22 different statements by using one FOR GENERATE block rather than typing 22 different equations by hand (or doing one simple assign in this case). If you need serial output you need to think in terms of registers and how those registers - all clocked at once - can give you your output. Abhimanyu Rastogi wrote: > yes... I need DATA > cuz, i have to serailly output data_word[21..0]( just a DFFE) out thru DATA > (output pin & DFFE) > and i really don't wanna put lb_word[] = data_word[] .... i only did that > cuz DATA = data_word[i] was not working properly...otherwise i would have > made lb_word[i] = LB where LB = DATA ( they are interconected on the synth > chip) > > So, how serial output work ..... is there some rule to follow for it?? > > Abhimanyu > > Russell Shaw <rjshaw@iprimus.com.au> wrote in message > news:3B831807.1A01DE25@iprimus.com.au... > > IIRC, this should work: > > > > lb_word[]=data_word[] > > > > Do you really need DATA ? > > > > Abhimanyu Rastogi wrote: > > > > > > hello, > > > > > > How does a for loop executes the statements in AHDL .... > > > > > > for instance...: > > > > > > FOR i IN 0 to 21 GENERATE > > > DATA.d = data_word[i]; > > > lb_word[i] = data_word[i]; --assuming DATA is connected to LB > > > END GENERATE; > > > > > > where... we have data_word[21..0] DFFE; lb_word[21..0] DFFE and DATA > DFFE; > > > > > > so now on simulation lets say i provide data_word[] = (H"38CCAA") then > wat > > > should be the result in DATA n lb_word[] > > > > > > Also, does it have sequentially or concurrently..?? > > > > > > Thx > > > > > > Abhimanyu rastogi > > > > -- > > ___ ___ > > / /\ / /\ > > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > > /__/ / Victoria, Australia, Down-Under /__/\/\/ > > \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ > > \__\/ \__\/Article: 34366
Rick Filipkiewicz schrieb: > > them [6/5 states resp.]. Only these core machines + the outgoing data pipe > control should use the raw, unregistered, PCI signals as inputs. Arnt all inputs defined as registered in the definition of PCI?? -- MFG FalkArticle: 34367
Mark wrote: > > Hi there! > > I'm pretty new at FPGAs, and what I'm trying to do is > program an MP3 decoder into an FPGA.. > Does anyone have experience at this? > Are there VHDL or Handel-C mp3 decoder sources around? > Or anyone wants to discuss this subject with me? :-)) Seems to me that you're better off implementing the decoder in a DSP. -aArticle: 34368
> case). If you need serial output you need to think in terms of registers and > how those registers - all clocked at once - can give you your output. > But how do i do this...... could u give an example of serially outputting data..... ?? John_H <johnhandwork@mail.com> wrote in message news:3B83DFA4.1D9A3AD3@mail.com... > The FOR GENERATE does't do anything for you serially. All you're doing is > implementing 22 different statements by using one FOR GENERATE block rather > than typing 22 different equations by hand (or doing one simple assign in this > case). If you need serial output you need to think in terms of registers and > how those registers - all clocked at once - can give you your output. > > > Abhimanyu Rastogi wrote: > > > yes... I need DATA > > cuz, i have to serailly output data_word[21..0]( just a DFFE) out thru DATA > > (output pin & DFFE) > > and i really don't wanna put lb_word[] = data_word[] .... i only did that > > cuz DATA = data_word[i] was not working properly...otherwise i would have > > made lb_word[i] = LB where LB = DATA ( they are interconected on the synth > > chip) > > > > So, how serial output work ..... is there some rule to follow for it?? > > > > Abhimanyu > > > > Russell Shaw <rjshaw@iprimus.com.au> wrote in message > > news:3B831807.1A01DE25@iprimus.com.au... > > > IIRC, this should work: > > > > > > lb_word[]=data_word[] > > > > > > Do you really need DATA ? > > > > > > Abhimanyu Rastogi wrote: > > > > > > > > hello, > > > > > > > > How does a for loop executes the statements in AHDL .... > > > > > > > > for instance...: > > > > > > > > FOR i IN 0 to 21 GENERATE > > > > DATA.d = data_word[i]; > > > > lb_word[i] = data_word[i]; --assuming DATA is connected to LB > > > > END GENERATE; > > > > > > > > where... we have data_word[21..0] DFFE; lb_word[21..0] DFFE and DATA > > DFFE; > > > > > > > > so now on simulation lets say i provide data_word[] = (H"38CCAA") then > > wat > > > > should be the result in DATA n lb_word[] > > > > > > > > Also, does it have sequentially or concurrently..?? > > > > > > > > Thx > > > > > > > > Abhimanyu rastogi > > > > > > -- > > > ___ ___ > > > / /\ / /\ > > > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > > > /__/ / Victoria, Australia, Down-Under /__/\/\/ > > > \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ > > > \__\/ \__\/ >Article: 34369
"Philip Freidin" <philip@fliptronics.com> wrote in message news:chu5otc4n394qaklkj21e0kisubphc5ng4@4ax.com... > On 21 Aug 2001 20:43:17 GMT, gah@ugcs.caltech.edu wrote: > >What is the maximum clock speed for Virtex-II, FF, through one LUT, > >to another FF? > > In a V-II , -5 speed grade, M3.3.08i speed files, with careful placement, > about 666MHz . > So, again with careful design, one could have a design with about half the gates and FF changing state at 666MHz, or about 333MHz each. (That is, assuming random data bits.) About a factor of two from what was claimed for the oscillation modes. -- glenArticle: 34370
"Tim" <tim@rockylogic.com.nospam.com> wrote: > >"Michael Boehnel" <boehnel@iti.tu-graz.ac.at> wrote in message >news:3B835877.71635D2A@iti.tu-graz.ac.at... >> Are there any significant differences between a logic emulated version >> (implemented in an FPGA) and an ASIC version. >> >> I could imagine that at least some timing differences should occure. Are >> these timing differences important? > > Raw speed is usually higher in ASIC, at a given process level. > >> Are there any other differences? > > ASICs are a generation or more ahead in density, if you can afford it > No tri-states in ASICs (going away in FPGAs) I am not sure what you mean by "No tri-states in ASICs". I guess it is possible that one is discouraged to use tri-states in a standard cell or gate array targeted design but I have yet to see a cell library which doesn't have any internal tri-state buffers or inverters. Especially with a standard cell methodology, you can do what ever you want, including designing your own cells.Article: 34371
"Muzaffer Kal" <muzaffer@dspia.com> wrote in message news:hgv7ot4plbq621l8au8n2am8lpe4grmtm7@4ax.com... > "Tim" <tim@rockylogic.com.nospam.com> wrote: > <snip> > > No tri-states in ASICs (going away in FPGAs) > > I am not sure what you mean by "No tri-states in ASICs". I guess it is > possible that one is discouraged to use tri-states in a standard cell > or gate array targeted design but I have yet to see a cell library > which doesn't have any internal tri-state buffers or inverters. > Especially with a standard cell methodology, you can do what ever you > want, including designing your own cells. Well, you have caught me out on this one. But I have worked with several teams who have claimed that their ASIC libraries supported muxes, obviously, but not internal t/s buses. Perhaps an ASIC specialist can report on the incidence of t/s buffers in mainline libraries from the big players. How about SA21 for starters?Article: 34372
In article <fe76d03b.0108210659.668efa4f@posting.google.com>, joey@sun.science.wayne.edu says... > Rick Filipkiewicz <rick@algor.co.uk> wrote in message news:<3B820B62.54174F87@algor.co.uk>... > > I'm with Austin on this. It *is* possible to get a Virtex-E to meet 33MHz PCI > > timing. I was in a similar position ~2.5 years ago when (1) I had to proto a PCI > > i/f destined, ultimately, for an ASIC and (2) a bought in IP solution was not > > acceptable to the client. > > Yes, I totally agree it could be done, but what I tried to mention in > my previous post is that the PCI core itself is not the problem at > all. The problem is the "rest of the chip". Its very common for people to emulate ASIC designs in FPGAs and its very common that they can only be run at a fraction of the clock speed that the ASIC runs at. To all the people advocating that he use an off the shelf PCI interface in the FPGA or giving advice on how to better code the state machines for the FPGA, while being good advice for a "from scratch" PCI design in an FPGA, I think you're missing the point. He has to keep the FPGA RTL the same as the ASIC RTL or else he is not verifying the ASIC design, which is the goal. -- Rich Iachetta iachetta@us.ibm.com I do not speak for IBM.Article: 34373
hamish@cloud.net.au wrote in message news:<ZvNg7.21651$A5.65678@news1.eburwd1.vic.optushome.com.au>... > Do you see much advantage with Amplify? Do you see it doing anything > which you couldn't do yourself with Synplify Pro and the Xilinx floorplanner? > > I have access to an Amplify license at work and in my brief experience > with it, it just seems to be a way to enter your floorplan and have > it appear in an NCF. So I just enter it into the UCF myself, with > floorplanner or by hand. > > I'd like to be proven wrong though. What does the tool itself actually > do with the floorplanning information? What optimisations can > it make at synthesis time given the floorplan? Well, amplify feels superior to synplify pro in synthesis. It's kind of comparing apples to oranges between versions of the software because I used synpro 7.0b2 and amplify 2.2.4. For me, Amplify's timing report was far more conservative which was great. Some designs failed by just a 4-5 ns during PAR (level2) with SynPro that succeeded under the same conditions with Amplify. Could have just been dumb-luck, but synthesis time I had those more accurate timing predictions with Amplify. As for floorplanning effect on synthesis, I have no idea offhand. You make a good point that everything could probably be done by hand or with the floorplanner tool. This tool's strength lies more in its ease of use. In about an hour using the Amplify floorplanner with little knowledge of the RTL, I lowered cycle time from 47ns to 37ns post-PAR meeting the 25mhz constraint with under an hours work. The paths were 25% logic 75% route. There's not a lot of choice for improving a design besides modifying the RTL code and improving placement/routing. Since modifying the RTL is a non-option in an ASIC prototype, Amplify was really the only route for improvement. I was very skeptical of the tool, especially because the thought of rearranging a million gates on a large Virtex is absurd. However it really was pretty easy working with the RTL structures instead of gates. My design had a lot of block repetition and wide structures, so that really helps. Your mileage may vary. -joeyArticle: 34374
In article <jWSg7.5538$o6.109727@news>, Abhimanyu Rastogi <abhi_rastogi@hotmail.com> writes >> case). If you need serial output you need to think in terms of registers >and >> how those registers - all clocked at once - can give you your output. >> > >But how do i do this...... could u give an example of serially outputting >data..... ?? > > within MAXPLUS (possibly quartus too) look for help on LPM_SHIFTREG . You will find the information you require there. -- Steve
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