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You'll need to use a layout program with an output format that is acceptable to the shop doing the board fab. Pads is one that seems to be fairly common. You'll wind up spending more for the software than you would have for contracting the board layout out to one of the design houses. The layout cost is roughly proportional to the number of pins. A few years ago, I was paying about $1 per pin for layout. I suspect this has gone up some in the mean time, and the price will vary from shop to shop. Steven Derrien wrote: > "Andy Peters > > > > david garnett wrote: > > > > > > The BurchED Spartan board is only two layer, > > > > That's good to know. > > > > If it were me, I'd do at least four layers - top and bottom for signal, > > middle two for VCC and GND. > > BTW, just to get an idea, let's say I m an inexperienced PCB designer > and > that I want to have my own PCB board for a specific app. (let's say a 4 > layers board with a SPII-pq208, SRAM, and and ethernet controller + > transceiver) i'd need around 100 sample of them (so it's very low > volume) > > 1) I could can ask for PCB designer services, to design the layout and > handle the production but then it's likely to be expensive (price range > ?) > > 2) I can do the layout on my own using for ex Orcad, since i am > inexperienced > do I have a chance to succeed (I mean to get a working board) and if so > how > long will it take ? and in such a case how much it would cost ? > > Thanks, > > steven > > app an > > > > -andy -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33751
In the case we had, the output of the driving flip flop was going to the direct in of a flip-flop in the other slice in the same CLB without passing through a LUT and without using the routing. IIRC the route delay for that fast route is a max of 0.17ns in a -4 part. The Tcko and Tsu/Th values are based on worst case, so a typical chip is going to go much faster. We toggled the output flip flops in adjacent IOBs by the two clocks. This gives you the shortest connection between the clock net and the pad. By using adjacent IOBs, we assumed similar Tcko for both flip-flops. There is no routing variability introduced because the output flop to pad is a dedicated route (through a tristate buffer). We did this in several locations around the chip. Falk wrote: > How can 500ps of clock skew cause this kind of trouble? The clock to out time plus some routing should always be greater than this? How did you measure the skew (skew matching of IO cells, equal routing to IO cells) > > Regards > Falk -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33752
"Jaime Andres Aranguren Cardona" <jaime.aranguren@ieee.org> wrote > So, would some of you, please, help me with some starting points, as > links, textbooks, vhdl code, etc...? Visit www.fpgacpu.org, particularly .../links.html. Though it exceeds both your requirements and your device resources, you may find instructive my Circuit Cellar magazine series, "Building a RISC System in an FPGA". It explores the design of a pipelined 16-bit RISC plus peripherals and video display in an XC4005XL (e.g. equivalent to an XCS10, about twice as many LUTs as your XCS05). Also, the last two chapters of David Vanden Bout's excellent "Practical Xilinx Designer Lab Book" (which accompanies Xilinx Student Ed. 1.5 and 2.1i, so your instructor may already have a copy) presents the design of two simple (4-bit and 8-bit) MCUs. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 33753
> Martin Schoeberl wrote:
> >
> > A never ending problem! Trying to get RAMs in my design so that there is
> > not to much vendor specific code.
> > For Altera I'm using Leonardo and Max+plus, for Xilinx WebPack.
> >
> > I need a RAM with rgistered rd and wr address and unregistered data (in/out)
> > ports.
> > One version works:
> > Generate a .tdf file with Altera wizard and declare the component in the
> > VHDL
> > code. But now I have .tdf files. I want only VHDL.
> >
Sorry, missed the original message...
MaxPlus2 can recognize 'magic names'. To implement any of the LPM memories
in EABs, just instantiate the right component. In your case (assuming 256x8 bits):
entity syn_ram_256x8_irou is
port ( Data : in std_logic_vector(7 downto 0);
Address : in std_logic_vector(7 downto 0);
WE : in std_logic;
Q : out std_logic_vector(7 downto 0);
Inclock : in std_logic
);
Copy this name & portmap into your design. Leonardo will complain
and generate EDF with a empty 'black box'. MaxPlus2 spots this and
fills the gap with the right thing (TM).
I guess you want to know how this magic works... Here we go:
If you dig deep enough into your MaxPlus2 installation, you'll find
a little DOS program called genmem.exe. This program generates a
VHDL (or Verilog) component with the right name. The component itself
is a handy simulation model for the memory, but make sure you don't
try to synthesize it.
Have a nice day,
Iwo
Article: 33754Iwo Mergler wrote: > > > Martin Schoeberl wrote: > > > > > > A never ending problem! Trying to get RAMs in my design so that there is > > > not to much vendor specific code. > > > For Altera I'm using Leonardo and Max+plus, for Xilinx WebPack. > > > > > > I need a RAM with rgistered rd and wr address and unregistered data (in/out) > > > ports. > > > One version works: > > > Generate a .tdf file with Altera wizard and declare the component in the > > > VHDL > > > code. But now I have .tdf files. I want only VHDL. > > > > > Sorry, missed the original message... > > MaxPlus2 can recognize 'magic names'. To implement any of the LPM memories > in EABs, just instantiate the right component. In your case (assuming 256x8 bits): > > entity syn_ram_256x8_irou is > port ( Data : in std_logic_vector(7 downto 0); > Address : in std_logic_vector(7 downto 0); > WE : in std_logic; > Q : out std_logic_vector(7 downto 0); > Inclock : in std_logic > ); > > Copy this name & portmap into your design. Leonardo will complain > and generate EDF with a empty 'black box'. MaxPlus2 spots this and > fills the gap with the right thing (TM). > > I guess you want to know how this magic works... Here we go: > > If you dig deep enough into your MaxPlus2 installation, you'll find > a little DOS program called genmem.exe. This program generates a > VHDL (or Verilog) component with the right name. The component itself > is a handy simulation model for the memory, but make sure you don't > try to synthesize it. Another way i found is to run the "mega wizard plug-in manager" in maxplus2. It will generate a vhdl file with the architecture and entity declaration, and another file with an instance of the component you want. Just copy that instance into your own design, and add your signal connections. -- ___ ___ / /\ / /\ / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ /__/ / Victoria, Australia, Down-Under /__/\/\/ \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ \__\/ \__\/Article: 33755
Ray Andraka wrote: > > You'll need to use a layout program with an output format that is acceptable > to the shop doing the board fab. Pads is one that seems to be fairly > common. You'll wind up spending more for the software than you would have > for contracting the board layout out to one of the design houses. What do they take as input data : board level schematic I guess, do they also handle all additionnal stuff like adding all the decoupling capacitors and line termination when required or is it the customer ? > The layout cost is roughly proportional to the number of pins. A few years ago, I was > paying about $1 per pin for layout. I suspect this has gone up some in the > mean time, and the price will vary from shop to shop. Do you mean $1 per pin for the layout design (seems pretty cheap to me) ? Wait a minute let's say I have may SPII with 128kx16 plus 100 pin this makes less than 1000$ which remains very affordable. (Am i wrong ?) Thanks again, Steven > > Steven Derrien wrote: > > > "Andy Peters > > > > > > david garnett wrote: > > > > > > > > The BurchED Spartan board is only two layer, > > > > > > That's good to know. > > > > > > If it were me, I'd do at least four layers - top and bottom for signal, > > > middle two for VCC and GND. > > > > BTW, just to get an idea, let's say I m an inexperienced PCB designer > > and > > that I want to have my own PCB board for a specific app. (let's say a 4 > > layers board with a SPII-pq208, SRAM, and and ethernet controller + > > transceiver) i'd need around 100 sample of them (so it's very low > > volume) > > > > 1) I could can ask for PCB designer services, to design the layout and > > handle the production but then it's likely to be expensive (price range > > ?) > > > > 2) I can do the layout on my own using for ex Orcad, since i am > > inexperienced > > do I have a chance to succeed (I mean to get a working board) and if so > > how > > long will it take ? and in such a case how much it would cost ? > > > > Thanks, > > > > steven > > > > app an > > > > > > -andy > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.comArticle: 33756
I have now found more bugs in the licensing program for Modelsim and as a result I have discontinued efforts to get the software licensing program to complete successfully. "ron" <ronhui@ctimail3.com> wrote in message news:1e8636c.0108021931.5bbe9126@posting.google.com... > I have painful experience when obtaining license from ModelSim and > Xilinx ISE Foundation, espeically Xilinx. > > It is difficult to imagine we pay so much for the software in exchange > for such poor service > > Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3B69B802.B5C06920@flukenetworks.com>... > > Dave Feustel wrote: > > > > > > > Does the Flexlm licensing and license validation procedure actually > > > *work* on Windows 2000? > > > > I can testify that validation works on win2k. > > My license server is elsewhere on the network. > > I assume you have set a path for > > LM_LICENSE_FILE or MGLS_LICENSE_FILE > > > > (Start, Settings, ControlPanel, > > System, Advanced, Environment . . .) > > > > > > --Mike TreselerArticle: 33757
Synplify-Pro has a simple "probe" feature for bringing internal signals to pins with no RTL mods. For more sophisticated debug insertion there is a Certify-SC option to Synplify-Pro. The non-Pro version of Synplify has no way to do this. Brian Dickinson wrote: > > "Rick Collins" <spamgoeshere4@yahoo.com> wrote in message > news:3B67A4B4.29694DFF@yahoo.com... > > I am adding some code to a verilog design for debug and I need to access > > signals in a remote portion of the design. I have been told that there > > is a way to do this in the form of > > "top_level.mid_level.low_level.signal_name" where the level names are > > module instance names. This works ok in simulation, but I can't get it > > to work in synthesis. We are using Synplify. Is this not supported by > > this tool? Is this not supported by any synthesis tool? > > Don't know of a synthesis tool which supports this... > If you want to access the signal in hardware, you need to make an > explicit > connection through the module ports. > If the signal access is just for debug, then you can hide the code from > the synthesis tool by using synthesis directives (comments which control > synthesis) e.g. enclose the remote signal access with the following > comments > > /* synthesis translate_off */ > <unsynthesisable debug code> > /* synthesis translate_on */ > > B > > > HDL, FPGA, PCB, Perl and Tcl training from Esperan > The World's Leading Methodology Training Company for > Electronic > Design > http://www.esperan.com -- Ken McElvain, CTO Synplicity Inc. (408)215-6060Article: 33758
I'd really try to find a bit larger of an FPGA. It would be really nice to
have something in a Virtex architecture, like a small Spartan-II, because
you could put the code in an internal blockRAM and then not have to worry
about external RAM. It would be self-contained except for any I/Os.
Xilinx has developed such a controller and it's available for free on their
website; you could look at it for ideas. I think it's called KPSCM or
something.
"Jaime Andres Aranguren Cardona" <jaime.aranguren@ieee.org> wrote in message
news:14a86f87.0108022041.445b1c13@posting.google.com...
> Hi, gurus:
>
> For a school project, I should implement within the next three months
> a basic, but prefereably not very basic, CPU = microprocessor on a
> PLCC84 cased Xilinx Spartan XCS05-3 running @ 10MHz, or even faster.
>
> The design should meet, or exceed, the following requeriments:
> - Speed
> - Make it fit on the FPGA
> - Should write our own compiler ("our" assembler -> bitsteram)
> - Instructions: 8 bits long
> - Data: 4 bits long
>
> So, would some of you, please, help me with some starting points, as
> links, textbooks, vhdl code, etc...?
>
> I am sure most of you, guys, could give good advice on the subject.
>
> Please reply to jaime.aranguren@ieee.org
>
> Thanks a lot, in advance
>
Article: 33759This is exactly what I don't understand about the divided outputs on the DLL. They aren't fed back to the feedback, so they aren't synchronous to the input, so what good are they? There's no way for the DLL to know the delay across the BUFG unless it is fed back, and you can only do that with 1X or 2X outputs. The best thing for you to do is probably use the same clock and clock-enable the slow logic every fourth cycle. Then you have to constrain all that circuitry as 4-cycle multicycle paths. Since the clock enable is then the critical path (since it's not a multicycle path) you may have to use a directive (like syn_direct_enable in Synplify) to ensure that the clock enable gets directly connect to the CE on the flops. "Cary McCormick" <jcmccorm@hiwaay.net> wrote in message news:qLja7.10341$C7.5227435@e3500-chi1.usenetserver.com... > > Hi folks, > I'm using a DLL in a SpartanII design and have discovered with lab > experimentation that lo and behold, the /4 output lags the edge of the x1 > output by about 1ns. I'm certain that I'm using the DLL correctly (BUFGs on > both outputs, feedback comes from BUFG'd x1 output) and I imagine that the > phase difference is due entirely to loading differences since the /4 clock > is *much* more heavily loaded than the x1 clock. > So, given that we're kind of stuck with this (what's the point of BUFG's > anyway if this happens?) how can I design with this? Will the Design Manager > (using 3.1) check for setup problems? Any design tricks that the gurus can > share on this matter?? Safety precautions I can add to the UCF file?? > Thanks!! > > Cary McCormick > > > > >Article: 33760
Kevin Neilson wrote:
>
> I'd really try to find a bit larger of an FPGA. It would be really nice to
> have something in a Virtex architecture, like a small Spartan-II, because
> you could put the code in an internal blockRAM and then not have to worry
> about external RAM. It would be self-contained except for any I/Os.
>
> Xilinx has developed such a controller and it's available for free on their
> website; you could look at it for ideas. I think it's called KPSCM or
> something.
>
Its the KCPSM, which stands for constant (K) Coded Programmable State
Machine. The name kind of explains what its suitable for. There's
supports for interrupts, and you can stream data in and out via an
addressed 8 bit port.
http://www.xilinx.com/xapp/xapp213.pdf gives more details
Just rolling back to the original post
> Should write our own compiler ("our" assembler -> bitsteram)
This could be a bit of a stretch. Your assembler producing a
parameterised RAM block is entirely possible (the KCPSM does this for
example) but this isn't the bitstream - you still have to go through
ppr. You could always use Xilinx's JBits to do this though directly on
the bitstream if you could move up to a Virtex device.
Phil
--
---------------------------------------------------------------------
__
/ /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545
\ \ Staff Software Engineer Fax: Unreliable use email :-)
/ / Loki/DARPA Email: phil.james-roxby@xilinx.com
\_\/\ Xilinx Boulder
---------------------------------------------------------------------
Article: 33761stoneman wrote: > But > some address are wrong in read and write the memory. > Does anyone have a tip or idea?? This type of problem is best solved using a simulation testbench. The "load and probe" technique is cheap. It might be effective if you are very good or very lucky. Mere mortals use simulation. --Mike TreselerArticle: 33762
You might want to make sure that the LM_LICENSE_FILE variable is set. 1. You can check this by going to: 2. Start|Run 3.Ttype <cmd> 4. Type <set> This will list all of the environment variables set for your machine The following text can also be save to a .bat file and used to start ModelSim XE. It may need to be modified to match your paths. This should only be used as a test to verify that the LM_LICENSE_FILE enviroment variable isn't being set correctly. REM ----- Start of ModelSim Batch File ------- set PATH=C:\Modeltech_xe\win32xoem;%PATH% set LM_LICENSE_FILE=C:\Modeltech_xe\win32xoem\license.dat cd C:\Modeltech_xe\win32xoem modelsim.exe REM ----- End of ModelSim Batch File ------- Later, Chris Russell Shaw wrote: > Go to: > > start|settings|control-panel|system|advanced|environment-variables > > set the LM_LICENSE_FILE to point to c:\flexlm\license.dat > > for user variables and system variables. > > Install IPX/SPX network protocol in windows2k. > > Dave Feustel wrote: > > > > I am having *zero* success getting the Flexlm licensing process > > for Modelsim to work on my Windows 2000 Pro SP1 Dell > > system. This in spite of generous help from Model Technology. > > The first attempt to access Modelsim after each install results in a > > flexlm error message (latest is 'can't find license file') and an > > invalidated license. > > > > This happens both with Webpack Modelsim and also the > > full version of Modelsim on CDROM delivered directly from Model. > > > > To say that attempting to use Modelsim under these conditions > > is getting old fast would be a serious understatement. > > > > Does the Flexlm licensing and license validation procedure actually > > *work* on Windows 2000? > > -- > ___ ___ > / /\ / /\ > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > /__/ / Victoria, Australia, Down-Under /__/\/\/ > \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ > \__\/ \__\/Article: 33763
Jaime Andres Aranguren Cardona wrote:
>
> Hi, gurus:
>
> For a school project, I should implement within the next three months
> a basic, but prefereably not very basic, CPU = microprocessor on a
> PLCC84 cased Xilinx Spartan XCS05-3 running @ 10MHz, or even faster.
>
> The design should meet, or exceed, the following requeriments:
> - Speed
> - Make it fit on the FPGA
> - Should write our own compiler ("our" assembler -> bitsteram)
> - Instructions: 8 bits long
> - Data: 4 bits long
>
> So, would some of you, please, help me with some starting points, as
> links, textbooks, vhdl code, etc...?
>
> I am sure most of you, guys, could give good advice on the subject.
>
> Please reply to jaime.aranguren@ieee.org
>
> Thanks a lot, in advance
One feature the early 4 bit chips had is that they where
made for calculator work. 4k rom space 256 byte data space?
Alu operations often just ADC,SBC,AND,LOAD,STORE. Testing
for carry or zero only. Addressing often limited to dedicated
pointer registers. Subroutine calls 3-4 levels deep with a
internal stack.
Ben.
--
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.
Article: 33764Hi all. I'm a Xilinx / ISE newbie and have (what I hope) is a simple question. I'm setting up ISE for multiple people working on an FPGA. We're using revision control with each person having a local working copy of the files. The catch is that the project.npl file lists all the files and directories as absolute paths, so it screws up sharing the file. How do I get ISE to save everything in the npl file as relative paths? Thanks, DavidArticle: 33765
The input is generally a text netlist. You'll have to confer with the vendor for the exact format. Most schematic editors have an option of exporting netlists in various formats. At least one of those can be imported by the layout tools. You are responsible for putting your decoupling caps, terminators etc in your design. For decoupling caps, the layout guy can obviously move them around the board, so you also generally have to supply a set of guidelines for the layout. Generally I give them rules for decoupling caps, a mechanical drawing of the board showing size, keep-out areas, height restricted areas, connector and switch locations etc and a board stack up showing the order of layers if it is multi-layer. You probably also have a feel for how things would get situated on the board, so you can give him a "suggested starting point" for the layout. You will also want to give him any manufacturing rules that need to be followed to keep the cost of populating the board down. Depending on the assembly shop, this might be restrictions as to what if anything can go on the back side, orientation of parts, additional keep-out rules, via restrictions, tooling hole requirements etc. You'll be expected to approve a preliminary layout before the board is routed, and to approve the gerber plots before the final artwork is generated. A good layout guy will already know what makes a board more manufacturable and will tell you if you want something that is a PITA. The number of pins means pins on _everything_. Decoupling caps each have 2 pins, each device has a number of pins. Connectors, switches etc all have pins. Still, at the prices I last used it worked out to about $1 a pin. $1000 is probably in the ballpark, although the $1 per pin number is a couple of years old. Steven Derrien wrote: > Ray Andraka wrote: > > > > You'll need to use a layout program with an output format that is acceptable > > to the shop doing the board fab. Pads is one that seems to be fairly > > common. You'll wind up spending more for the software than you would have > > for contracting the board layout out to one of the design houses. > > What do they take as input data : board level schematic I guess, do they > also handle all additionnal stuff like adding all the decoupling > capacitors > and line termination when required or is it the customer ? > > > The layout cost is roughly proportional to the number of pins. A few years ago, I was > > paying about $1 per pin for layout. I suspect this has gone up some in the > > mean time, and the price will vary from shop to shop. > > Do you mean $1 per pin for the layout design (seems pretty cheap to me) > ? > Wait a minute let's say I have may SPII with 128kx16 plus 100 pin this > makes > less than 1000$ which remains very affordable. (Am i wrong ?) > > Thanks again, > > Steven > > > > > Steven Derrien wrote: > > > > > "Andy Peters > > > > > > > > david garnett wrote: > > > > > > > > > > The BurchED Spartan board is only two layer, > > > > > > > > That's good to know. > > > > > > > > If it were me, I'd do at least four layers - top and bottom for signal, > > > > middle two for VCC and GND. > > > > > > BTW, just to get an idea, let's say I m an inexperienced PCB designer > > > and > > > that I want to have my own PCB board for a specific app. (let's say a 4 > > > layers board with a SPII-pq208, SRAM, and and ethernet controller + > > > transceiver) i'd need around 100 sample of them (so it's very low > > > volume) > > > > > > 1) I could can ask for PCB designer services, to design the layout and > > > handle the production but then it's likely to be expensive (price range > > > ?) > > > > > > 2) I can do the layout on my own using for ex Orcad, since i am > > > inexperienced > > > do I have a chance to succeed (I mean to get a working board) and if so > > > how > > > long will it take ? and in such a case how much it would cost ? > > > > > > Thanks, > > > > > > steven > > > > > > app an > > > > > > > > -andy > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33766
Only one output from the DLL can be fed back to its input, so even using the 2x you run into the same thing. The DLL is designed with the individual outputs closely matched so that there is very little skew coming out of them. Likewise, the bufgs that you can reach with a DLL are co-located and closely matched so that with an equal loading the individual clock trees are phase aligned. The problems occur when the loading on the clock networks is heavily skewed. We also found that jitter on the DLL clock input seems to cause the phase alignment of the individual outputs to move, probably more so than the clock network loading. The problem with using the clock enable as described below is that you can't put that on a clock network, and the "low skew" global networks are too slow if your clocking at even half of what the part is capable of. In this particular case, he said most of the chip is being clocked by the 1/4 clock, in which case you would need to distribute a fast CE over the whole chip. You also unnecessarily congest the routing and increase power. Using two clocks is a good solution, just be careful when crossing the boundaries of the clock domains. Kevin Neilson wrote: > This is exactly what I don't understand about the divided outputs on the > DLL. They aren't fed back to the feedback, so they aren't synchronous to > the input, so what good are they? There's no way for the DLL to know the > delay across the BUFG unless it is fed back, and you can only do that with > 1X or 2X outputs. > > The best thing for you to do is probably use the same clock and clock-enable > the slow logic every fourth cycle. Then you have to constrain all that > circuitry as 4-cycle multicycle paths. Since the clock enable is then the > critical path (since it's not a multicycle path) you may have to use a > directive (like syn_direct_enable in Synplify) to ensure that the clock > enable gets directly connect to the CE on the flops. > > "Cary McCormick" <jcmccorm@hiwaay.net> wrote in message > news:qLja7.10341$C7.5227435@e3500-chi1.usenetserver.com... > > > > Hi folks, > > I'm using a DLL in a SpartanII design and have discovered with lab > > experimentation that lo and behold, the /4 output lags the edge of the x1 > > output by about 1ns. I'm certain that I'm using the DLL correctly (BUFGs > on > > both outputs, feedback comes from BUFG'd x1 output) and I imagine that the > > phase difference is due entirely to loading differences since the /4 clock > > is *much* more heavily loaded than the x1 clock. > > So, given that we're kind of stuck with this (what's the point of > BUFG's > > anyway if this happens?) how can I design with this? Will the Design > Manager > > (using 3.1) check for setup problems? Any design tricks that the gurus can > > share on this matter?? Safety precautions I can add to the UCF file?? > > Thanks!! > > > > Cary McCormick > > > > > > > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33767
Phil Hays <spampostmaster@home.com> writes: > Kamal Patel wrote: > > > > That is correct Robert. The ISE GUI ... > > I hope that batch files still will work. I hope so too (I assume you mean all the individual command line tools). The only GUI program I use is floorplanner. However, I would love to see the tools available under Linux rather than a GUI with a talking chip (cousin of the MS paper-clip)... Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 33768
Hello David, Go to Edit => Preferences to bring up the Preferences dialog box. Under the General tab, you can select the Default Path Type for New Sources as Relative Paths. Best regards, Kamal Patel David Rogoff wrote: > Hi all. > > I'm a Xilinx / ISE newbie and have (what I hope) is a simple question. > I'm setting up ISE for multiple people working on an FPGA. We're using > revision control with each person having a local working copy of the > files. The catch is that the project.npl file lists all the files and > directories as absolute paths, so it screws up sharing the file. How > do I get ISE to save everything in the npl file as relative paths? > > Thanks, > > DavidArticle: 33769
Jaime Andres Aranguren Cardona wrote:
> - Should write our own compiler ("our" assembler -> bitsteram)
Your assembler won't be able to write out a Xilinx bitstream. Why not
do what the single-chip micros do, and have a program EPROM (or EEPROM,
or whatever)? The "program" should exist independent of the FPGA
implementation of the processor. Just make sure your CPU accesses the
EPROM when reset. :)
The neat thing about rolling the CPU into an FPGA is that your "CPU" can
have external-device chip selects that do exactly what you want them to,
and as many as you want (within reason, of course). And you can tailor
external bus cycles to whatever hardware you're talking to: slow EPROM,
fast SRAM, whatever.
-andy
Article: 33770Gentlemen, I'm looking for full-time Verilog engineer with FPGA and networking layers 1/2/3 experience to join our team. VHDL/AHDL is a plus. We are medium-sized high-tech company located in Boston, MA. We developing test and measurement equipment. You can visit us at http://www.ueidaq.com If you are interested please contact me at alex_at_ueidaq.com (replace _at_ with @) -- Regards, AlexArticle: 33771
I'm considering one of the smaller CoolRunner CPLDs to replace glue logic and a bidirectional buffer in a low-power data logger design. Can I easily implement the equivalent of a 74LPT245 in this device? I looked in the free schematic tool, and the '245 was not one of the TTL chips available for inclusion. Is this because the chip cannot easily emulate the part? Or do I simply have to build it from back-to-back sets of tri-state buffers with an invert on one set of output enables? Secondary question: Now that I've got data sheets and software, where do I find development hardware and/or a programmer? Eventually, I'll set up for in-system programmming, so a JTAG programmer that can be plugged onto my boards would be handy. Mark BorgersonArticle: 33772
Gonzalo Arana <garana@arnet.com.ar> wrote in message news:<3B56F320.6947DC50@arnet.com.ar>...
> Hi,
>
> I tried to make my own uart model. I wanted something much easier to
> use than a 16550, more flexible (5, 6, 7 or 8 data bits; 1, 2 stop bits,
> any baudrate, etc.), and of course, designed to be built into an FPGA.
>
> Well, I wrote it, simulated it and (apparently) works great. When I run
> it ('looping' RX with TX), I have theese strange problems:
>
> 1) When I send from a PC to the FPGA a sequence of characters
> (ie: echo aaa >/dev/cua0), I read (cat /dev/cua0): aXXa.
> In hexa: I send: 61 61 61 0a
> I get: 61 58 58 e1
>
> 2) That kind of problem is noted when I send to the FPGA bytes whoose
> LSB is 1. I tried sending one million of ascii characters, all of them
> with LSB = 0, and I got NO errors.
>
> 3) I get none of theese errors when I simulate the entire entity.
>
> I know the problem is on the receiver (uartrx.vhd), because I did sent
> from the FPGA (uarttx.vhd)
> a sequence of 'a' (in ascii) and it worked just as it should be.
>
> Could someone please help me?
> Any suggestions on the coding style would be welcome.
> If I get this work right, I will give away this set of files for free (I
> believe to opencores.org).
>
> Thank you very much in advance,
>
> Gonzalo Arana
> --
The biggest single thing you can do for reusability and success of
with these types of designs is use a single high frequency clock to
clock the whole design. Don't be tempted to generate a bit rate clock
and use that to clock flip flops. The way to do it is to generate a
bit rate ENABLE. Its okay to require a 16 or higher ratio of system
clock to bit rate. Following this concept will allow simplicity of
implimention (single clock) and wide usage (arbitrary clock).
Jay
Article: 33773Oh, so it's unloaded. And remember that it's not frequency that matters for signal integrity, it's the edge rate. I would bet that it IS a reflection, and you can't see it. You should load the signals down properly. You may want to use the same sort of circuit that's documented in the data sheets as the test circuit -- usually some specified resistors to VCC and ground, and a cap. --andy "Sune G. Krohn" wrote: > > The load is a track (2.5cm) to a connector with a FET probe (0.7pF||100k > ohm). > We have tested with different frequency, so it is not the reflection. > > "Andy Peters <andy [@] exponentmedia com >" <".> wrote in message > news:FFga7.1224$B.115611@newsread1.prod.itd.earthlink.net... > > "Sune G. Krohn" wrote: > > > > > > I can't get a signal out of Xilinx Virtex-II 2V100 and 2V40 with a > correct > > > duty cycle. > > > > > > I only see this problem in 1.5 and 2.5 voltages mode. > > > > > > I also see the problem on Xilinx Virtex-II Evaluation Kit with a 2V40. > > > > > > As output I use OBUF_LVCMOS15_F_16 for 1.5 V and OBUF_LVCMOS33_F_16. > > > > > > With a frequency about 100MHz is the duty cycle about 35/65. In the test > I > > > run the clock through a FF to make a 50/50 duty cycle and with no luck. > > > > > > It is always the high pulse that a shorter than the low, even if I > invert > > > the signal. > > > > > > We have asked Xilinx's Technical Support Office United Kingdom every day > for > > > two weeks and they can't answer the question they just ask irrelevant > > > questions. For instance, they ask my to do an IBIS simulation on their > > > Evaluation Kit with their chip. > > > > What's the signal's load? That's why they want you to do an IBIS sim... > > > > -andyArticle: 33774
Austin Franklin wrote: > > > I was merely making the observation that cost and size of company do not > > determine the quality of a design. > > I would absolutely agree with that. > > > I do > > realize the that large designs do not necessarily use many pips. In fact, > for > > high performance designs, I try to minimize the number of pips crossed. > > One thing is nagging me about this... I believe I was reading that the > intention of this "test" was to maximize the number of pips/resources used > on a single chip...and that seemed to induce failure. I may not be saying > that correctly, but follow me...my head is still on vacation. Pips are > quite resistive, and they also will degrade the signal... I seem to > remember a time ago, when you could only go through so many pips without > having to be "re-powered". Might there be an internal EMI issue, heat issue > or general signal integrity issue causing these failures? I didn't read > that they were hard failures, or that they were even tested for hard > failures after a failure was found? The tools might be causing the problem, > not taking into account actual signal integrity issues in the chip... Just > a though... > > The numbers just seem way too high to me too...and I'd have to say I've > shipped many tens of thousands of FPGAs, with VERY dense, fast designs, and > not seen anything remotely like this... I may be talking out of my hat, but it seems that most posters are missing one point. We all my have done a lot of designs and we may have worked with a lot of chips, but Joshua's application exercises many chips with many different designs each and every time. If he does not find the "hidden" defects, his customers will find them. In your designs, you may have a few iterations of a given design, but you likely have many, many fewer than 100. Even those will have a lot of commonality. So if you don't exercise all of your boards with a lot of different and possibly "exotic" designs, you may not see anything like the defect rates Joshua is talking about. BTW, if 1 pp 5000 is not an acceptable noticed defect rate, what is? I have never worked in high volume manufacturing and I would like to know what are typical failure rates for complex ICs. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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