Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Kevin Neilson wrote: > An alternative using a conventional VCO-based PLL with an FPGA would be to > implement most of the PLL as a DDS. Not really. First the frequency has to be PLL'ed up. A DDS just makes a frequency lower, much lower usually. Some of the more expensive Analog devices DDS have selectable PLLs. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 68726
Hey i was wondering if any one had any idea how to create some sorta bus interface that would communicate between a FPGA (Spartan D2E) and a CLPD (DI02) board.. somethin like wait ready write sorta thing.. any idea. coz i am having trouble trying to get the switches to work on the cpld throug the fpga. any idea and recommendations would help greatly.. Thnx inadvance! TyronArticle: 68727
Oleg, If ModelSim does not open at all usually this is an indication that the ModelSim path is not setup correctly. If ModelSim does open, failures of this sort can be related to the amount of time required to launch the ModelSim process and for it to get through its startup and to communicate back to Sysgen. The delay can be a function of processor speed, local vs. network installation, licensing issues, etc. Sysgen v6.1 is set to wait to hear from ModelSim for a fixed period of time and if this time is exceeded then this error will be seen in Sysgen. To improve load time try moving ModelSim to the front of your path and license environment variables. Later, Chris Oleg wrote: >Hi, >I am using system generator 6.1 withing Matlab 13 and ISE 6.1 and >modelsim 5.7d. When i run a HDL co-simulation of my black box(imported >VHDL to black box), the modelsim shows the following error: the >communication interface timeout, simulation halted.....and all >Matlab's windows hangs up indefinitly. >When i simulate my imported VHDL entity in black box it doesnt react >to the stimulus generated by simulink. I can see the test vectors >applied by simulink to my black box but this one doesnt react (output >= 0 all time) >Thanks for any help > >Article: 68728
Rajeev, System Generator for DSP now supports HDL Co-Simulation using ModelSim. This allows you to BlackBox your HDL, and bring it into Simulink. When you simulate the design, ModelSim is called by SysGen in order to simulate the HDL. You can find out more informaiton here. http://support.xilinx.com/products/software/sysgen/features.htm#importing Later, Chris Rajeev wrote: >Oleg, > >In Altera DSPBuilder I have found that it is not possible to simulate >external VHDL, if I want simulation I have to fill in the black box with >equivalent model built out of Simulink _or_ Altera blocks. I would be >very interested to know if System Generator supports simulation of external >VHDL. > >However Matlab and Mentor have a product available that allows running >ModelSim VHDL and Verilog simulations from Matlab+Simulink. > >http://www.mathworks.com/company/pressroom/articles/article7062.html > >http://www.mathworks.com/products/modelsim/ > >I'm also interested to hear your overall experience and satisfaction with >SystemGenerator, online or off. > >Regards, >-rajeev- >--------------- >benkhalh@hotmail.com (Oleg) wrote in message news:<5f8ab9cc.0404141146.31389696@posting.google.com>... > > >>Hi, >>I am using system generator 6.1 withing Matlab 13 and ISE 6.1 and >>modelsim 5.7d. When i run a HDL co-simulation of my black box(imported >>VHDL to black box), the modelsim shows the following error: the >>communication interface timeout, simulation halted.....and all >>Matlab's windows hangs up indefinitly. >>When i simulate my imported VHDL entity in black box it doesnt react >>to the stimulus generated by simulink. I can see the test vectors >>applied by simulink to my black box but this one doesnt react (output >>= 0 all time) >>Thanks for any help >> >>Article: 68729
Hi, there: I am looking for PCI Express speficitaion...May I know where I can get it besides the PCI SIG? I have no membership with that sig... KelvinArticle: 68730
Hi, Does any one used ICAP with Microblaze? I am trying to read some frames using documentation from XAPP662. I modified the ipif core(Xapp661 reference design) given by xilinx to work with OPB. Everything is working fine in simulation, I mean signals to ICAP are going as in the Xapp662 document. while implementaion I am getting just zeros. I used virtex2v1000, with 24MHz clock. can any one give me some suggestions. Any help will be most appreciated. Thanks ArunArticle: 68731
Hi Arun, Arun wrote: > I am trying to read some frames using documentation from XAPP662. > I modified the ipif core(Xapp661 reference design) given by xilinx to > work with OPB. Everything is working fine in simulation, I mean > signals to ICAP are going as in the Xapp662 document. while > implementaion I am getting just zeros. I used virtex2v1000, with 24MHz > clock. can any one give me some suggestions. Any help will be most > appreciated. I recommend you use the OPB_XHWICAP core that ships with EDK6.2... it's got some good supporting drivers that wil help you get going more quickly than rolling your own. Regards, JohnArticle: 68732
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:407f3188@news.starhub.net.sg... > Hi, there: > > I am looking for PCI Express speficitaion...May I know where I can get it > besides the PCI SIG? http://www.mindshare.com/pciexpress/pciexpress_books_main.html HendraArticle: 68733
rajeev wrote : > In Altera DSPBuilder I have found that it is not possible to simulate > external VHDL, if I want simulation I have to fill in the black box with > equivalent model built out of Simulink _or_ Altera blocks. I would be > very interested to know if System Generator supports simulation of external > VHDL. Yes you can simulat imported VHDL in to black box using system generator i done it many time in univesity computer but i dont know why i can do so in other computer containing same required softwares...??? rajeev wrote : > However Matlab and Mentor have a product available that allows running > ModelSim VHDL and Verilog simulations from Matlab+Simulink. Yes its good tool but it can only simulat your design. System generator can also (after you simulat your design to make sure it work correctly) implement you design in the FPGA and make a test (simulation) in the hardwar which is caled hardward co-simulation. RegardsArticle: 68734
I'm looking at designing with Spartan 3. The data sheet says the power-on-reset timing ranges from 5-7ms. Does anyone have any design tips/suggestions for meeting this spec? Anything I should watch out for?Article: 68735
[Austin & Paul, thanks for the civilized and interesting discussion.] > Poor Adam, I knew him, and traveled and lectured with him a long time > ago. Funny his failure is now a standard business school study case. He > is but one example of why we should all strive to be humble.... > > http://en.wikipedia.org/wiki/Adam_Osborne The Computer History Museum recently had an "Osborne Odyssey" evening which gave a bit more nuanced view into the story. The impression I got from the evening was one of a somewhat poorly organized company and Osborne not really being qualified for running the business. The new machines, while ready to ship, where held back because floppy disks could occasionally get stuck in the drive (requiring a plier to get them out). Another interesting tidbit: Osborne was quite arrogant and would readily turn down interested resellers for "not being professional enough". All while the major competitor Kaypro would sell as many or as few as anyone would like. TommyArticle: 68736
tyron123@yahoo.com (Tyron) wrote in news:3e4a6899.0404151220.211d7156 @posting.google.com: > Hey > i was wondering if any one had any idea how to create some sorta bus > interface that would communicate between a FPGA (Spartan D2E) and a > CLPD (DI02) board.. somethin like wait ready write sorta thing.. any > idea. coz i am having trouble trying to get the switches to work on > the cpld throug the fpga. > any idea and recommendations would help greatly.. > Thnx inadvance! > Tyron > We just published a Compact Flash / IDE hard drive interface for the XSB- 300E Board that uses a wait-ready type of interface since the FPGA is much faster than the PIO mode interface. The documentation is here: http://www.xess.com/appnotes/an-041404-atacntl.pdf and the design files are here: http://www.xess.com/projects/xsbatacntl.zip The pioIntfc module in the atacntl.vhd file may be similar to what you need since it generates the slow read and write pulses that are needed to talk to the disk / CF card. -- || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 || || devb@xess.com PO Box 33091 || || http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||Article: 68737
"Kelvin @ SG" <kelvin8157@hotmail.com> writes: > I am looking for PCI Express speficitaion...May I know where I can get it > besides the PCI SIG? > I have no membership with that sig... You have to be a member to get the specficiation. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 68738
Hi, ist there any vhdl example published for use of an external SRAM as a dual ported RAM? I imagine a state machine writing a data flow into the RAM, and a short FIFO for the read path out of the RAM, and some logic feeding the FIFO and handling the arbitration to the RAM. Maybe a write FIFO is also necessary. The RAM has 512k x 8. Thanks for any hint. Klaus HiltropArticle: 68739
Hi, What is the need for PLL / DLL ? what kind of system requires this? When it is required? Regards, MuthuArticle: 68740
<khiltrop@gesytec.de> wrote in message news:c5o15r$eoc$1@swifty.westend.com... > Hi, > > > ist there any vhdl example published for use of an external SRAM as a dual > ported RAM? > > I imagine a state machine writing a data flow into the RAM, > and a short FIFO for the read path out of the RAM, > and some logic feeding the FIFO and handling the arbitration to the RAM. > Maybe a write FIFO is also necessary. > > The RAM has 512k x 8. > > Thanks for any hint. > > > Klaus Hiltrop > Hi, I have found this http://www.itee.uq.edu.au/~peters/xsvboard/index.html which explains a lot but I am still looking for better.. Christos.Article: 68741
I thought I might go for a green and not red apple... We have been discussing at work the need for subscritions and who we pay. Has anybody done comparisons re: timing and 'compactness' for symplify vrs xst in small (<150k) FPGA's. We are using a number of spartan 2e 150's and a few 50's too and I was wondering about the need for the symplify tools. SimonArticle: 68742
Registers are usually reset/set as part of configuration. It depends on the types of registers implemented. However you can also use the DONE signal to drive an external reset chip that will extend the reset beyond configuration by an amount. There also some logic configurations that you can use to add a delay beyond configuration. If you are worried about DLL lockup you can gate the locked signals into a reset signal. -- John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Steve Smith" <stevesmith_98@yahoo.com> wrote in message news:5da07ec1.0404151930.498c5fa7@posting.google.com... > I'm looking at designing with Spartan 3. The data sheet says the > power-on-reset timing ranges from 5-7ms. Does anyone have any design > tips/suggestions for meeting this spec? Anything I should watch out > for?Article: 68743
Hi all, i have got a basic doubt in altera's flex10 k library component "8count" which is a 8-bit up/down counter.This library component has a output named "COUT" is it the decoded version of terminal count(255) or something else ?? any body can clarify this!! thanks in advance rgds, pravArticle: 68744
Tyron,
For the DIO2/D2E board you have, there are reference manuals
and schematics. See the page:
http://www.digilentinc.com/Materials/current.html
There should be timing diagrams in the DIO2 manual.
In fact, there should be VHDL code in the DIO2 manual.
Cheers,
Jim
There are also examples in the board verification link.
Tyron wrote:
> Hey
> i was wondering if any one had any idea how to create some sorta bus
> interface that would communicate between a FPGA (Spartan D2E) and a
> CLPD (DI02) board.. somethin like wait ready write sorta thing.. any
> idea. coz i am having trouble trying to get the switches to work on
> the cpld throug the fpga.
> any idea and recommendations would help greatly..
> Thnx inadvance!
> Tyron
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 68745T. Irmen wrote: > Hi Magnus, Hi Thomas, > strange application but anyhow: > > I guess, when I look at ieee802.3ae appendix 44a figure 44a-1 the "sync > header bits" were prepended every 64 scrambled bits, Exactly. In IEEE 802.3 (802.3ae is now included in the 802.3 document) 10GBASE-X the 64 data bits is scrambled and the 2 sync bits are not. However, the sync bits are DC balanced by the "64B66B" encoder (quotes is there not to confuse it with a real line encoder like 4B/5B or 8B/10B, it's really just an encoder of various "messages") as indicated by Figure 49-7 where sync bits 01 means data and 10 means control block, so that is really just a one bit transmission channel using two symbols per transmitted bit (1B/2B). So, those block codes may or may not be usefull, and when doing a non-10GBASE-X application using that hardware, it may be a design-choice not to use the 64B/66B encoder since it does not really do much for the actual line encoding (DC-balance, rate of transitions) except for the two sync-bits in every 66 symbol period. I can acheive the goals of a line encoding (DC-balance, rate of transitions, alignment) without the 64B/66B encoder/decoder block as long as I ensure the DC balance of the sync bits. Using one as the direct transmission channel and the other just being the inverted version of that channel, I have acheived the same 1B/2B encoding style on which alignment depends as well as the DC-balancing. > by the way a great way to synchronize via barrel shifter. Not really. It uses much more overhead than needed, but for an application like 10GE I guess it's OK. > I think if you donīt want that behavior search for a switch in the xilinx > manual to switch of sync header generation, or scramble by yourself. (Do you > only rely on the balancing character of the scrambler polynom?) The full 64B/66B encoding path of 10GBASE-X only depends on the scrambling for the data bits for balancing. It's just like in SDH/SONET, but with a sufficiently long self-synchronous scrambler. I'm not really depending on stuff much differently than in 10GBASE-X, I'm just considering using it differently to fit my needs. Cheers, MagnusArticle: 68746
Meng Soo wrote: > Magnus, Hi Meng, > I'm not sure about the 64B/66B encoder, but in 8B/10B mode, the extra > bits are sent/received on TX/RXCHARDISPMODE and TX/RXCHARDISPVAL Yes, I am aware of that. But it would be an assumption made by me, and I wanted to make sure that my assumption was going to be validated since the UG didn't give that detail. Since I asked, the UG35 has come out in V1.3, which does state that TXCHARDISPVAL[0] and TXCHARDISPMODE[0] receives the sync bits [0] and [1] respectively, but the receiver side is however still unclear, but it should probably be safe to assume the same mapping for the RX side. > The following app note outlines the connections > http://www.xilinx.com/bvdocs/appnotes/xapp649.pdf > > I'd assume that the 64B/66B mode is similar. Yes, assume is the word. Too many assumptions and I have a hell of a debugging to do. Better nail it down early. Cheers, MagnusArticle: 68747
Tommy Thorn <TommyAtNumba-Tu.Com--not@yahoo.com> wrote in message news:<M6Jfc.6089$Fo4.73141@typhoon.sonic.net>... > [Austin & Paul, thanks for the civilized and interesting discussion.] > > > Poor Adam, I knew him, and traveled and lectured with him a long time > > ago. Funny his failure is now a standard business school study case. He > > is but one example of why we should all strive to be humble.... > > > > http://en.wikipedia.org/wiki/Adam_Osborne > > The Computer History Museum recently had an "Osborne Odyssey" evening > which gave a bit more nuanced view into the story. The impression I got > from the evening was one of a somewhat poorly organized company and > Osborne not really being qualified for running the business. > > The new machines, while ready to ship, where held back because floppy > disks could occasionally get stuck in the drive (requiring a plier to > get them out). > > Another interesting tidbit: Osborne was quite arrogant and would readily > turn down interested resellers for "not being professional enough". All > while the major competitor Kaypro would sell as many or as few as anyone > would like. > > Tommy He came to visit us at Inmos (for a big stash of pounds) in 79/80 to tell us what he thought we should be doing in micro architecture given his knowledge of 8080s and so on. I think everyone concluded what a waste of money, nice fella but essentially telling us to do same as Intel,Moto. Kind of brought in as a celebrity. Well he was a brit so we were curious about him. He certainely had solid views on architecture, he was wrong, and later some might say so were we (or maybe not). regards johnjakson_usa_comArticle: 68748
Thank you Christos, your link finally leads to www.xess.com, a very good source. I did not find what I am looking for, however, it's also possible I overlooked a good example. ----------- Indeed in my case the incoming (serial) data stream cannot be interrupted and needs to put data into RAM immediately. Because of the serial-parallel conversion there is time to read data for the other side which wants to get the data out of the RAM, asynchronously to the in-data-stream. As I cannot preview when the serial stream sends data or stops, I need to fill a FIFO at least for the reading side as long as any data is available in the RAM. writing into RAM and reading from it seems from outside completely asynchronous. Maybe I will also need a FIFO for the in-data as the routine/state machine filling the read-FIFO cannot know when new data-in comes. There is a sort of arbiter necessary controlling the accesses to the RAM. A short buffer of this type could be realized inside the FPGA with a dual ported RAM, however 512k Bytes is too much. In order to keep cost of the final product low the external RAM should be a usual single port RAM. KlausArticle: 68749
Hello, At this time I write manually in the field "user code" of Quartus an hexadecimal 8 digits timebased code, which is displayed in the window of the FPGA programmer. And often, I forget to to fill up this field in the setting of Quartus, and I read back FFFFFFFF! I have a lot of different FPGA to synthetise , so I start up Symplify in a loop in a TCL script, and then Quartus is launched by Synplify and reads the tcl script written by Synplify. Is there any way to do that automatically, by passing this parameter from Symplify?? I know the way to automatically pass a time based constant or a generic to Symplify, and put it in a special register on ROM, but I think that the User Code of the FPGA is the right place to put this value!! Thanks, Pierre-Louis
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z