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Hi, I am wondering what's the difference between MPGA and FPGA? MPGA is Mask Programmed Gate Array. What does Mask mean here? sincerely ------------- Kuan Zhou ECSE departmentArticle: 68951
Matthew Ouellette <matt.ouellette@xilinx.comNOSPAM> wrote in message news:<408731B0.2070809@xilinx.comNOSPAM>... > Hiro, > > The OPB inclued in the EDK supports burst transactions. However, a > potential limiting factor may be some of the IP that we deliver which > doesn't support burst transactions (for instance, the MicroBlaze I and D > Master OPB connections do not support burst currently). > > Matt > > hiro wrote: > > Dear All, > > > > Does OPB bus(V2.0) included in Xilinx EDK6.2 support burst transfer > > mode (fixed burst or variable burst)? > > If yes, how many data can it transfer(read/write) at one operation? > > > > Hiro Hi Matt, If we write our own IP Master that supports burst transfers and attach it to OPB along with microblaze. Will the system work? Regards ArunArticle: 68952
A mask-programmable gate array uses one (or more) metal mask in the IC manufacturing process, to achieve the intended functionality. In an FPGA, the user programs a standard off-the shelf chip, either by loading a bitstream into latches, or into Flash cells, or by programming antifuses. The manufacturer just provides software support. Peter Alfke > From: Kuan Zhou <zhouk@rpi.edu> > Organization: Rensselaer Polytechnic Institute, Troy NY, USA > Newsgroups: comp.arch.fpga > Date: Thu, 22 Apr 2004 17:39:53 -0400 > Subject: What is MPGA? > > Hi, > I am wondering what's the difference between MPGA and FPGA? > MPGA is Mask Programmed Gate Array. What does Mask mean here? > > > > sincerely > ------------- > Kuan Zhou > ECSE department > >Article: 68953
Jim Granville wrote: [Old topic Issues on Shift Register in a Clockless UART ] > That design can be done with a delay line ( which needs baud-precision - not really a common building block...), plus it's not clear how it would manage sync in packed streaming data... > ( I've changed the topic, as that thread was looking like someone's homework.) I think there is scope to study more what can, and can't be done with delay lines. FPGAs cannot clock above 1GHz, but they CAN resolve time to ~140ps regions, in some cases ( see Peter A's posts ). Taking the example above, delay line bit sampling is easy enough, but the byte sync is rather harder. I think the only solution is a longer delay line, and wider stop bits - so the data is framed as 8(+) Stop bits, 1 start Bit, 8 data bits... (8 bits is illustrative only) A capture is triggered only when the delay line taps show 8 stop bits, and one start - otherwise the data 'leaving' the delay line can trigger false captures. Txmit would be via a register chain/MUX tree, that loads/holds until flipped from 'wait' to 'delaylinego', then data would stream out. Pacing would be done from a slower clock, but the time domain precision of this would be delay element sized (~140ps) This assumes, of course, that access to this detail is possible in the FPGA hardware :) All up, data rates in the GigaBaud region would appear do-able. There are benefits to thinking more in time-domain, rather than simple MHz - once the ideas are there, the tools and fabric can follow. -jgArticle: 68954
fpgadev@yahoo.com (AndyAtHome) wrote in message news:<29ab33c4.0404220812.3fe7b63@posting.google.com>... > Dear All, > > I'm just about to purchase Xilinx ISE BaseX plus MXE for 1,295 USD. > Having downloaded the free edition I have to say I'm less than > impressed with the general user friendliness - no keyboard shortcuts, > no code completion, etc. > I haven't had any gripes with Webpack XST other than very optimistic XST synth results for sp3. KB shortcuts wouldn't save me much, you can use other text editors instead of that provided like TextPad with language support. I am not sure code completion means much, if the tool could guess what you want, I thinks it would be mostly wrong. HDL keyword completion might help a little but code entry is pretty minimal part of design isn't it. Theres also the templates ready made to edit. > Is it the case that in terms of commercial tools chains ISE plus > Modelsim is the only thing in the market under $2,000? > At a DAC show I picked up a full license for 1 of the other Verilog simulators for $1K, it was the 1st time they ever sold a license on the floor to an EE. Normally EDA budgets are out of EE hands so they usually only sell outside the show to accounts. > It would be great to hear from any other Xilinx developer's that have > found an alternative under 2,000 USD. > There is also the free HDL simulators but I haven't tried them. > Thanks, > > Andy. regards johnjakson_usa_comArticle: 68955
Let me describe today's and tomorrow's capabilities. Inside the FPGS, the general-purpose routing structure makes it difficult to clock GP logic much faster than 500 MHz, but dedicated functions can be pushed faster, perhaps to 800 MHz. On-chip clock delay can be completely eliminated, and global clock skew can (hopefully) be kept below 150 ps. Clock phase shifting can have <30 ps resolution. When saving pc-board area and interconnect pins is important, dedicated transceivers can run (today in SpartanProX) at slightly over 10 gigabits/second (100 picosecond per bit). These are all fairly realistic parameters for aggressive designs. Just my personal observations, not an official Xilinx position. Peter Alfke > From: Jim Granville <no.spam@designtools.co.nz> > Organization: TelstraClear > Newsgroups: comp.arch.fpga > Date: Fri, 23 Apr 2004 10:48:59 +1200 > Subject: Time domain/Delay line UARTs - high speeds > > Jim Granville wrote: [Old topic Issues on Shift Register in a > Clockless UART ] >> That design can be done with a delay line ( which needs > baud-precision - not really a common building block...), > plus it's not clear how it would manage sync in packed streaming data... >> > > ( I've changed the topic, as that thread was looking like someone's > homework.) > > I think there is scope to study more what can, and can't be done with > delay lines. > FPGAs cannot clock above 1GHz, but they CAN resolve time to > ~140ps regions, in some cases ( see Peter A's posts ). > > Taking the example above, delay line bit sampling is easy enough, but > the byte sync is rather harder. I think the only solution is > a longer delay line, and wider stop bits - so the data is framed > as 8(+) Stop bits, 1 start Bit, 8 data bits... > (8 bits is illustrative only) > > A capture is triggered only when the delay line taps show > 8 stop bits, and one start - otherwise the data 'leaving' the delay > line can trigger false captures. > > Txmit would be via a register chain/MUX tree, that loads/holds > until flipped from 'wait' to 'delaylinego', then data would stream > out. Pacing would be done from a slower clock, but the time > domain precision of this would be delay element sized (~140ps) > This assumes, of course, that access to this detail is possible > in the FPGA hardware :) > > All up, data rates in the GigaBaud region would appear do-able. > > There are benefits to thinking more in time-domain, rather > than simple MHz - once the ideas are there, the tools and fabric > can follow. > > -jg >Article: 68956
> > > I have read the solution #2561 about how to compile librarie for
> > > modelsim. I download the tcl script file, but I don't know how to use
> > > it. Can anybody tell me?Thanks
Just downloaded the zip file xilinx_lib_4.zip from solution 2561 from:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=2561
And the readme.txt is as followed:
README FOR XILINX LIBRARIES AID FOR MODELSIM
Tcl script to install and compile Xilinx 3.x/4.x HDL (Verilog/VHDL)
libraries using Modelsim 5.4x/5.5x SE/PE simulators
NOTE: Tested with 5.5c SE
------------------------------------------------------------------------
Installation:
FOR EE:
Use the "source" command from the ModelSim prompt to load that Tcl/Tk
code. At the Modelsim prompt, type
MODELSIM> source <path_to_script>/xilinx_lib.tcl
FOR PE:
Set the enviroment variable MODELSIM_TCL to the name of the script prior
to invoking ModelSim. [Note: MODELSIM_TCL can be a ":" separated list of
Tcl/Tk files to load].
MODELSIM_TCL <path_to_script>/xilinx_lib.tcl
Where <path_to_script> is the pathname for the directory to where the
script was saved.
FOR MXE:
Not to be used with MXE. The HDL libraries come precompiled for MXE.
------------------------------------------------------------------------
USE:
The "Xilinx Libraries Aid" window will pop up. Enter the following
information:
- Select the language whose libraries need to be compiled.
- Select the version of the Xilinx software installed on the
computer.
IMPORTANT NOTE: An incorrect selection of "Xilinx Software
Version" will lead to errors during the installation of the libraries.
- Select which libraries need to be compiled.
- Enter the "Install Path" where the compiled libraries will be
saved.
- Enter the path to the Xilinx software on the machine. (eg.
C:\fndtn or D:\xilinx)
- Once all the information has been entered, press the "Compile"
button to compile the desired libraries.
DISCLAIMER: This is a tactical script created for the sole purpose
of easing the compilation of Xilinx libraries for Modelsim.
Article: 68957while configuring the virtex device I keep getting the error " INIT pin does not go high". I have checked all the connections but it still stays. PLease let me know what could be causing this and how i could resolve it. I have tried configuring a simple and gate but it still doesnt work. THanks, ZIncArticle: 68958
Peter Alfke wrote: (in answer to a question about a clockless UART) > Simple answer: You cannot. You can of course generate your own clock... Someone I know used to have a paper tape reader that you would pull the tape through by hand. A row of phototransistors and LEDs would sense the holes as they went by, including the row of clock holes. I had wondered about making a card reader using a similar design, but there are no clock holes. It would be necessary to either run the card at a constant speed, or otherwise measure the speed or position of the card. A rubber wheel and phototransistor/LED sensor to read its position should be enough. Paper tape is self clocking but punched cards are not. -- glenArticle: 68959
Someone wrote: >>I am wondering what's the difference between MPGA and FPGA? >>MPGA is Mask Programmed Gate Array. What does Mask mean here? >>Peter Alfke wrote: > A mask-programmable gate array uses one (or more) metal mask in the IC > manufacturing process, to achieve the intended functionality. > In an FPGA, the user programs a standard off-the shelf chip, either by > loading a bitstream into latches, or into Flash cells, or by programming > antifuses. > The manufacturer just provides software support. If I remember this right, originally there were Gate Arrays, which were actually closer to transistor arrays. Everything needed to make logic circuits except the metal layer. (Maybe only one or two at the time.) NRE costs are lower than standard cell or custom logic, though usable density was a little lower, too. Then along came FPGA's, so the original ones have been renamed? -- glenArticle: 68960
check out at Xilinx.com , online store, there are many proto type boards. if you are from university and yours is research project, Xilinx is Kind enough to donate you not only the boards but all the software tools. - one who's been benefitted by XUPArticle: 68961
Hi I have been following this conversations for quite a while, and i have to completely agree with rickman, as of me, I have had lot of help from Xilinx experts and others in this group which expedited my work manyfolds. Another aspect I like to express is, how this group helps emerging engineers ( I will be graduating as a MS grad this may) , it motivates and it critizes and applauds. Actaully now I take every step to help others and share ideas so that they dont go thro the same frustration i have had sometimes. Thanks Group -- RamArticle: 68962
Rajiv, Component instantiation will be the easiest method to implement 8 bit alu, from one bit alu's in your design. creat a vhdl for 8 bit alu declare one bit alu instantiate and map the ports RamArticle: 68963
serdar, go to www.support.xilinx.com and select documentation tab, under this section there is a link for tutorials, this is the starting point. RamArticle: 68964
"sunil" <inaganti_suni@yahoo.com> wrote in message news:9f28d282.0404220159.164f8828@posting.google.com... > HI, > Thanks to all who gave a response. Actually i need the VCD file > for power calculation. So, please tell me whther i have to simulate > with the correct data(clk frequnecy depends on the max.frequency > allowed) or not for generating VCD file. Your estimate is likely to be no better than what you give the tool to work with. Xpower will give an estimate based on activity rates you provide--either default, or manually, or via vcd. Your simulation should reflect what you would want to measure. JasonArticle: 68965
If you need to open an arbitrary file (like I often want to do), define it as a generic, with a default value. When you call the simulator (I've worked with Modelsim doing this), provide the generic as part of the call. E.g., vsim tb_config -ggeneric1=generic1value ... (other options.) Then you can set up a script (or batch file) with whatever value you need for the generic-- or just manually type in every time you run it. Jason "paris" <273986malaka@email.it> wrote in message news:c64kuc$ut8$1@avanie.enst.fr... > hi guys, > > im having some trouble with reading from a file, actually the thing is the > opening part. > the problem is that i "dont" know the name of the file to read before > compiling, that is because i've a "configuration" file where i give > commands, one of them being the name of the "input" file. > > i know i could use a function, but that only works when i've a small amount > of data to read, cause otherwise, storing a HUGE array slows down the > simulation, without saying that modelsim tells me that i has not enough > memory and will start paging to disk and after a while it says that i got > completely out of memory. > > Simulation works perfect if i read one line (of the input file) at the time, > but that means that the filename has to be written on the code (at least > that's how i've been doing, by using ' file fp : TEXT is in "input.dat"; ') > > now i need to open an arbitrary file, so i tried "file_open(fp, > filenameString, READ_MODE);" the problem is that somehow it doesnt work, as > it seems that if i open the file in one process (i have to open the file > just once and read it till the end of the file at every rising_edge(clk), so > that's two processes). It doesnt work cause it seems that the file is > "closed" outside the process it was opened (i think i even read about that > issue). > > Also i cant find "file_open" declaration. > > i also tried with a process like this: (im at home now, so i dont have the > real sources, but i cant sleep so im writing to ask for help :) please) > > process > begin > > if (filenameString /= nothing) then > file_open(fp, filenameString, READ_MODE); > > while (not endfile(fp)) loop > wait until rising_edge(clk); > read(fp, data); > etc, etc > end loop; > file_close(fp); > end if; > end process; > > that didnt work either, im not sure if it was because of the file_open part > (i also did a check on the opening, it was succesful) or because the process > get in an infinite loop, modelsim just stop responding (i think that endfile > might return false if the file is not open, giving rise to the infinite > loop, but the loop would at least be "waiting" for "clk" and it would > actually read the data, but that doesnt happen). The file might get closed > once "out" the process (like when another process gets executed) or > something, i have no clue... > > do any of you knows or have faced already this kind of situation? namely, > reading a file whose name's specified after compilation (by another file) > line by line (that is, not using a function to read a whole chunk of data > and storing it in an array) > > any comments will be appreciated, thanks > > > > Paris > > > >Article: 68966
Hi, newgrouper, does anyone know what dqm does ? The specification of micron is vague. What mask function does it mean ? Thanks Steven.Article: 68967
Steven wrote: > Hi, newgrouper, > > does anyone know what dqm does ? The specification of micron is > vague. What mask function does it mean ? > > Thanks > > Steven. Hi My interpretation is that the mask means that you can choose to not overwrite parts of existing data when you do a write to a certain address. A little example: If you have a data width of 64 bits and have 8 bits of dqm:s, and have a data architecture that use byte-variables. Then you can store 8 variables on one address and change one without destroy the others by using dqm as byte-enable. If I'm wrong I'm sure someone will correct me. /PfnaArticle: 68968
Does anyone know some examples of using CPLD or FPGA devices in railways = equipment? Regards JacekArticle: 68969
Hello, how do I connect a 64-bit wide SODIMM-SDRAM-module to a 32-bit SDRAM-controller? I saw different ways in the web (from connecting the upper and lower 32-bit together on the pcb and making the selection with the 8 dqm lines to very strange connections of the address lines to the dqm pins and different chip select) but have no idea which one is really working and the best way. I am currently totally free because the schematics are at the beginning. Best Regards, MarcArticle: 68970
In article <c6anq7$7r$1@news.onet.pl>
jacekmocki@poczta.onet.pl "Jacek Mocki" writes:
> This is a multi-part message in MIME format.
>
> ------=_NextPart_000_0033_01C42926.EA90A2E0
> Content-Type: text/plain;
> charset="iso-8859-1"
> Content-Transfer-Encoding: quoted-printable
>
> Does anyone know some examples of using CPLD or FPGA devices in railways =
> equipment?
>
> Regards
Yes. I think it was a Xilinx FPGA in a trainboard air conditioning
system. Normalair Garret IIRC. Can't be too certain as I only ever
had a very brief glimpse.
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Article: 68971This is off topic for the news group, but I know there is a vast array of experience here, hopefully someone can help. I've an application where I need a 20MHz clock which can be adjusted by +/- 2% (rough requirements, the client doesn't actually know what's required). The timebase of frequency adjustments isn't critical. I haven't been given any jitter specs. This has to be incorporated in a working prototype in 3 weeks so the solution must be simple and fairly stable. The VCXOs that I've found are adjustable by at most 200ppm, so this isn't an option. I'm thinking of using a 74LS624 with a single pin DAC driving the frequency control input. The data sheet specifies 20MHz as the maximum output frequency, but the performance graphs show outputs at up to 30MHz. The prototype board I'm using has an Altera Cyclone (EP1C6). Ideal requirements... 20MHz +/- 2%, easily adjustable. Simple (single device ?) Operates from 3.3V supply Can be sourced from distributor in a couple of days. Thanks for any ideas, Nial StewartArticle: 68972
"AndyAtHome" <fpgadev@yahoo.com> wrote in message news:29ab33c4.0404220812.3fe7b63@posting.google.com... > Dear All, > > I'm just about to purchase Xilinx ISE BaseX plus MXE for 1,295 USD. > Having downloaded the free edition I have to say I'm less than > impressed with the general user friendliness - no keyboard shortcuts, > no code completion, etc. As Jon says, don't rely on the P+R tools for design entry, there are much better text editors about (I too use Textpad). > Is it the case that in terms of commercial tools chains ISE plus > Modelsim is the only thing in the market under $2,000? The 'full' version of Modelsim is >$5K I think. Have a look at .. www.symphonyeda.com ..for a less expensive alternative. Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 68973
Nial Stewart wrote: > This is off topic for the news group, but I know there > is a vast array of experience here, hopefully someone > can help. > > I've an application where I need a 20MHz clock which can > be adjusted by +/- 2% (rough requirements, the client doesn't > actually know what's required). The timebase of frequency > adjustments isn't critical. I haven't been given any > jitter specs. > > This has to be incorporated in a working prototype in > 3 weeks so the solution must be simple and fairly > stable. > > The VCXOs that I've found are adjustable by at most > 200ppm, so this isn't an option. > > I'm thinking of using a 74LS624 with a single pin DAC > driving the frequency control input. The data sheet > specifies 20MHz as the maximum output frequency, but > the performance graphs show outputs at up to 30MHz. > > > The prototype board I'm using has an Altera Cyclone > (EP1C6). > > Ideal requirements... > 20MHz +/- 2%, easily adjustable. > Simple (single device ?) > Operates from 3.3V supply > Can be sourced from distributor in a couple of days. > LTC6900, LTC6903 from linear technology Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 68974
Jacek, Yes we have FPGAs that have been used in railway equipment. The problem is the sometimes close to ten year qualification process* for railway equipment, which means by the time it is qualified for use, the parts are well into their obsolesence. If you have such an application, you should contact a Xilinx FAE, and discuss the best choice of product with them (one that we expect will be around for another > 20 years like the 2K has been, and the 3K will have been). As always, if any of our products are used in an application where human life despends on the perfect functioning, see the very serious legal stuff at: http://www.xilinx.com/legal.htm For example, we heard that a manufacturer wants to use an FPGA in a nuclear reactor control system. That certainly gets our attention, as we insisted that the design be done in such a way that is consistent with the application (ie fully TMR, dual redundant, hot standby, etc etc etc). *(based on what I've heard about a certain railway equipment supplier) Austin Jacek Mocki wrote: > Does anyone know some examples of using CPLD or FPGA devices in railways > equipment? > > Regards > > Jacek
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