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Jim Granville wrote: > Martin Maurer wrote: > > Hello, > > > > i am using a FSM in my CPLD design (XC95108). It is written in ABL. It is > > working fine so far, beside some curious behaviour. On some special > > condition it seems, my FSM stops working. Something like the token gets lost > > ??? I have seen it when a lot of "traffic" is on a lot of lines, sometimes > > already at start up (i still have the xilinx boot adapter connected all the > > time, when i then do a verify of my written program it is running again, > > verify succeeded of course). I have not used any global inputs (they are > > N.C.), for the state machine i have a initial state inside my abel sources. > > I jump everytime from one state to another, can't see any state which gets > > lost. > > > > Can you give me a tip for this how to solve it ? Can i use something like a > > "default" case to come back even i such a case ? I read that one hot state > > machines are not the best things for CPLD. When i convert it, will it solve > > my problem ? Is there an easy way of converting it ? > > Look in the .RPT file, to see the state-nodes, and the conditions for > a next-state. If a One-Hot ends up with zero, or >=two bits hi, it may > or may not recover. If you have a spare pin, decode those options to it, > and verify if that is your failure mode. > Causes can be aperture effects, where an external signal is not stable > on the clock edge. Look carefully at async signals that cause state > changes. > recovering from all Zero is simple enough, and could be already done > in your code. > > -jg I concur, looking at the equations in the fitter report file is the place to start. A couple of other notes: 1. In general, a one-hot encoding is not the way to go in CPLDs. It obviously uses more registers to hold the state bits than, say, a gray encoding. For an Abel symbolic FSM, you can specify the state-encoding using the Process Properties for the "Compile Design" step in iSE 6.x. Alternatively, you can put a property statement in the Abel source. Something like: XILINX PROPERTY 'ENUM_ENCODING myFSM=gray'; where myFSM is declared in the Abel source to be a STATE_REGISTER. 2. Be aware that the default behavior of Abel FSMs for unspecified cases is different than VHDL/Verilog. Time has dimmed my memory, but I recall that for a FSM coded in VHDL or Verilog, if you fail to specify the next state for a certain condition, the FSM will simply hold state. Abel FSMs (I think this mainly applies to non-symbolic FSMs) will go to the "all 0's" state, which would not be good for a one-hot (this assumes that the FSM is implemented using D flops). This behavior was very clearly documented in the old Abel Reference Manual, but I haven't looked lately to see how clearly documented it is today. If you need further info, I would suggest contacting the Xilinx Hotline. -Dennis McCrohan Speaking for myself, not for Xilinx.Article: 69051
On 25 Apr 2004 14:30:27 -0700, johnjakson@yahoo.com (john jakson) wrote: >JP@noemail.com wrote in message news:<o1be80trst70j4obop4bosoi0meub5cubh@4ax.com>... >> Hello all, >> >> I am an electrical engineering student and in need of some advice for >> a project. There is a project that involves emulating a 16 bit >> microprocessor in an FPGA and I would like to gain some information >> about where to start. >> So, here are my questions: >> 1) Is it actually possible to emulate a microprocessor in an >> FPGA? >> > >A get ahead of the crowd, student, I like that. > >As Phil says, it is definitely doable but will take some serious >effort. > Hi John, Thank you so much for such a detailed response. I am reviewing it and will follow the links to augment my limited knowledge about this subject. Hopefully, by the fall, I will have learned enough about the field to be able to start the project. Thanks again and take care, JPArticle: 69052
> Someone suggested reducing the fanout of the signals by duplicating > them, but I assume Quartus must be doing that for me. I know xilinx > has a "max fanout" setting, though I couldn't find it in quartus. If I > need to do this manually how will I do this? > To set the Max Fanout use the Quartus II Assignment Editor. The steps are as follows: 1. Click on Assignments->Assignment Editor 2. Click on the Logic Options Button in the top right. 3. Double Click on am empty cell in the To column. You can either type in your instance name whose fan out you want to restrict or click on the arrow button which will bring up the node finder. You can select the name in the node finder and hit OK. 4.In the Assignmnet Name field down select Maximum Fan-Out from the drop down. 5. In the Value Column type on the Fan-Out number. Alternatively if you know the name of the instance whose Fan Out you want to restrict from the timing report, right click on the name in the timing report and select Locate to Assignment Editor. This will open up the Assignment Editor and populate the To column for you. Then follow steps 2, 4 and 5 above. - Subroto Datta Altera Corp.Article: 69053
Anand P Paralkar <anandp@sasken.nospam.com> wrote in message news:<408CA66F.7FAA0E6A@sasken.nospam.com>... > Hi, > > I was talking to an "expert" in synthesis and he mentioned that there is > > a lot of difference between a synthesizable RTL code for a FPGA and a > synthesizable RTL code for an ASIC. > > Is this true? > > If so, could you please point the significant differences between the > two and what causes these differences. > > Thanks, > Anand They don't have to be so different. if you design for ASIC and port to FPGA, the results will be poor as ASICs will allow for maybe 5x as much logic depth per clock cycle up to say a few 100MHz. if you design for FPGA with equiv resources available in ASIC, the results should be good both ways, only faster for ASIC but not as much as the 5x would suggest since you will have taken advantage of what is already fast in FPGA. When RTL is written for for HW that is easy to infer to blocks that can be mapped well onto mults,wide adders, memories, muxes, so on, the differences can be smaller. If most of the logic is unstructured and not very pipelined the differences will be much larger. For ASICs to succeed in the future, I think it would be prudent to design for FPGA if at all possible and expect 1st pass success on ASIC and get early prototypes for months in advance of silicon. Buts thats not always doable, where ASIC will always shine is true full customization for semi digital with some analog content. An all digital low vol 1 clock ASIC is an easy target for FPGA. The ASICs you find in very high (n Mil unit) volumes such as disk controlers, DVD players are way too cost sensitive for FPGAs to make any dent and usually require multiple and varying clock domains with some analog stuff thrown in. For my own tastes, I'd stick to the easy path where they can be more equivalent. regards johnjakson_usa_comArticle: 69054
Marc Randolph <mrand@my-deja.com> wrote in message news:<vfOdnQ0PnMfd8BHdRVn-tw@comcast.com>... > Josh Graham wrote: > > > Hello all, > > I am trying to get XST (ISE 6.1) to infer a dynamic shift register > > implemented using Virtex II LUTS. I have used the VHDL model shown > > below. > > However XST does not use LUTS, instead flip-flops are used. When I > > change the line srout <= sr(n) where n is a static value XST manages > > to use LUTS for the shift register. Can anybody please tell me what I > > am doing wrong. This is the same code as given in XST Synthesis ans > > Verification guide. > > Howdy Josh, > > Does the guide say that it will use only LUTs for an addressable (or > dynamic) shift register? My understanding and experience is that it > will take all consecutive and more importantly, unused bits, and roll > them into a LUT based SRL (assuming it doesn't have a reset). I'm > pretty certain that it is configured during synthesis/map/P&R and can't > be addressable or dynamic. > > Ray Andraka uses these a lot, so I'll bet he has an efficient way to do > what you want (although I would plan on it being larger than your > originally thought). > > Good luck, > > Marc I had the opposite problem in Verilog, when I had a deep pipeline more than 4b deep I think, with no inter logic, it did roll into a wide srl16 and halved my clock in doing so. There is an option in the XST preferences display for turning this feature on/off. I think if I can tune the srl with an extra true FF at the end it will be useable at full speed, just the timing for srls is slower on the output bit. There's also some appnotes on it and there is some template code for these if you look in the right place. I would suggest not coding them directly unless you really know that they must be used. If you suddenly decide to insert logic into the middle, you will have to redo that. regards johnjakson_usa_comArticle: 69055
Hello, I have a problem with peforming master dma with the xilinx pcix core. I'm writing into the systemy memory with 4KB blocks and I use a 4KB-BlockRAM in the FPGA as prefetchable datasource. The BlockRAMs have a read latency of one clock cycle. If I increment the internal source-address-counter with m_data_nxt, then the first piece of data comes out one cycle to late. The Design Guide says that the first piece of data must be presented to the core with assertion of m_attr_vld and the subsequent pieces with m_data_nxt. I thought that this mechanism can compensate the read latency of the BlockRAMs. But it looks like the first piece of data is NOT sampled with assertion of m_attr_vld. Who knows about the problem, when is the first piece of data samlped? greetings, MatthiasArticle: 69056
Hans, I would call that an output, or a broken input. Austin Hans Maier wrote: > Does a CPLD Input source current ? When I measure the voltage > at my CPLD input pin, it is somewhere in the 3V range. When I connect > it to ground, it sources about 50 mA. Is that normal ? I thought an > input should not behave like this ..!? > >Article: 69057
"Matthias Müller" <spam*mur@iis.fhg.de> wrote >Hello, >I have a problem with peforming master dma with the xilinx pcix core. >I'm writing into the systemy memory with 4KB blocks and I use a >4KB-BlockRAM in the FPGA as prefetchable datasource. The >BlockRAMs have a read latency of one clock cycle. If I increment the >internal source-address-counter with m_data_nxt, then the first piece of > >data comes out one cycle to late. The Design Guide says that the first >piece of data must be presented to the core with assertion of m_attr_vld > >and the subsequent pieces with m_data_nxt. I thought that this mechanism > >can compensate the read latency of the BlockRAMs. But it looks like the >first piece of data is NOT sampled with assertion of m_attr_vld. Who >knows about >the problem, when is the first piece of data samlped? >greetings, >Matthias Hello, when m_attr_vld is asserted, you have to provide the transfer attributes on the M_DATA_IN bus. In the same cycle, read the first piece of data into the output register of the BlockRAM and increment your address pointer. The first piece of data is sampled by the core at the first occurence of M_DATA_NXT. Use this event to transfer the second piece of data to the BlockRAM register and increment your address pointer... Hope this helps, MichaelArticle: 69058
Hi Michael, I'm definitely interested. A link to the paper would be very much appreciated. Cheers, DwayneArticle: 69059
Hi Allan, I'd be interested in having a look at the parts. Could you kindly dig up the numbers? Thanks kindly, Dwayne Surdu-MillerArticle: 69060
Hi,
I have some problems when using two clock domains in my design.
My main clock works at a frequency of 60 Mhz. The clock port is routed
to the input port of the internal DLL which provides two clock
sources, one of the same frequency (60 Mhz) and the other of 20Mhz.
There is a rising edge detector FF excited with 20 Mhz clock
re_detect:
block is
signal aux : std_logic;
begin
process( rst, clk_20 )
begin
if ( rst = '1' ) then
aux <= '0';
elsif ( clk_20 = '1' and clk_20'event ) then
aux <= input;
end if;
end process;
re_edge <= not(aux) and input;
Note: the input is synchronized to avoid glitches and metastability.
Then I have another FF whose set and reset are separate conditions
that is
excited with 60 Mhz clock.
process ( rst, clk_60 )
begin
if ( rst = '1' ) then
out <= '0';
elsif ( clk_60'event and clk = '1' ) then
if ( input = '1' ) then
out <= '1';
end if;
if ( re_edge = '1' ) then
out <= '0';
end if;
end if;
end process;
I have simulated functionally the design with Modelsim 5.6f and I see
that "out" signal doesn´t become low when "re_edge" is active. Note
that the if clauses are writen in such way so that the reset condition
has the biggest priority.
This might be because the "re_edge" signal is a 0 ps wide pulse, I
mean is asserted and dessaserted in the same simulation step and in
the same time with the rising edge of the clock signal.
I don't know certainly why, but I believe that it can be because I use
the DLL. I have created the same design using a clock divider instead
of a DLL and it works but there are several differences in the
functional simulation:
- "re_edge" signal is a clk_20 period wide signal instead of a glitch
- "aux" signal is asserted 1 clk_20 period later than the "input"
signal
Anybody any suggestion?
Thanks in advance,
Arkaitz
-------------------------------
Ikerlan
Electronics Area
Pº J. M. Arizmendiarrieta, 2
20500 Arrasate (Gipuzkoa)
-------------------------------
Article: 69061"Bruno Cardeira" <bmscc@netcabo.pt> wrote in message news:<407086f8$0$3532$a729d347@news.telepac.pt>... > Hello, > does anyone know if it is possible to connect several Xilinx XC9536 CPLD > output pins in a Wired-OR configuration? > If possible, how can I do it in VHDL? > > Thanks > Best Regards > Bruno OK. Lots of responses already to your problem. A small remark regarding the use of strong pullups or pulldown resistors: they are of course required if you need speed and may not integrate more complex logic, but are power hungry. Obvious ! However, I had a problem like that one day, and solved it differently. If the output pins you want to wire-or may be driven by a sequential state machine AND no contention can occur (by definition of the problem for instance), it is not difficult to build a state machine that drives the wire-or bus 1 or more clocks at the value required, and finally ends up by driving the bus to its rest (idle) state for 1 more clock (even maybe half a clock). Then, idle state is kept by weak pullups or pulldowns or keeper circuits if any.Article: 69062
Hey check out www.stretchinc.com SteveArticle: 69063
Hi, I'm currently auctioning a PCI prototyping board on eBay. For those of you doing PCI development, it may be of interest: http://tinyurl.com/2n2xa It's been sitting (unused) in my closet since 1999. After I sell this one, I'll be selling one or two more. I'm using the proceeds to fund a hobby project. Thanks for reading, Eric CrabillArticle: 69064
Thank you Mike, thank you Rene
Kind regards,
Florian Student
Article: 69065Hi, Michael already answered the question, but I thought I'd follow up anyway. > If I increment the internal source-address-counter with > m_data_nxt, then the first piece of data comes out one > cycle to late. The Design Guide says that the first > piece of data must be presented to the core with > assertion of m_attr_vld and the subsequent pieces > with m_data_nxt. That is correct. > I thought that this mechanism can compensate the read > latency of the BlockRAMs. It works with the BlockRAMS. The m_data_nxt signal is telling your use application, "You need to provide the next piece of data during the next clock cycle." So, you could use m_data_nxt to control the BlockRAM, which has a latency of one cycle -- and it will work properly. > But it looks like the first piece of data is NOT > sampled with assertion of m_attr_vld. Who knows about > the problem, when is the first piece of data samlped? You either need to arrange your design so that the first piece of data is always available when the transfer starts (data ready, sitting at BlockRAM output) or you need to "prefetch" the first piece using your own m_req as a start flag, or one of the m_add* signals from the core (which will assert in response to your assertion of m_req). You are not told the specific cycle the data is sampled. You should design to the directions in the design guide. This way, your design will not break if we ever have to modify the specific cycle that the data is sampled. The reason you're not told exactly when is that it varies depending on what bus mode you're in, and it's a function of the initiator state machine -- something that is not "observable" by the user application. Thanks, EricArticle: 69066
Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote: : Thanks for all the replys guys, I should have stipulated : that the frequency has got to be adjustable on the fly. : > LTC6900, LTC6903 from linear technology : This looks like my best bet, apart from.... : > > Can be sourced from distributor in a couple of days. : I can get them from the LTC web site, does anyone have : any experience of their delivery times? The delivery time is very short! -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 69067
Marius Vollmer <mvo@zagadka.de> wrote: : Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes: : > lbroto <lbroto_ARONDBAS_@free.fr> wrote: : > : > : I'm lookink for a quartus web edition for Linux. : > : > [...] : > : > I'd wish they would use wine and talk to Codeweavers/WineX about : > maintanance. Their software mostly works already with wine used as an : > emulator... : Does anyone have experience with running the Quartus Web Edition on : Linux? : We are considering making a hobbyist FPGA board, and we are : considering both Xilinx and Altera, but the design software will need : to be gratis and run on GNU/Linux. I have the Xilinx WebPACK running : on GNU/Linux using Wine (command line only but that's enough), but I : have found no information yet on doing the same with Quartus. : I think I'll just try to get it running... There are some hack's needed. They are not clean and were not applied by the wine source code mantainer. No clean solution was found yet. Another problem is some slight problem with Wine's MSVCRT implementation. When you managed to get Quartus going and run a project, it will go a long way, but then it finds data corruption and aborts. Running with native MSVCRT doesn't show that problem, but neither Xilinx nor Quartus distributes the redistributable MSVCRT with there package. As Altera uses FlexLM for license control, it is harder to get going the Xilinx. Try first to set up the license control, even running the Quartus license with FlexLM for Linux and pointing the Wine Quartus session to that license server will work ( even tunnelling via ssh). Another thing to consider is that the Altera Quartus license is only valid for half an year. While it looks like this will not change, no one will guarantee. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 69068
>I would call that an output, or a broken input. Yes, this is driving me mad .... It is configured as input, and it WORKS as input. If I pull it down to ground, the logic detects the low level. Could it still be broken ? How could I break an input ? There are only 5V on the board ....And the rest of the chip works just fine ....Article: 69069
Steve,
I'm sure Jeff and his cohorts appreciate the plug... The
website says far more than they were willing to tell us last
week. BTW, we missed you at FCCM again this year.
Steve Casselman wrote:
> Hey check out www.stretchinc.com
>
> Steve
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 69070Hans Maier wrote: >>I would call that an output, or a broken input. > > > Yes, this is driving me mad .... > > It is configured as input, and it WORKS as input. If I > pull it down to ground, the logic detects the low level. > > Could it still be broken ? How could I break an input ? > There are only 5V on the board ....And the rest of the > chip works just fine .... You could clarify if your 50mA meant 50 microamps, or 50 milliamps. Many times I've seen the greek 'u' in uA morph into mA on the internet as it jumps fonts.... 50uA could be a normal pin pullup, 50mA sounds like the PFET is on. A simple test is to try moving the function to another pin, or simply swap the pin allocates (two same-class pins). If the problem stays with the pin, it's likely to be chip related, if it moves with the function, suspect something in your code... -jgArticle: 69071
Ray Andraka wrote: > Steve, > > I'm sure Jeff and his cohorts appreciate the plug... The > website says far more than they were willing to tell us last > week. BTW, we missed you at FCCM again this year. > > Steve Casselman wrote: > > >>Hey check out www.stretchinc.com >> >>Steve Looks interesting.. Does the EEMBC benchmark mean they have real silicon ? On all other cores, I see (ASM OPT) gives quite a gain over (C OPT). Thus on this core, could one expect (ASM + Floorplan OPT) to also give gains ? -jgArticle: 69072
Jon, http://news.bbc.co.uk/1/hi/england/3549809.stm http://news.bbc.co.uk/1/hi/uk/3315197.stm Cheers, Syms.Article: 69073
Jim Granville wrote: > Looks interesting.. > Does the EEMBC benchmark mean they have real silicon ? > On all other cores, I see (ASM OPT) gives quite a gain over (C OPT). > > Thus on this core, could one expect (ASM + Floorplan OPT) to > also give gains ? There is more info here : http://www.eet.com/semi/news/showArticle.jhtml;jsessionid=O2NAUQOWPWFSWQSNDBCCKHQ?articleID=19200029 Talks of dual port memory, 100MHz logic fabric speeds, and this comment was the most revealing : "When the compiler extracts and creates a custom pipeline, it also works out the latency, so it knows how large a delay slot to insert in the code stream for that operation." So the PR talk of a 'single opcode' was only part of the story - These HW assisted single opcodes can be quite slow (relative to other single opcodes, but of course, still much faster than SW wheel spinning ) DMA reload in two halves in 80-100us also sounded good... No sign yet of numbers showing just how big the ProgLogicFabric is ? -jgArticle: 69074
Mikhail, If you mean can you still program the FPGAs over the JTAG then yes, it's OK. I've done it before with a Virtex II and an Intel StrongArm processor. IIRC you need a boundary scan discription file for the 3rd party IC to keep Impact happy. Sorry I can't be more specific, this work was at a previous company. Cheers, Syms. "MM" <mbmsv@yahoo.com> wrote in message news:c6j4mp$cb5n8$1@ID-204311.news.uni-berlin.de... > Does anyone know if it is OK to have 3rd party devices in one JTAG chain > with Xilinx FPGAs and CPLDs? The Xilinx devices I am using are XC2VP4 and > XC9572XL... > > > Thanks, > /Mikhail > > -- > To reply directly: > matusov at square peg ca > (join the domain name in one word and add a dot before "ca") > >
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z