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John, Nope. The technology, programs, and results are proprietary. I have said all that I can say. It works, it makes money. It is a technology that is protected (by patents). Austin John Providenza wrote: > Any chance Peter or Austin could post some non-proprietary information > on the typical number of tests and average test time for a "generic" > FPGA versus one for the EasyPath with a known FPGA bit pattern? As > the devices get more complex, does test time go up linearly? What > does test time cost per second? How expensive are the testers? > Any other tidbits to enlighten/amuse us? > > Device testing is something a lot of people are never exposed to, so > this could be an interesting education. > > EasyPath sounds like a cute idea - I hope it works well for Xilinx. > > John ProvidenzaArticle: 69501
BP, I think Jim answered this already. No, I don't think we are going back to the ASIC model any time soon, but there is a class (a large class) of applications for devices that get programmed to do one thing, and are extremely unlikely to require an upgrade. Even if the device does require an upgrade, I think folks on this thread have already noted that the probability for failure to load for a small number of changes is pretty near 0 (just based on the number of good paths and bits vs the one or two bad bits). The really remarkable thing about EasyPath (already has happened) is when the customer calls up two months later, and says "I made this mistake, and I need to change the contents of a LUT and a path...." and we can say, "send us the new bitstream" and let them know exactly what kind of chances there are that all the parts already in the field have of not being able to work with the new pattern, and change to testign for the new pattern for their next delivered lot. Saved some butts, that is for sure! Try that with an ASIC. Austin BrakePiston wrote: > Austin, > > so what you are saying is that you can build a chip to potentially > suit any design you like, but in fact customers are more interested in > getting their own design to work and don't really care about the other > possibilites. > > Does that mean that in the future, if everyone adopts this strategy, > we will be back to having to swap chips at every upgrade? I thought > one of the (many) wonderful advantages of FPGAs is their prolonged > lifetime due to upgrade potential..... > > Effectively, if everyone does go down that route, Xilinx, Altera and > Co. will become ASIC producers!! Very good ones, don't get me wrong, > with time and money savings for everyone, but..... > > Maybe I'm just getting a bit nostalgic...... > > > > On Mon, 10 May 2004 07:58:30 -0700, Austin Lesea <austin@xilinx.com> > wrote: > > >>ACM, >> >>Oh, that was really mature. >> >>Did you know that we need to start new wafers to supply Easypath? (can >>not rely on having enough die with one or two memory cells that are at >>fault to satisfy demand). >> >>Did you know that the cost savings are mostly from testing the chip for >>what the customer uses it for, rather than for testing it for what >>everyone of our 250 thousand seats of software might design it to do? >> >>Oh, and what about all those laser trimmed redundant chips out there, >>are those also scrap? After all, every one of those has a proven >>hardware faults! >> >>(PS: thanks for bringing this up again, and giving me the opportunity >>to reply -- it is so much fun to see the subject line of your posting >>promoted by someone else besides me) >> >>Austin >> >>acm wrote: >> >>>Easypath = EasyScrap... >>> >>>Hey, buy our excess scrapped inventory!!!! >>> > >Article: 69502
O.K. that site requires registration Here's a clip from the datasheet: 14.5.4 YUV to RGB Conversion In the ICP, YUV to RGB conversion is done by sequentially processing triplets of Y, U, and V pixel data to convert the pixels to an internal YUV 4:4:4 format and applying the YUV to RGB conversion algorithm on the YUV 4:4:4 pixels. The results of this conversion normally go to the PCI bus but can also go back to SDRAM. YUV to RGB conversion has two steps. First the Y, U and a V pixel data are used to generate an RGB pixel at the output location. When the Y,U, and V pixels are ready, YUV to RGB conversion is performed using the following algorithms: R = Y + 1.375(V)= Y + (1 + 3/8)(V) G = Y - 0.34375(U) - 0.703125(V) = Y - (11/32)(U) - (45/64)(V) B = Y + 1.734375(U) = Y + (1 + 47/64)(U) In CCIR601, the U and V values are offset by +128 by inverting the most significant bit of the 8-bit byte. This is the way the U and V values are stored in SDRAM. The above algorithms assume that the U and V values are converted back to normal signed two's complement values by inverting the MSB before being used. ... The values used are not exactly those specified in the CCIR601 specification, but they seem to work quite well and the constants make for small multipliers. Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote in message news:<c7p2e5$h8$1@news.epidc.co.kr>... > On a sunny day (10 May 2004 15:14:15 -0700) it happened gabor@alacron.com > (Gabor Szakacs) wrote in <8a436ba2.0405101414.243d7b94@posting.google.com>: > > >Sorry I posted a link to the glossy sales literature. > >The data sheet is at: > > > >http://www.support.trimedia.philips.com/trimedia/Download/pnx1300-CQS.pdf > > > >This has the algoriths in chapter 14 > panteltje:~/download/html# wget http://www.support.trimedia.philips.com/trimedia/Download/pnx1300-CQS.pdf > --01:13:57-- http://www.support.trimedia.philips.com/trimedia/Download/pnx1300-CQS.pdf > => `pnx1300-CQS.pdf' > Connecting to www.support.trimedia.philips.com:80... connected! > HTTP request sent, awaiting response... 401 Authorization Required > Connecting to www.support.trimedia.philips.com:80... connected! > HTTP request sent, awaiting response... 401 Authorization Required > Authorization failed. > JPArticle: 69503
On 11 May 2004 19:10:35 +0200, Petter Gustad <newsmailcomp6@gustad.com> wrote: >Jim Lewis <Jim@SynthWorks.com> writes: > >> acm wrote: >> > Easypath = EasyScrap... >> > Hey, buy our excess scrapped inventory!!!! >> > >> What is wrong with taking lemons and making Lemonade? > >Drive manufactures have been doing this for years. They just maintain >a defect sector list on the drive. > >Petter Yup. Used to be written on the label with a pen. - BrianArticle: 69504
How do I disable bus-hold on an XC9500XL device, using Foundation F4.2i Project Manager? The answer database talks about a setting in Project Navigator (whatever that is) but I can't find anything in Project Manager. I'm happy to hack the Jedec file, if it comes to that! Richard. http://www.rtrussell.co.uk/ To reply by email change 'news' to my forename.Article: 69505
I have been doing some investigation into blob analysis algorithms and would like to know if there are any designs that have been renedered into FPGAs. Thanks for your help. Brad Smallridge AIVISION.COM 415-661-8068Article: 69506
>The really remarkable thing about EasyPath (already has happened) is >when the customer calls up two months later, and says "I made this >mistake, and I need to change the contents of a LUT and a path...." and >we can say, "send us the new bitstream" and let them know exactly what >kind of chances there are that all the parts already in the field have >of not being able to work with the new pattern, and change to testign >for the new pattern for their next delivered lot. Exactly! So more and more people will come to you instead of going to ASIC manufacturers, provided costs/time/characteristic are sufficiently good. So that divides the FPGA industry into 2: one half carries on like we know it,i.e. reprogrammable logic. The other half attacks ASIC on it own territory, i.e. a certain type of devices which are quite happy not to change over time. Either way, FPGAs will be conquering the world!! Now, on a more serious note, I seem to remember predictions by Makamoto and its famous pendolous that the market is moving towards reconfigurable hardware anyway. So here is my question: why did Xilinx think of Easypath? The market is coming its way anyway...... A few possibilities: - Virtex II Pro wasn't selling enough, so an alternative was needed. - Industry scope redefinition: Xilinx saw quite a lot of business available on this area, and, because at the end of the day we're out here to make money, went down that route, even if it meant changing a few things here and there - Xilinx had a bunch of slightly defective Virtex II Pros. Instead of throwing them away, started Easypath. It then proved a success, so much so that potentially perfect devices are sold without guarantee that they would work. Now, option 1, I would discard. Option 2: well, I seem to understand Xilinx is on the up as of lately, overtaking all its competitors and still pulling away. Why go down that route, considering that in the next 3-5 years the FPGA market is going to grow to levels never seen before? Option 3: Seems to me the most reasonable. Views? Regards,Article: 69507
"BrakePiston" <brakepiston@REMOVEyahoo.co.uk> wrote in message news:rqj4a0d9qlnnc4r5kt4v23i627bfjdcm2p@4ax.com... > A few possibilities: > > - Virtex II Pro wasn't selling enough, so an alternative was needed. > - Industry scope redefinition: Xilinx saw quite a lot of business > available on this area, and, because at the end of the day we're out > here to make money, went down that route, even if it meant changing a > few things here and there > - Xilinx had a bunch of slightly defective Virtex II Pros. Instead of > throwing them away, started Easypath. It then proved a success, so > much so that potentially perfect devices are sold without guarantee > that they would work. How about: - Xilinx found they could deliver previously untested parts at a significantly lower cost while maintaining profit margins just by performing custom testing with 100% coverage of a single design rather than 100% coverage of every teeny tiny little piece of every corner of the device. The fact that it helps stave off a change to ASICs is a bonus. If an FPGA will only have one design, the generic 100% testing of the device is effectively a waste of effort with more capital equipment and manufacturing capacity devoted to the lengthy process than is necessary. The tradeoff comes to when the cost of test development and the part management outweighs this "waste."Article: 69508
hi, is there any Virtex-II Pro (with only one PPC core embedded, XC2VP4-5FG456C), the clock, config ROM, JTAG (maybe also USB) and some RAM board out there? cause i've seen some cards from Memec (there's one at about 400dollars with EDK and 200 without it), but they dont have any RAM, and other boards have too much peripheals that i dont need and then they have like 20 user I/O pins available, cause they have keyboard, display, leds, parallel port, A/D, D/A, video, and a lot of other stuff. If i wanted those peripheals later i guess i'd get a daughter board, but in the beggining i'd like as much I/O as possible another one is the one for gameboy (i dont know it's name) it seems to have everything i want, just the FPGA is not a Virtex-II Pro any pointers will be appreciatedArticle: 69509
Hi Fabio, I'd recommend checking with Lattice and asking whether the oldest versions of their logic design software support ISP1032 and ISP1032E. Someone there should have a legacy software package that will help you. Otherwise, you're kinda stuck. Synario was bought by Xilinx, I believe. I doubt that they'll be able to help you out. ( but one never knows until one explores a little :-) ) If you need only view the old Synario ECS schematics, I believe the latest Lattice design software will at least let you do that much. Best regards, Dwayne Surdu-MillerArticle: 69510
"SneakerNet" <nospam@nospam.org> wrote in message news:<g7goc.3675$XI4.141034@news.xtra.co.nz>... > Hello > > I'm looking at interfacing my compact flash card with my Cyclone FPGA. What > I want is some help/advice on how to start. Is there a website that has > details on this? > > Thanks in advance > Regards Been there, done that ;^) Here are some resources I found useful: http://www.compactflash.org/cfspc2_0.pdf http://www.xilinx.com/bvdocs/appnotes/xapp398.pdf ftp://ftp.xilinx.com/pub/applications/refdes/xapp398.zip http://www.xilinx.com/products/cpldsolutions/module/compact_flash.pps http://www.esconline.com/db_area/01chicago/400.pdf http://www.esconline.com/db_area/98fall/pdf/549.pdf http://e-www.motorola.com/files/32bit/doc/app_note/AN2293.pdf http://e-www.motorola.com/files/32bit/doc/app_note/AN2647.pdf http://www.circuitcellar.com/echips-pdfs/0201/c0201mspdf.pdf http://www.mcselec.com/an_123.htm http://www.sandisk.com/pdf/oem/AppNote80C51FlashATAv1.0.pdf http://www.sandisk.com/pdf/oem/AppNoteCFHostv1.0.pdf http://www.armanet.com/Pages/engineeringright.html#compactflash http://docs-pdf.sun.com/802-6321/802-6321.pdf http://www.oxsemi.com/products/an/oxan17.pdf http://www.oxsemi.com/products/an/oxan18.pdf http://pcmcia-cs.sourceforge.net/ http://www.latticesemi.com/lit/docs/appnotes/cpld/an8005.pdf http://www.latticesemi.com/account/_download.cfm?AMID=2929 http://courses.ece.uiuc.edu/ece311/lectures/ http://www.analog.com/library/analogDialogue/archives/37-01/compact_flash.html http://www.analog.com/library/analogDialogue/cf.html Cheers! -- PabloBleyerKocik/"I wonder what Microsoft will do now that pbleyer2004 / they no longer have Gary Kildall to lead @embedded.cl/ the way for them?" -- Sol LibesArticle: 69511
> With two clocks and two write ports!? Ok, maybe not that particular case, but most other configurations of dual-port RAM can be infered. In Verilog at least, isn't this a problem with the language rather than the FPGA tools (i.e. you can't write to the same variable from two different processes)? > Open-source doesn't *have* to mean no-cost... Sure. I was more refering to that fact that due to the quality & size of some open source/free software projects, the bar has been raised significantly. Cheers, JonBArticle: 69512
Hello Dwayne, first I want to thank you for your answer. You wrote: >I'd recommend checking with Lattice and asking whether the oldest >versions of their logic design software support ISP1032 and ISP1032E. >Someone there should have a legacy software package that will help you. The situation is the following: about 5 years ago a my ex-colleague started a project with Synario 3.0 and then discontinued it. Now I have to resume his work and improve it. I have searched in our software archive but Synario 3.0 cannot be found. I only found some old floppy disk of the "Lattice IspPDS 2.71 software" that is unuseful to me (moreover, the hardware key license does not work properly...). I looked on internet and downloaded Synario 5.1 : it opens my .syn files but it says that it can't proceed correctly because the project was saved with a ISP1032-60 , and that version of software supports only ISP1032E series. This should NOT be a problem, because in our warehouse we also have a ISP1032-70 device. If I choose the ISP1032-70 device the program starts. Then I can see schematic and ABEL files, BUT when I try to complete che fitting process, a fatal and very strange error occurs: the report says something like: ".....**name_of_the_command_line_invoked** : error code -1 : failed to spawn child process " ??? It is NOT an error about the project : it seems an error regarding some failure in the operating system (I use Windows 98: is it too "recent" for that version of Synario??)... ??? So I downloaded the latest software ISPLever from Lattice site, but it does not support neither 1032 nor 1032E .... :-( It seems that the only solution (assuming that I'm not able to resolve that strange error) is to find Synario 3.0 .... : I'll try to re-contact my ex-colleague. Or.... is there another solution?? Do exist some other tools that can be used? For example, is it possible to use a third part software (and then load the EDIF file in PDS?) ? >[Xilinx] > I doubt that they'll be able to help you out. In fact: in the site there are very few info >If you need only view the old Synario ECS schematics, I believe the >latest Lattice design software will at least let you do that much. Well, as I said above, I can see the schematics, but I have to modify them and to program a board with that old device (I can't migrate to a newer device: the pinout would be incompatible) Thank you again for your support, Fabio -- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzo -*- To reply via email write the correct sum (in letters) in the email addressArticle: 69513
Hi Michael, Thanks, that fixed it! You leave out the LOC in the BMM, and then P&R copies the BMM and adds the LOC in. Just to clarify to anyone else reading, in my build process, I 'added' the BMM file to the top level EDIF file in Navigator. Thanks again and cheers, Syms. "Michael Schöberl" <MSchoeberl@ratnet.stw.uni-erlangen.de> wrote in message news:2geckcF1pjjaU1@uni-berlin.de... > > you need a .bmm file (Block RAM Memory Map) ... it contains the > names of the blockrams... > > If you put this file in the project tree (asigned to the toplevel) then > place&route will create a second .bmm file with the location of the > blockrams ... > > bye, > Michael >Article: 69514
BP, As Pinky says to Brain, "Why Brain, what are we doing tomorrow night?" And Brain's reply: "the same thing we do every night, Pinky, try to take over the world!!!" Austin BrakePiston wrote: >>The really remarkable thing about EasyPath (already has happened) is >>when the customer calls up two months later, and says "I made this >>mistake, and I need to change the contents of a LUT and a path...." and >>we can say, "send us the new bitstream" and let them know exactly what >>kind of chances there are that all the parts already in the field have >>of not being able to work with the new pattern, and change to testign >>for the new pattern for their next delivered lot. > > > Exactly! So more and more people will come to you instead of going to > ASIC manufacturers, provided costs/time/characteristic are > sufficiently good. > > So that divides the FPGA industry into 2: one half carries on like we > know it,i.e. reprogrammable logic. The other half attacks ASIC on it > own territory, i.e. a certain type of devices which are quite happy > not to change over time. > > Either way, FPGAs will be conquering the world!! > > Now, on a more serious note, I seem to remember predictions by > Makamoto and its famous pendolous that the market is moving towards > reconfigurable hardware anyway. > > So here is my question: why did Xilinx think of Easypath? The market > is coming its way anyway...... > > A few possibilities: > > - Virtex II Pro wasn't selling enough, so an alternative was needed. > - Industry scope redefinition: Xilinx saw quite a lot of business > available on this area, and, because at the end of the day we're out > here to make money, went down that route, even if it meant changing a > few things here and there > - Xilinx had a bunch of slightly defective Virtex II Pros. Instead of > throwing them away, started Easypath. It then proved a success, so > much so that potentially perfect devices are sold without guarantee > that they would work. > > Now, option 1, I would discard. > Option 2: well, I seem to understand Xilinx is on the up as of lately, > overtaking all its competitors and still pulling away. Why go down > that route, considering that in the next 3-5 years the FPGA market is > going to grow to levels never seen before? > Option 3: Seems to me the most reasonable. > > Views? > > Regards, > > >Article: 69515
Hei, i try to configure an APEX20K400E with the passive parallel asynchronous configuration scheme but at a certain point in the configuration phase the FPGA signals an error by pulling nSTATUS low. To locate the error i counted the number of transfered bytes and i saw the following. For the same configuration file (.rbf) the FPGA signals every time the error at a certain point. That point varies from configuration to configuration file. For one file it stops always after 4000 bytes, for another after 170.000 bytes and for a third one after 20.000. I tried it as well with two different FPGAs from the same type. The result is the same. The timing and the signal levels i've checked according to the Altera documentation. Cheers, Torsten PS: Using Quartus 3.0 SP2 to create a raw binary file (.rbf)Article: 69516
Fabio G. wrote: > Hello Dwayne, > first I want to thank you for your answer. > > You wrote: > > >>I'd recommend checking with Lattice and asking whether the oldest >>versions of their logic design software support ISP1032 and ISP1032E. >>Someone there should have a legacy software package that will help you. > > > The situation is the following: about 5 years ago a my ex-colleague > started a project with Synario 3.0 and then discontinued it. > Now I have to resume his work and improve it. > I have searched in our software archive but Synario 3.0 cannot be found. > I only found some old floppy disk of the "Lattice IspPDS 2.71 software" > that is unuseful to me (moreover, the hardware key license does not work > properly...). > I looked on internet and downloaded Synario 5.1 : it opens my .syn files > but it says that it can't proceed correctly because the project was > saved with a ISP1032-60 , and that version of software supports only > ISP1032E series. This should NOT be a problem, because in our warehouse > we also have a ISP1032-70 device. > If I choose the ISP1032-70 device the program starts. > Then I can see schematic and ABEL files, BUT when I try to complete che > fitting process, a fatal and very strange error occurs: the report says > something like: ".....**name_of_the_command_line_invoked** : error code > -1 : failed to spawn child process " > ??? It is NOT an error about the project : it seems an error regarding > some failure in the operating system (I use Windows 98: is it too > "recent" for that version of Synario??)... ??? > > So I downloaded the latest software ISPLever from Lattice site, but it > does not support neither 1032 nor 1032E .... :-( > > It seems that the only solution (assuming that I'm not able to resolve > that strange error) is to find Synario 3.0 .... : I'll try to re-contact > my ex-colleague. > > Or.... is there another solution?? If you can load, and get partway along the tool flow, that is some progress. Dig about and see what files have been produced - the engine of Synario is ABEL, plus vendor specific fitters. Fitters commonly use BLIF, PLA, or sometimes EDIF files, so try and find the .EXE that is the fitter for your old device. "failed to spawn child process" could simply mean it was unable to find the fitter, and if you can manually launch the fitter, it will work ok. Talk with lattice, they should know what these legacy fitter(s) are called, as well as file and calling methods for command line operation. -jgArticle: 69517
Tom Hawkins wrote: > What can we do to improve open-source EDA? > > Regards, > Tom > For me, and I guess for a lot of people in this industry, contribute to open source could be a legal minefield: - In my job contract, it stated my employer own the copyright of designs I done. So officially I cannot post any IP design/source code to public. - Patent issues. Some of my knowledge might relate to patented products. Release of such information could mean I could get sued. And of course, usually I am too tired after work anyway ;-) JoeArticle: 69518
Leave them float. "Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote in message news:409ff3eb$1@news.vsnet.ch... > HI all, > > I am designing on a FG256 package. > > I have a large part of unused IOs. > Is that better to fix the unused IOS to VCCO or to GND or can I let all > unused IOs float? > > Regards, > Laurent >Article: 69519
Hi, Is anyone aware of a equation decompiler for GAL devices? I'm looking for a program that can take a GAL JEDEC fuse map file and decompile it to its source logic equations. I know this can be done manually but that can be very tedious and error prone. Thanks, SteveArticle: 69520
azcycle wrote: > Hi, > > Is anyone aware of a equation decompiler for GAL devices? I'm looking for a > program that can take a GAL JEDEC fuse map file and decompile it to its > source logic equations. I know this can be done manually but that can be > very tedious and error prone. Google for JED2EQN -jgArticle: 69521
Thanks, I'll check it out. Steve "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:4Dyoc.1606$FN.175397@news02.tsnz.net... > azcycle wrote: > > Hi, > > > > Is anyone aware of a equation decompiler for GAL devices? I'm looking for a > > program that can take a GAL JEDEC fuse map file and decompile it to its > > source logic equations. I know this can be done manually but that can be > > very tedious and error prone. > > Google for JED2EQN > -jg >Article: 69522
Sean Durkin <smd@despammed.com> wrote in message news:<2geoclF1v5s3U1@uni-berlin.de>... ... > Then just make it bigger. :) You probably have some sort of > BRAM-controller in your design... attached to the PLB, OPB, or > OCM-controller. Usually the smallest size available is 8kB, which is too > little in most cases, especially when you need a bunch of extra libs. > > To get more instruction-side memory, all you have to to is change the > address range of the BRAM-controller, EDK takes care of the rest. The > size has to be a power of 2 though (8kb, 16kb, 32kb, 64kb...), and you > have to make sure you don't use more BRAMs than you have available in > your FPGA.. For example, in an xc2vp7 there are 44 BRAMs of 2kb each, so > the biggest memory size for your PPC is 64kb. > > For example: a base address of 0xFFFF0000 and a high address of > 0xFFFFFFFF for your BRAM-controller wuld give you 64kb of memory for > your program. > > Note that 0xFFFFFFFC must always be included in the address space, since > that is the address the PPC starts program execution from. > > cu, > Sean Thanks, Sean. But, the base address and length seem to be specified multiple places. The base address shows up once in the linker script and the length shows up twice (!) in the linker script. Also, the base is in the .pbd file as well. Is there one centralized place to set these parameters?Article: 69523
Hi Iwo, Iwo Mergler wrote: > I'm looking for a CF FPGA prototyping card. Do you know > of such a beast? > > The closest I could find so far is the Wildcard, combined > with a CF to PCMCIA adapter. I don't know of any other cards, but some second hand comments about the Wildcard: Someone I spoke to recently was complaining bitterly that the WildCard's communication interface between the FPGA and the PCMCIA bus is extremely narrow and slow, basically he was forced to do single-byte programmed reads/writes across that interface. Yuck. So, it seems to make the idea of using the Wildcard as a computational accelerator/coprocessor pretty useless - you just re-invent the bus-bound architecture... It may just be a problem with the host drivers, rather than the WildCard architecture itself, I'm not sure. If anyone from Annapolis is reading this it would be interesting to get clarification. Regards, JohnArticle: 69524
Hi, In my design, there is a flash memory chip connecting to fpga chip, I want to program the flash memory through the JTAG port on the FPGA, where can I find some introduction? Thanks a lot! Regards
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