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that's sound you in trouble, a design with no room for pipelines? one thing i want to point out:(Ray mentioned it before?) you need to do manual placement so that the flipflop can sit next to the blockram, auto placement some time failed to do that.Article: 69551
Hi, When using the DDR functionality, is it the user's responsibility to provide the phase-shifted clocks or does the above mentioned primitive do this for me? The documentation is not very clear. Although using a DLL to phase-shift is the best practice, can I get by just using an inverter between the two clocks? If so, does the Virtex-II IOB provide a "free" inverter (gets absorbed in the IOB)? Comments? AnilArticle: 69552
Chris Cheung wrote: > Leave them float. > > > "Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote > in message news:409ff3eb$1@news.vsnet.ch... > >>HI all, >> >>I am designing on a FG256 package. >> >>I have a large part of unused IOs. >>Is that better to fix the unused IOS to VCCO or to GND or can I let all >>unused IOs float? >> >>Regards, >>Laurent >> > > > I think leaving them float is not so good idea. Since I am using FG256, the ball will be not able for debug pin. If I route the pcb ground to the unused pin I can let the unused FPGA IOs Float or drive the unused FPGA IOs as an output '0' -> to reduce ground bouncing ! Laurent www.amontec.com ------------ And now a word from our sponsor ------------------ Do your users want the best web-email gateway? Don't let your customers drift off to free webmail services install your own web gateway! -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----Article: 69553
yup. Autoplace virtually never puts the flip-flop adjacent
to the block RAM. Unless it is in a critical feedback loop,
you should be able to pipeline.
thangkho wrote:
> that's sound you in trouble, a design with no room for
> pipelines?
>
> one thing i want to point out:(Ray mentioned it before?)
> you need to do manual placement so that the flipflop can
> sit next to the blockram, auto placement some time failed
> to do that.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 69554"rat" <rattt@col.edu.cn> wrote in message news:c7ujmp$1phn$1@mail.cn99.com... > Hi, > In my design, there is a flash memory chip connecting to fpga chip, I want > to program the flash memory through the JTAG port on the FPGA, where can I > find some introduction? The basic idea is that you put the FPGA in EXTEST and take control all the IOs via the JTAG port, so you have complete access to the flash memory. HTH, Jim jimwu88NOOOSPAM@yahoo.com http://www.geocities.com/jimwu88/chipsArticle: 69555
Amontec Team, Laurent Gauch wrote: > If I route the pcb ground to the unused pin I can let the unused FPGA > IOs Float or drive the unused FPGA IOs as an output '0' -> to reduce > ground bouncing ! There was a longer discussion of this very subject few month ago. Peter or Austin explained it in a longer post, you should find it in google, looking for "virtual grounds"Article: 69556
Jim Granville <no.spam@designtools.co.nz> ha scritto: >> - Fit design OK > >but presumably there is no .JED file at this stage ? Yes, that is the problem :-( Before answering to your message, I would like to update you about the current situation: in the afternoon I've made some progress. Assumed that SYNDPM of Synario 3.0 does not work properly, I tried to use the SYNDPM file that I found in a directory of the recent ISPLever 4.0 . This did not give benefits (device not supported, missing DLL, ecc...). So I started to read some PDF documentation about Synario: I realized that the design flow chain can be as follows: - use Synario to make SCH, ABL files, ecc. - use Synario to perform some steps of synthetization process (until the Pre-fit step: you get the .tt2 file) - import the .tt2 file in IspPDS+ software - check pinout assigment - compile --> obtatin JEDEC file With this sequece it *seems* that the synthesis is ok: I tried to make a new very simple design from scratch and it worked fine. I'm still having some troubles in importing the old design but these troubles *should* be overcomed. Now your message: >-i pldhcc.tt2 -> Input file is PLA format pldhcc.tt2 ( your compiled >design ) Right >-of verilog -> output format This is the output format used for post-synthesis simulation? I expected that output file was also the .jed file, right? >compiling/reducing to boolean eqns OK, you just need to get the >fitter to co-operate :) >It is the right version fitter ? Yes, it is: it is the default fitter installed with the package > fit15xx.exe -h2 gives a full help list I tried /? /h -h ... but nothing.... >if theirs does not give help from blank command line, you could >trawl the .EXE in a file viewer >- eg to check your SYNDPM version >is correct for your device, verify you can find target >ispLSI1032E-70LJ84 inside the .EXE Good idea, I did not think to that! ;-) >move your .PLA to the fitter/fitlib dir, and try simpler command lines. Good suggestion: I'll try it Let me ask you another question: If I would want to syinthetize a project using VHDL, which third party software could I use? Something like Leonardo Spectrum, for example? (it creates an EDIF file that is then imported from IspPDS+) Just two last things to note: 1) In 1998 another person had my same problem! : http://www.fpga-faq.com/archives/09650.html#9663 ...but nobody answered to his message. I wrote to that person but he could not be able to help me. 2) This morning I wrote to Lattice, and this evening they aswered asking futher information and giving a first suggestion: "Fabio, The only thing I can suggest is to uninstall and reinstall the software. Somehow the ini files for the doftware might be pointing to another software. " ...not big helpful.... I'll try to reinstall... who knows what will happen.... ;-) Thank you again, Jim, for your useful support. Regards, Fabio -- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzoArticle: 69557
Fabio G. wrote: <snip> > - use Synario to make SCH, ABL files, ecc. > - use Synario to perform some steps of synthetization process (until the > Pre-fit step: you get the .tt2 file) > - import the .tt2 file in IspPDS+ software > - check pinout assigment > - compile --> obtatin JEDEC file > > With this sequece it *seems* that the synthesis is ok: I tried to make a > new very simple design from scratch and it worked fine. This was for your needed ispLSI1032E-70LJ84 - or a newer device/fitter ? <snip> >>-of verilog -> output format > > > This is the output format used for post-synthesis simulation? > I expected that output file was also the .jed file, right? oops, yes, I forgot to mention that implicit one :) >> fit15xx.exe -h2 gives a full help list > > > I tried /? /h -h ... but nothing.... Don't you love Sw that does this! :( Part of it is 'muddled security thinking', and I know Synario used encryption that caused them many problems. Still, a _fitter_ is not something to be paranoid about, as the target devices make great dongles, surely ? > > Let me ask you another question: If I would want to syinthetize a > project using VHDL, which third party software could I use? > Something like Leonardo Spectrum, for example? (it creates an EDIF file > that is then imported from IspPDS+) I think lattice offer a VHDL flow, but for 32 MC CPLDs I'd suggest you stick with ABEL ( Xilinx still offer that ) ABEL (& CUPL) allows creation of test vectors in the JED file. -jgArticle: 69558
Wut the heck are you talking about? On Thu, 13 May 2004, thangkho wrote: > that's sound you in trouble, a design with no room for pipelines? > > one thing i want to point out:(Ray mentioned it before?) you need to do > manual placement so that the flipflop can sit next to the blockram, auto > placement some time failed to do that. >Article: 69559
"rat" <rattt@col.edu.cn> wrote in message news:<c7ujmp$1phn$1@mail.cn99.com>... > Hi, > In my design, there is a flash memory chip connecting to fpga chip, I want > to program the flash memory through the JTAG port on the FPGA, where can I > find some introduction? I don't think it's possible to do this. The FPGA JTAG ports are dedicated to boundary scan, and in the case of CPLDs, are used for device programming. You can't access the JTAG controller directly in FPGA logic. However, you could implement your own JTAG TAP controller in the FPGA and wire that to the flash controller, and bring your JTAG signals out on regular I/O pins. -aArticle: 69560
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<40a0ebc8$0$25328$cc9e4d1f@news-text.dial.pipex.com>... > "Dave Marsh" <me@privacy.net> wrote in message > news:40a0dd9d$0$15249$fa0fcedb@lovejoy.zen.co.uk... > > I have twenty Xilinx XC9572XL VQFP64. Their sealed package has been open > two > > months, and stored in an office with no temperature/humidity control. Now > I > > want to get these devices soldered in for a pre-production run. > > > > If I put these in without carrying out a baking cycle am I asking for > > trouble? What are the likely effects due to moisture, and what are > people's > > real-life experiences? > > Reflow soldering without baking them (probably 120 C for 24 hours) might > give problems. Hand soldering should be OK: I never have problems, anyway. I'm not so sure about that. I bought a handful of microcontrollers about a year ago and stuffed boards, and all was fine. I never resealed the bag (I don't have the facility) so they sat until I used them a month ago. I handsoldered one prototype and it failed in a particular way. After much gnashing of teeth (I hate shotgunning parts), I removed the micro and replaced it with another from the same bag, which worked. I have since hand-built three more prototypes and I've had a 50% fallout. I guess I should've baked the parts... -aArticle: 69561
The clock to Q of the BRAMs is what it is, and it is longer than the clock to
Q of the flip-flops in the fabric. The best solution is to pipeline the BRAM
outputs by adding a register. For maximum performance, that register should
be placed immediately adjacent to the block RAMs to minimize the routing
delays out of the block RAM. The automatic placement does an exceptionally
poor job at placing pipeline registers on BRAM outputs, so in order to have
them be of much use you have to do a little floorplanning.
Now you mentioned you can't afford to pipeline the design, which I'll trust
you on for the moment. If that is the case, then you'll have to live with the
long clock to Q from the BRAM, although it doesn't mean you also have to live
with the routing delays to the logic you have connected to them, nor
necessarily the propagation delay through that logic. First, look at the
logic connected the BRAM outputs. Is it designed for minimum propagation
delay to the next flip-flop? Is there anything you can do to reduce the
number of LUTs it passes through? Are you using the carry chain (the carry
chain can be expensive in terms of propagation delay)? Next, look at your
timing report. It enumerates how much of the delay between the BRAM and the
flip flop is attributed to logic and how much to routing, and gives you the
delay for each net in the path. You need to reduce those delays by placing
the logic as close to the BRAMs as you can get it. If your design is like
many novice FPGA designs, your signal goes through several LUTs before
reaching a flip-flop. Each LUT has a flip-flop with it, so pipelining comes
for free if you can afford the latency, but I assume you know that. Anyway,
the automatic placer does alright with placing one level of logic (levels of
logic are the number of LUTs the signal passes through between flip-flops),
but when there are two or more levels of logic, the placer does quite poorly,
often placing the LUTs far away from the direct path between the flip-flops.
What you need to do is constrain the placement of the flip flops as well as
all the logic between the flip-flops and the BRAM so that it is kept as close
to the BRAM as practical. An area constraint on that logic will help,
although the ultimate performance will come by hand placing that critical
logic.
Another consideration is that the automatic router in recent versions of ISE
has gotten lazy compared to the router in versions 2 years ago. The current
router no longer gets the shortest route between well placed logic, rather it
stops optimizing each route as soon as the route is under the timing
constraint. The result is you wind up with every route being a critical
route, and in dense high perfomrance designs you get congestion so that the
router can't find a solution that meets timing. Running the router multiple
times in the reentrant mode will sometimes improve the results, but usually
will not achieve the level of performance you can get with a hand route, or in
the case of VirtexI devices what you could achieve with the version 3 sp8
tools. If placement constraints alone don't get your timing to where it needs
to be, you can try doing some hand routing of that circuit using FPGA editor.
At the very least, that will tell you how much performance is possible, and if
the level of performance you seek is possible with your circuit, it may be the
only way to reach it given the current state of the tools without further
changes to your design.
Matthew E Rosenthal wrote:
> Wut the heck are you talking about?
>
> On Thu, 13 May 2004, thangkho wrote:
>
> > that's sound you in trouble, a design with no room for pipelines?
> >
> > one thing i want to point out:(Ray mentioned it before?) you need to do
> > manual placement so that the flipflop can sit next to the blockram, auto
> > placement some time failed to do that.
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 69562> can anybody here tell me how to instantiate an edn module with ise 6? > i tried so, but it didnot work: > You need to define the entity of uart_tx and set it as a black box in your synthesis tool. HTH, Jim jimwu88NOOOSPAM@yahoo.com http://www.geocities.com/jimwu88/chipsArticle: 69563
winston wrote: > Hi, > > I am trying to update a XILINX EDK 3.2 project file to a EDK 6.1 > project file. I tried using the revup32to61 utility that is included; > however, I receive the error message posted below. The PERL file that > this utility is looking for is no where to be found. I have tried > searching both EDK installation disk and the entire hard-disk; howver, > the file is not on either. Thanks in advance. I get the same error, the mentioned script is simply not there. But to avoid that, all you have to do is change the instance names of your components: the instance name and the name of the corresponding core must not be identical. That's what the perl-script would do for you automatically, if it was there.. cu, SeanArticle: 69564
Bassman59a@yahoo.com (Andy Peters) writes: > "rat" <rattt@col.edu.cn> wrote in message news:<c7ujmp$1phn$1@mail.cn99.com>... > > Hi, > > In my design, there is a flash memory chip connecting to fpga chip, I want > > to program the flash memory through the JTAG port on the FPGA, where can I > > find some introduction? > > I don't think it's possible to do this. The FPGA JTAG ports are > dedicated to boundary scan, and in the case of CPLDs, are used for > device programming. You can't access the JTAG controller directly in > FPGA logic. Look at Jim's message. You can control all the IO's on the FPGA through the FPGA. Then you can apply patterns on the pins connected to the flash to program it. In general you can do this with most JTAG devices. I've programmed I2C proms through the JTAG port of on of our ASICs. The tricky part is to generate the JTAG patterns to do the programming. > However, you could implement your own JTAG TAP controller in the FPGA > and wire that to the flash controller, and bring your JTAG signals out > on regular I/O pins. I guess rat might be interested to put the FPGA bitstream into the flash in order to program the FPGA. In this case there is no loaded FPGA on the board. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 69565
Hello, I'm looking for a way to generate somewhat random netlists of upto 25 ALU-like cells. As an illustration of the cells' level of abstraction, please see http://www.doe.carleton.ca/~fma/RCHW/Cell.png. The blue boxes are word-oriented computing/boolean logic. I know that pure random netlists are not realistic, so I'm looking for a more realistic scheme. Related material that I've google so far are: Mentor Graphics's Generator "PartGen": "Generation of Very Large Circuits to Benchmark the Partitioning of FPGAs" J. Pistorius E. Legai M. Minoux ISPD?99 : April 12 - April 14, 1999 "Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations" Justin E. Harlow III & Franc Brglez PartGen assumes fine-grain logic elements, so interconnection statistics may differ from my word-oriented ALU-like elements. In particular, my cells can take alot of inputs, each net representing a multi-bit word. Because PartGen deals with fine-grain, I assume that many more levels of hierarchy are assumed. I haven't yet inquired about whether the program is available, or how quickly one can ramp up on it to generate simple random netlists. I am ploughing through the 2nd reference right now. Can anyone suggest references, approaches, or ideas/considerations for generating a somewhat random netlist at level of abstraction of my cells? I'm not necessarily looking for a program. In fact, it would probably be more convenient to code up the generator myself using matlab, given some guiding constraints. Thanks for any suggestions. Fred -- Fred Ma Dept. of Electronics, Carleton University 1125 Colonel By Drive, Ottawa, Ontario Canada, K1S 5B6Article: 69566
Thanks for your answer Kenneth Should perhaps have mentioned that I am using a flash to store the images in. This is a 1Mb flash. The Ram I use is 2Mb. I have compressed the HW image to 400Kb. So I only have 600Kb left for all my apps( uC Linux, VoIP framework, VoIP app, chipcontroller sw, etc.) So you see it is quite nessesary to have more space. If you find a way to do this could you then plz contact me by mail or my Messenger profile. If you want me to contact you if I figure this out I can contact you. I prefer having my dev contact in my Messenger so plz use this. My MSN Messenger profile is mse_arhus@hotmail.com Always nice to have a realtime chat with people. So if you have any suggestions plz contact me. Regards GreateWhite.DK "Kenneth Land" <kland1@neuralog1.com1> wrote in message news:10a71c6ip7lvr1e@news.supernews.com... > > "GreateWhite.DK" <mse@ect.dk> wrote in message > news:40a37e22$0$459$edfadb0f@dread14.news.tele.dk... > > Hi > > > > I am struggleing with the bootcode. I have compressed the hardware image > to > > half the size with the buildin tool. Now I want to compress the SW image. > > How can I do this? Can it be done from within Quartus II or must I do it > in > > some other way? > > > > Hope u can help > > Thanks upfront > > GreateWhite.DK > > > > > > I assume you mean that you want to store your Nios firmware in the EPCS > config chip using the compressed bitstream facilities? > > Well, I don't have the answer, but I'd like to do the same thing. :) I'm > using an EPCS4 with a compressed HW image and uncompressed firmware. > > It's not quite enough room for all of my firmware, but if I could compress > it, it would fit. I don't see any API in the ASMI interface to access > compression. I could do my own compression, but since I have another serial > flash chip on my board I just use that. > > In a few months Altera will be shipping EPCS16 and EPCS64 config chips with > lots more room. Still it would be nice to have an ASMI interface to > compress/decompress. Perhaps with Nios II? :) > > Ken > >Article: 69567
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<guSoc.1853$FN.204427@news02.tsnz.net>...
> > With this sequece it *seems* that the synthesis is ok: I tried to make a
> > new very simple design from scratch and it worked fine.
>
> This was for your needed ispLSI1032E-70LJ84 - or a newer device/fitter ?
Sorry, I don't fully understand what you mean.
I have an old Synario project saved for ispLSI1032-60 (that is not
supported by Synario 5.1), but I have available also a ispLSI1032E-70
(supported).
With the new design flowchain that I found, it seems that I'm able to
work properly with 1032E.
If also Synario would work properly (that is, if SYNDPM would not give
the "spawn child error"), I could work only with Synario without
IspPDS, I think.
> I think lattice offer a VHDL flow, but for 32 MC CPLDs
I found references about a "ISPvhdl" tool: it could be useful to me.
I looked in SYNDPM.exe with an HEX file viewer.
I found some messages:
LatticeStdioWinID LatticeAppQuit LatticeAppStart suspend continue
terminate beat SYNDPM EXIT MESSAGE Syndpm Exiting %d
PDS_SYNDPM_DEBUG SYNDPM DEBUG MESSAGE SYNDPM CLOSING APPLICATION
SynDPM Closing Application %d, imm:%d SYNDPM abel_yield ended
SYNDPM MESSAGE Syndpm break received %d %s SYNDPM abel_yield
started Sent Heart Beat to Synario environment SYNDPM To Synario
PDS_SYNDPM_HEARTMSG %s: Child process (%d) exited with status:%d.
Wait Child *** Process is gone?...
Child process ID = %d, is active.
PDS_SYNDPM_CHILDPROC %s: Wait Child *** received child %d quit
with status %d
%s: Wait Child *** received child %d started.
No response from LSC Compiler...
Click cancel to abort returning from spawnvp.
%s: Using Current Child Id (%d) instead of handle.
%s: Child Proc %s ID -- %d
Request to close syndpm received. Syndpm exiting with status %d
%s
%s
****HERE ******** Received process exit status -1 Possible system
problem to spawn child process PDS_DPM_EXE SYNDPM LICENSE ERROR
for the ispDS+ 5.1 compiler.
FlexLM License file must be copied to the above location
License file %s not found.
Application Registered SYNDPM DEBUG ispDS+ rt PDS_SYNDPM_ARGS
LATTICE_CONSOLE_ID=%u %s/bin/dpm.exe Environment Variable PDSPLUS
is undefined. PDSPLUS=d:\pdsplus PDSPLUS=%s
PATH=%s
PATH=%s\bin;%s; PATH Cannot open current context SYNDPM CONTEXT
Env License File Set License File
LM_LICENSE_FILE=%s\license\license.dat PDS_LIC=%s PDSPLUS=%s
LM_LICENSE_FILE=%s FOUND LM_LICENSE_FILE LM_LICENSE_FILE PDSLic
PDS_LIC Failed to get PDSPLUS context string SYNARIO PDSPath ENV
PDSPath SYNARIO PDSPLUS ENV PDS_SYNDPM_ENV PDSPLUS syndpm.log wt
PDS_SYNDPM_LOG=1 c:\tmp\syndpm.log PDS_STDIO_DEBUG=1
c:\tmp\syndpm.sio PDS_SYNDPM_HEARTMSG=1 c:\tmp\syndpm.hbt
PDS_SYNDPM_ENV=1 c:\tmp\syndpm.env PDS_SYNDPM_ARGS=1
c:\tmp\syndpm.arg PDS_SYNDPM_DIOMSG=1 c:\tmp\syndpm.msg
PDS_SYNDPM_DEBUG=1 c:\tmp\syndpm.dbg PDS_SYNDPM_LOG SYNDPM
TKOutputProcMsg Data String(%d): '%s' PDS_SYNDPM_DIOMSG Syndpm
Terminate msg received %d OWNER_PROCESS CREATE COM WINDOW %s:
Failed to Create Application's COM window.
STDIO PROC %d laStdioCommClass
There are references to environment variable to set, and many other
things... : I tried to set some variables: something strange happens
(the hard disk works for more time than when no variable are set),
but the result is negative.
Even when not setting anything, I noticed that after sending the
command line, a short windows appear and suddendly disappears: it
could be the "child" process that generates the problem to SYNDPM....
Maybe with other changes I could find the solution, but I've already
lost too much time: I'll try to use the alternative design flow chain.
Thank you again,
Bye!
Article: 69568tom1@launchbird.com (Tom Hawkins) writes: > jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405121132.2e45e653@posting.google.com>... > > > With two clocks and two write ports!? > > > > Ok, maybe not that particular case, but most other configurations of > > dual-port RAM can be infered. In Verilog at least, isn't this a > > problem with the language rather than the FPGA tools (i.e. you can't > > write to the same variable from two different processes)? > > Verilog does not have this restriction. I've searched the LRM and > I've run testcases through two reputable implementations without > complaints (ncverilog, icarus). > > Hence my frustration. We can precisely describe a dual port block-ram > in Verilog, yet the tools draw a blank. We can even preset RAMs with > values, but most, if not all, completely disregard initial statements. > I've asked Synplify, and they can infer two-read, one-write, two-clock RAMs currently. They plan to support the full two port functionality in future... Initials are another thing though! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69569
> > Ok, maybe not that particular case, but most other configurations of > > dual-port RAM can be infered. In Verilog at least, isn't this a > > problem with the language rather than the FPGA tools (i.e. you can't > > write to the same variable from two different processes)? > > Verilog does not have this restriction. I've searched the LRM and > I've run testcases through two reputable implementations without > complaints (ncverilog, icarus). You are correct. Although it is only ever supported for simulation. I can kind of understand why though. Take the following: module test(c1, c2, a, b, d); input c1, c2, a, b; output d; reg d; always @(posedge c1) d <= a; always @(posedge c2) d <= b; endmodule What logic would you synthesize it to? Have you tried this with a behavioural synthesis tool? Maybe that could do a better job. > Hence my frustration. We can precisely describe a dual port block-ram > in Verilog, yet the tools draw a blank. We can even preset RAMs with > values, but most, if not all, completely disregard initial statements. Isn't this fixed in v200x? I do agree it's all a bit crap. Cheers, JonBArticle: 69570
Fabio G. wrote: <snip> > I looked in SYNDPM.exe with an HEX file viewer. > I found some messages: > > LatticeStdioWinID LatticeAppQuit LatticeAppStart suspend continue > terminate beat SYNDPM EXIT MESSAGE Syndpm Exiting %d > PDS_SYNDPM_DEBUG SYNDPM DEBUG MESSAGE SYNDPM CLOSING APPLICATION > SynDPM Closing Application %d, imm:%d SYNDPM abel_yield ended > SYNDPM MESSAGE Syndpm break received %d %s SYNDPM abel_yield > started Sent Heart Beat to Synario environment SYNDPM To Synario > PDS_SYNDPM_HEARTMSG %s: Child process (%d) exited with status:%d. > Wait Child *** Process is gone?... > Child process ID = %d, is active. > PDS_SYNDPM_CHILDPROC %s: Wait Child *** received child %d quit > with status %d > %s: Wait Child *** received child %d started. > No response from LSC Compiler... > Click cancel to abort returning from spawnvp. > %s: Using Current Child Id (%d) instead of handle. > %s: Child Proc %s ID -- %d > Request to close syndpm received. Syndpm exiting with status %d > %s > %s > ****HERE ******** Received process exit status -1 Possible system > problem to spawn child process PDS_DPM_EXE SYNDPM LICENSE ERROR > for the ispDS+ 5.1 compiler. > FlexLM License file must be copied to the above location > License file %s not found. > Application Registered SYNDPM DEBUG ispDS+ rt PDS_SYNDPM_ARGS > LATTICE_CONSOLE_ID=%u %s/bin/dpm.exe Environment Variable PDSPLUS > is undefined. PDSPLUS=d:\pdsplus PDSPLUS=%s > PATH=%s > PATH=%s\bin;%s; PATH Cannot open current context SYNDPM CONTEXT > Env License File Set License File > LM_LICENSE_FILE=%s\license\license.dat PDS_LIC=%s PDSPLUS=%s > LM_LICENSE_FILE=%s FOUND LM_LICENSE_FILE LM_LICENSE_FILE PDSLic > PDS_LIC Failed to get PDSPLUS context string SYNARIO PDSPath ENV > PDSPath SYNARIO PDSPLUS ENV PDS_SYNDPM_ENV PDSPLUS syndpm.log wt > PDS_SYNDPM_LOG=1 c:\tmp\syndpm.log PDS_STDIO_DEBUG=1 > c:\tmp\syndpm.sio PDS_SYNDPM_HEARTMSG=1 c:\tmp\syndpm.hbt > PDS_SYNDPM_ENV=1 c:\tmp\syndpm.env PDS_SYNDPM_ARGS=1 > c:\tmp\syndpm.arg PDS_SYNDPM_DIOMSG=1 c:\tmp\syndpm.msg > PDS_SYNDPM_DEBUG=1 c:\tmp\syndpm.dbg PDS_SYNDPM_LOG SYNDPM > TKOutputProcMsg Data String(%d): '%s' PDS_SYNDPM_DIOMSG Syndpm > Terminate msg received %d OWNER_PROCESS CREATE COM WINDOW %s: > Failed to Create Application's COM window. > STDIO PROC %d laStdioCommClass Hmmm, sounds like this fitter uses the KEY and license scheme of a certain release Synario, so you will need to have all that correctly installed and setup. > Maybe with other changes I could find the solution, but I've already > lost too much time: I'll try to use the alternative design flow chain. If the 'E' version fits, and you have a tool flow for that, sounds like you are OK. -jgArticle: 69571
Dear Comp.Arch.Fpga I was just trying to get a license key for Quartus II Web Edition. It tells me that I need to provide a NIC to get the license key: * >Network Interface Card Number:*Your NIC number is a 12-digit hexadecimal number >that identifying the Windows workstation that serves the Quartus II Web Edition license. >You can find the NIC number for your network card by typing ipconfig /all at a command >prompt. Your NIC number is the number on the physical address line, minus the dashes, >for example, 00C04FA392EF Does this mean that I should install an ethernet card? Also I don't understand "Windows workstation that serves the Quartus II Web Edition license". Does this mean I need a network of several machines to use Quartus II? Your help is appreciated, FlorianArticle: 69572
"Anil Khanna" <anil_khanna@mentor.com> wrote in message news:<40a3b3f0$1@solnews.wv.mentorg.com>... > Hi, > > When using the DDR functionality, is it the user's responsibility to provide > the phase-shifted clocks or does the above mentioned primitive do this for > me? The documentation is not very clear. > The primitive has two clock inputs, they should both be connected. > Although using a DLL to phase-shift is the best practice, can I get by just > using an inverter between the two clocks? If so, does the Virtex-II IOB > provide a "free" inverter (gets absorbed in the IOB)? Yes. You can connect clk to one input and !clk to the other and the inverter is sucked into the IOB. Note that many people still use the 0 and 180 clock outputs from a DCM to do this which requires two global clock buffers. Also remember that to work reliably with a single clock and its inversion, your clock needs to have a 50% duty cycle. > > Comments? > > AnilArticle: 69573
Fred Ma <fma@doe.carleton.ca> wrote in message news:<40A4605E.256F58DA@doe.carleton.ca>... > Hello, > > I'm looking for a way to generate somewhat random netlists of upto 25 > ALU-like cells. As an illustration of the cells' level of > abstraction, please see http://www.doe.carleton.ca/~fma/RCHW/Cell.png. > The blue boxes are word-oriented computing/boolean logic. > snipping Looks like a datapath to me, and a piece of cake. Why wouldn't you use a HDL, either one can describe bit twiddly ops. Verilog is esp suitable for that being very wire low level oriented. You can almost as easily describe this in C by converting the HDL for simulation purposes. But I think I am missing your main point too. regards johnjakson_usa_comArticle: 69574
You do not need a network. However you do need to install Ethernet card, to get the NIC number. The NIC number is used to generate the license for your computer. - Subroto Datta Altera Corp. "Florian Student" <studenfn@trick.informatik.uni-stuttgart.de> wrote in message news:c82g11$op0$1@inf2.informatik.uni-stuttgart.de... > Dear Comp.Arch.Fpga > > I was just trying to get a license key for Quartus II Web Edition. It > tells me that I need to provide a NIC to get the license key: > * > >Network Interface Card Number:*Your NIC number is a 12-digit > hexadecimal number >that identifying the Windows workstation that serves > the Quartus II Web Edition license. >You can find the NIC number for > your network card by typing ipconfig /all at a command >prompt. Your NIC > number is the number on the physical address line, minus the dashes, > >for example, 00C04FA392EF > > Does this mean that I should install an ethernet card? Also I don't > understand "Windows workstation that serves the Quartus II Web Edition > license". Does this mean I need a network of several machines to use > Quartus II? > > Your help is appreciated, > > Florian >
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