Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 69575

Article: 69575
Subject: Re: Effects of moisture on CPLD
From: "Dave Marsh" <me@privacy.net>
Date: Fri, 14 May 2004 14:49:39 +0100
Links: << >>  << T >>  << A >>
"Andy Peters" <Bassman59a@yahoo.com> wrote in message
news:9a2c3a75.0405131635.25f8ea90@posting.google.com...
> "Leon Heller" <leon_heller@hotmail.com> wrote in message
news:<40a0ebc8$0$25328$cc9e4d1f@news-text.dial.pipex.com>...
> >
> > Reflow soldering without baking them (probably 120 C for 24 hours) might
> > give problems. Hand soldering should be OK: I never have problems,
anyway.
>
> I'm not so sure about that.  I bought a handful of microcontrollers
> about a year ago and stuffed boards, and all was fine.  I never
> resealed the bag (I don't have the facility) so they sat until I used
> them a month ago.  I handsoldered one prototype and it failed in a
> particular way.  After much gnashing of teeth (I hate shotgunning
> parts), I removed the micro and replaced it with another from the same
> bag, which worked.  I have since hand-built three more prototypes and
> I've had a 50% fallout.  I guess I should've baked the parts...
>
> -a

Thanks Andy. That's interesting - One of the assembly houses I've come
across on the web says the parts would need baking before they will hand
solder them . This seems to concur with your experiences.

Dave




Article: 69576
Subject: Re: Quartus II Web Edition
From: Ray Andraka <ray@andraka.com>
Date: Fri, 14 May 2004 10:02:21 -0400
Links: << >>  << T >>  << A >>
IIRC, windows 2000 needs that NIC to be connected to a network in order to make
the serial number available to the computer.  I recall someone doing something
with a loopback connector to make it appear.

Subroto Datta wrote:

> You do not need  a network. However you do need to install Ethernet card, to
> get the NIC number. The NIC number is used to generate the license for your
> computer.
>
> - Subroto Datta
> Altera Corp.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 69577
Subject: Re: Quartus II Web Edition
From: "Kenneth Land" <kland1@neuralog1.com1>
Date: Fri, 14 May 2004 09:41:05 -0500
Links: << >>  << T >>  << A >>

When I do work offsite I take a small 5 port switch with me.  Plugging my
PC's network cable into the switch causes the NIC to be active and available
for licensing software.

Ken

"Ray Andraka" <ray@andraka.com> wrote in message
news:40A4D16D.3079F0EE@andraka.com...
> IIRC, windows 2000 needs that NIC to be connected to a network in order to
make
> the serial number available to the computer.  I recall someone doing
something
> with a loopback connector to make it appear.
>
> Subroto Datta wrote:
>
> > You do not need  a network. However you do need to install Ethernet
card, to
> > get the NIC number. The NIC number is used to generate the license for
your
> > computer.
> >
> > - Subroto Datta
> > Altera Corp.
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 69578
Subject: Re: Instantiating subblock signals with VHDL
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 14 May 2004 08:01:24 -0700
Links: << >>  << T >>  << A >>
arkaitz wrote:

> This question might obvious, but I cannot find any other way to
> instantiate signals from a top of a design for simulation purposes.

Consider instancing all of your sub-entities,
directly into a testbench and wiring
them up with testbench signals.
Now one level of structural wiring 
is directly visible.

After you get this working, add an instance
of the real top entity into the same testbench
to verify that it works the same.

    -- Mike Treseler



Article: 69579
Subject: Re: Quartus II Web Edition
From: Rene Tschaggelar <none@none.net>
Date: Fri, 14 May 2004 17:08:10 +0200
Links: << >>  << T >>  << A >>
No, it does not. Not really.
You have to change/add a registry key :


HKLM\System\ControlSet001\Services\Tcpip\parameters\
new DWORD : DisableDHCPMediaSense assign =1

Rene


Ray Andraka wrote:
> IIRC, windows 2000 needs that NIC to be connected to a network in order to make
> the serial number available to the computer.  I recall someone doing something
> with a loopback connector to make it appear.
> 
> Subroto Datta wrote:
> 
> 
>>You do not need  a network. However you do need to install Ethernet card, to
>>get the NIC number. The NIC number is used to generate the license for your
>>computer.
>>
>>- Subroto Datta
>>Altera Corp.
> 
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
> 
> 

Article: 69580
Subject: best fpga development board?
From: geoffrey wall <wallge@eng.fsu.edu>
Date: Fri, 14 May 2004 11:21:27 -0400
Links: << >>  << T >>  << A >>
Im looking to do some real-time video processing algorithms,
but i am mostly a software person... i need an fpga with good 
development tools (not buggy) that will be easy to use for someone who 
is learning how to program hdl and use the hardware for the first time.
Ideally i would like a powerful and flexible board with good development 
tools, good tech support and documentation. Any suggestions?

thanks


Article: 69581
Subject: Re: virtex dev board?
From: "myren, lord" <thefowle@wam.umd.edu>
Date: Fri, 14 May 2004 11:37:11 -0400
Links: << >>  << T >>  << A >>
it also looks like it lacks any sort of connectors for Rocket I/O.  The 
higher model Memec boards have connectors for Rocket I/O... I'm not sure 
if that means the Rocket I/O is unusuable, or if you can access it 
through the pin headers.

Myren

Article: 69582
Subject: Re: Video Blob Analysis on FPGAs
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Fri, 14 May 2004 09:04:19 -0700
Links: << >>  << T >>  << A >>
Still looking for some suggestions.



Article: 69583
Subject: Re: program flash memory through JTAG on FPGA
From: Ryan Laity <ryan-dot..laityatpleasenospam@x--i-lin_xdotcom>
Date: Fri, 14 May 2004 09:19:09 -0700
Links: << >>  << T >>  << A >>
You could also implement a MicroBlaze system with the processor, a 
memory controller peripheral (EMC), and a Debug Module (MDM) in the 
FPGA.  You'd configure the FPGA via JTAG and then connect your PC to the 
MDM via JTAG and XMD.  With this arrangement, you're using JTAG as your 
connection to the debug module which is running in the FPGA.  It's not 
terribly fast(see XMD documentation for more information) but it's 
getting faster and it'll definitely get the job done.  You could also 
use another connection to a terminal/PC such as ethernet or RS232 to 
make this transfer of data, it just depends upon what you have available 
to you.

I believe that there are also companies who specialize in using the 
boundary scan "XTEST" capability to program storage parts such as Flash 
just as Petter described - you may also wish to look into that.

Best regards,
Ryan Laity
Xilinx Applications

Petter Gustad wrote:
> Bassman59a@yahoo.com (Andy Peters) writes:
> 
> 
>>"rat" <rattt@col.edu.cn> wrote in message news:<c7ujmp$1phn$1@mail.cn99.com>...
>>
>>>Hi,
>>>  In my design, there is a flash memory chip connecting to fpga chip, I want
>>>to program the flash memory through the JTAG port on the FPGA, where can I
>>>find some introduction?
>>
>>I don't think it's possible to do this.  The FPGA JTAG ports are
>>dedicated to boundary scan, and in the case of CPLDs, are used for
>>device programming.  You can't access the JTAG controller directly in
>>FPGA logic.
> 
> 
> Look at Jim's message. You can control all the IO's on the FPGA
> through the FPGA. Then you can apply patterns on the pins connected to
> the flash to program it. In general you can do this with most JTAG
> devices. I've programmed I2C proms through the JTAG port of on of our
> ASICs. The tricky part is to generate the JTAG patterns to do the
> programming.
> 
> 
>>However, you could implement your own JTAG TAP controller in the FPGA
>>and wire that to the flash controller, and bring your JTAG signals out
>>on regular I/O pins.
> 
> 
> I guess rat might be interested to put the FPGA bitstream into the
> flash in order to program the FPGA. In this case there is no loaded
> FPGA on the board.
> 
> Petter
> 

Article: 69584
Subject: Re: best fpga development board?
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 14 May 2004 09:26:36 -0700
Links: << >>  << T >>  << A >>
Hi Geoffrey,
I saw your posting on comp.dsp, I guess you've decided on the FPGA route?
So, for boards and other goodies go to Philip's excellent
http://www.fpga-faq.com/ . I've used a board from www.xess.com to do the
stuff you're talking about. It did what they said it would!
Good luck, Syms.
"geoffrey wall" <wallge@eng.fsu.edu> wrote in message
news:c82o6r$g2m$1@news.fsu.edu...
> Im looking to do some real-time video processing algorithms,
> but i am mostly a software person... i need an fpga with good
> development tools (not buggy) that will be easy to use for someone who
> is learning how to program hdl and use the hardware for the first time.
> Ideally i would like a powerful and flexible board with good development
> tools, good tech support and documentation. Any suggestions?
>
> thanks
>



Article: 69585
Subject: Re: virtex dev board?
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 14 May 2004 09:36:31 -0700
Links: << >>  << T >>  << A >>
Myren,

Unless a board has been layed out properly for MGT use, other than 
checking functionality, it is not recommended.

Check with your disti or Xilinx FAE on what boards are intended for MGT 
use, and which ones are not intended for MGT use.

For example, to pass the XAUI jitter tests, or to get the longest reach, 
requires a board that was designed for the best performance of the MGTs 
per the MGT user manual.  If the board was built to showcase the PPC, 
then the vendor (including Xilinx) may not have spent the time and/or 
money on the MGT part of the pcb (because they did not have to).

Another common error, is that some standards do not run at 3.125 Gbs. 
Often folks will be checking out a fibre channel optical interface, and 
call and ask us why it doesn't work at 3 gig.....uh, excuse me, the 
optics stopped working a long time ago!?

A good sign that a pcb was not intended to support the MGTs is that 
there are no SMAs on the pcb.  But even with SMAs on the pcb, it still 
may have been an afterthought to provide a connection even though the 
user's guide was not followed.

Even a layout with no thought for the MGTs will still function, and 
allow development of the code.


Austin

myren, lord wrote:
> it also looks like it lacks any sort of connectors for Rocket I/O.  The 
> higher model Memec boards have connectors for Rocket I/O... I'm not sure 
> if that means the Rocket I/O is unusuable, or if you can access it 
> through the pin headers.
> 
> Myren

Article: 69586
Subject: Re: best fpga development board?
From: geoffrey wall <wallge@eng.fsu.edu>
Date: Fri, 14 May 2004 13:50:32 -0400
Links: << >>  << T >>  << A >>
actually, i think we are going to try both solutions(dsp and fpga) and 
see how they compare with each other. thanks for the feedback.

Symon wrote:
> Hi Geoffrey,
> I saw your posting on comp.dsp, I guess you've decided on the FPGA route?
> So, for boards and other goodies go to Philip's excellent
> http://www.fpga-faq.com/ . I've used a board from www.xess.com to do the
> stuff you're talking about. It did what they said it would!
> Good luck, Syms.
> "geoffrey wall" <wallge@eng.fsu.edu> wrote in message
> news:c82o6r$g2m$1@news.fsu.edu...
> 
>>Im looking to do some real-time video processing algorithms,
>>but i am mostly a software person... i need an fpga with good
>>development tools (not buggy) that will be easy to use for someone who
>>is learning how to program hdl and use the hardware for the first time.
>>Ideally i would like a powerful and flexible board with good development
>>tools, good tech support and documentation. Any suggestions?
>>
>>thanks
>>
> 
> 
> 


Article: 69587
Subject: Re: One issue about free hardware
From: Roger Larsson <roger.larsson@skelleftea.mail.telia.com>
Date: Fri, 14 May 2004 17:59:03 GMT
Links: << >>  << T >>  << A >>
Tom Hawkins wrote:

> 2. With Confluence under GPL, I have yet to receive a single bug
> report or source code contribution.
> 

For some tools it can take a very long time to build a userbase.
Step 1. You need to know about it.
        - I know about Confluence.
Step 2. You need to have something suitable to try it with.
        - Maybe this summer...
Step 3. It needs to be good enough.
        No idea... since I have not tried it yet.
Step 4a. It needs to have bugs to give you bug reports :-)
Step 4b. It needs to be incomplete to give you feature requests.
Step 5. Bugs or feature requests that you can't easily fix might
        generate source code contributions.
        Take care when accepting contributions... When added you
        can not dual license (contribution is copyrighted by their author).
        But most contributors won't have a problem with that...

Compare with:
* MySQL
* Qt
* Erlang (functional programming language, GPL:ed by Ericsson) and they have
lots of people internally that uses it.
 - it slowly builds momentum...
But there are a lot more people that use databases, create user
interfaces, ...

/RogerL

-- 
Roger Larsson
Skellefteċ
Sweden

Article: 69588
Subject: Re: Simple way to generate random netlists of ALU cells
From: Fred Ma <fma@doe.carleton.ca>
Date: 14 May 2004 21:58:38 GMT
Links: << >>  << T >>  << A >>
john jakson wrote:
> 
> Fred Ma <fma@doe.carleton.ca> wrote in message news:<40A4605E.256F58DA@doe.carleton.ca>...
> > Hello,
> >
> > I'm looking for a way to generate somewhat random netlists of upto 25
> > ALU-like cells.  As an illustration of the cells' level of
> > abstraction, please see http://www.doe.carleton.ca/~fma/RCHW/Cell.png.
> > The blue boxes are word-oriented computing/boolean logic.
> >
> 
> snipping
> 
> Looks like a datapath to me, and a piece of cake.
> 
> Why wouldn't you use a HDL, either one can describe bit twiddly ops.
> 
> Verilog is esp suitable for that being very wire low level oriented.
> 
> You can almost as easily describe this in C by converting the HDL for
> simulation purposes.
> 
> But I think I am missing your main point too.

I'm actually not trying to model the ALU-like cell.  I'm trying to
generate random netlist of those cells.  However, a completely
random net list is not realistic.

Fred
-- 
Fred Ma
Dept. of Electronics, Carleton University
1125 Colonel By Drive, Ottawa, Ontario
Canada, K1S 5B6

Article: 69589
Subject: Re: best fpga development board?
From: jon@beniston.com (Jon Beniston)
Date: 14 May 2004 16:01:37 -0700
Links: << >>  << T >>  << A >>
> i need an fpga with good 
> development tools (not buggy) 

You're hoping! IMHO, you should stear well clear of Xilinx's XST.. It
has a nasty habbit of synthesizing bad logic. Agggh! It's even
screwing me as I right this. The alternatives aren't cheap (synplify
for example), but are better.

Cheers,
JonB

Article: 69590
Subject: Re: One issue about free hardware
From: jon@beniston.com (Jon Beniston)
Date: 14 May 2004 16:05:06 -0700
Links: << >>  << T >>  << A >>
>         Take care when accepting contributions... When added you
>         can not dual license (contribution is copyrighted by their author).
>         But most contributors won't have a problem with that...

GCC et al deal with this by requiring contributors to assign
copyright, and it hasn't been a problem for them.
 
> Compare with:
> * MySQL
> * Qt
> * Erlang (functional programming language, GPL:ed by Ericsson) and they have
> lots of people internally that uses it.
>  - it slowly builds momentum...
> But there are a lot more people that use databases, create user
> interfaces, ...

How many FPGA/ASIC designers do we reckon are out there? I'm sure I've
heard Xilinx saying they have a couple hundred thousand installations
of their s/w. That's quite a big target audience.

Cheers,
JonB

Article: 69591
Subject: Re: ISE 6.2i Synopsys Design Compiler libraries?
From: jon@beniston.com (Jon Beniston)
Date: 14 May 2004 16:07:18 -0700
Links: << >>  << T >>  << A >>
Petter Gustad <newsmailcomp5@gustad.com> wrote in message news:<m3isf0zoya.fsf@scimul.dolphinics.no>...
> Earlier the Xilinx ISE distribution included a CAE Libraries CD. This
> CD contained Synopsys Design Compiler libraries (.db files) which were
> installed under $XILINX/synopsys/libraries/syn/. 
> 
> But now I can't seem to find any Synopsys .db files in ISE 6.2i. Can I
> download these from the Xilinx Web site or order a CD? 
> 
> It's not a problem for Virtex-II/Pro and Spartan-III where Synopsys
> provide libraries with Design Compiler FPGA (BTW a great synthesis
> tool, especially if you are used to DC for ASIC design). 
> 
> Petter

See:

http://www.xilinx.com/ise/partner_libraries/index.htm

Cheers,
JonB

Article: 69592
Subject: Clueless newbie question -- what has changed to make moisture such
From: "William H. Maddox III" <NOSPAMmaddox@NOSPAMtransmetaDOTCOM>
Date: Fri, 14 May 2004 16:46:00 -0700
Links: << >>  << T >>  << A >>
Plastic packages have been used for years, but it is only very recently
that I've heard of moisture absorption becoming big issue.  Clearly, with
such dramatic effects on reliability, it can't be that we just were ignorant
of a long-standing problem.  What is it about these parts that causes the
moisture sensitivity, or why has it become such an issue recently?

--Bill

Article: 69593
Subject: Re: Simple way to generate random netlists of ALU cells
From: Ray Andraka <ray@andraka.com>
Date: Fri, 14 May 2004 19:51:04 -0400
Links: << >>  << T >>  << A >>
Why?

Fred Ma wrote:

>
> I'm actually not trying to model the ALU-like cell.  I'm trying to
> generate random netlist of those cells.  However, a completely
> random net list is not realistic.
>
> Fred
> --
> Fred Ma
> Dept. of Electronics, Carleton University
> 1125 Colonel By Drive, Ottawa, Ontario
> Canada, K1S 5B6

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 69594
Subject: Re: One issue about free hardware
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 14 May 2004 17:33:02 -0700
Links: << >>  << T >>  << A >>
Jon Beniston wrote:

> How many FPGA/ASIC designers do we reckon are out there? I'm sure I've
> heard Xilinx saying they have a couple hundred thousand installations
> of their s/w. That's quite a big target audience.

That sounds a little inflated to me.
I would guess only 5-10 thousand in the US.

      -- Mike Treseler

Article: 69595
Subject: Re: Video Blob Analysis on FPGAs
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 14 May 2004 17:38:22 -0700
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:

> Still looking for some suggestions.

Consider google.com

http://www.itee.uq.edu.au/~damien/GuRoo/theses/Wong.pdf

 -- Mike Treseler

Article: 69596
Subject: Re: program flash memory through JTAG on FPGA
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Fri, 14 May 2004 17:42:56 -0700
Links: << >>  << T >>  << A >>

Hi,

There's a tool called Universal Scan that does just what
you are looking for.  http://www.universalscan.com/
I had some students using it at SJSU to program an Intel
Flash attached to a Spartan-IIE.  I was impressed with 
the tool.

Eric

Article: 69597
Subject: 5V signals at Spartan-IIE inputs
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 14 May 2004 20:44:31 -0400
Links: << >>  << T >>  << A >>
Hi all,

I overlooked this during design and the board has already been manufactured.
I have a XC2S300E connected to inputs of a 5V chip. The outputs of that chip
going back to the FPGA pass through level translation. What I overlooked is
that those 5V inputs of the chip have internal pullups (I beleive 5k)...

So, my question is how bad is this situation? The max FPGA input voltage is
obviously exceeded but the current is limited to 1mA...

Thanks,
/Mikhail



Article: 69598
Subject: Re: 5V signals at Spartan-IIE inputs
From: "Andras Tantos" <andras_tantos@yahoo.com>
Date: Fri, 14 May 2004 17:50:21 -0700
Links: << >>  << T >>  << A >>
> Hi all,
>
> I overlooked this during design and the board has already been
manufactured.
> I have a XC2S300E connected to inputs of a 5V chip. The outputs of that
chip
> going back to the FPGA pass through level translation. What I overlooked
is
> that those 5V inputs of the chip have internal pullups (I beleive 5k)...
>
> So, my question is how bad is this situation? The max FPGA input voltage
is
> obviously exceeded but the current is limited to 1mA...
>
> Thanks,
> /Mikhail
>

Xilinx says that the Spartan2E series is 5V tolerant if you limit the input
current to ~10mA (IIRC). They propose the use of serial limiting resistors
but I guess the solution is irrelevant as long as the current is within
limits.

--
Regards,
Andras Tantos
<http://andrast.tantos.homedns.org>



Article: 69599
Subject: Re: One issue about free hardware
From: jon@beniston.com (Jon Beniston)
Date: 14 May 2004 18:09:54 -0700
Links: << >>  << T >>  << A >>
Roger Larsson <roger.larsson@skelleftea.mail.telia.com> wrote in message news:<HN7pc.59087$mU6.238562@newsb.telia.net>...
> Tom Hawkins wrote:
> 
> > 2. With Confluence under GPL, I have yet to receive a single bug
> > report or source code contribution.
> > 
> 
> For some tools it can take a very long time to build a userbase.
> Step 1. You need to know about it.
>         - I know about Confluence.
> Step 2. You need to have something suitable to try it with.
>         - Maybe this summer...
> Step 3. It needs to be good enough.
>         No idea... since I have not tried it yet.
> Step 4a. It needs to have bugs to give you bug reports :-)
> Step 4b. It needs to be incomplete to give you feature requests.

Step 4c. It needs to be programmed in a language that your small
target audience have heard of! How many Verilog/VHDL coders also know
OCaml? C or Java and you might have a chance...

Cheers,
JonB



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search