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Symon wrote: > In the past, I've kept the entity ports as slv, just using unsigned etc. > within the architecture. Partly because of reuse, easier for others to > understand on a multiple person team, etc. Now that numeric.std has been > standardised, I wonder if there's a reason to do this anymore? If you have unsigned as primary IOs on your FPGA, xilinx tools will replace them with slv on the gate level model and break your testbench. -JCCArticle: 69676
First realize that VHDL has nothing to do to your question. Neither do the FPGAs. Your question probably belongs to the comp.dsp newsgroup, but before you post it there I would recommend you to do some more homework. /Mikhail "viswanath" <daita@eng.usf.edu> wrote in message news:791e9679.0405171229.4a846cc5@posting.google.com... > Hi, > I have to design a low pass filter in VHDL. How can one go about > designing such a filter when the medium is event driven and time > domain based?? > How should one decide on the filter characteristics if we just know > the symbol time rate. > If I am using standard VHDL and not AMS is it possible for me to > design such a filter which is used in the recovery loops of receiver? > Most of the references on filter and digital communications refer to > frequency domain analysis. How can I go around this problem? > If the input is a pulse then a low pass filter is an integrate and > dump. However if I have a sampled sine wave how could I design a low > pass filter? Could you please reply and let me know? > I would grealty appreciate your reply. > Looking forward to your replies, > Thanks > Viswanath > PS: I would be needing a filter after the mixing of two sine waves to > filter out the higher frequency componentsArticle: 69677
"Jeff Cunningham" <jcc@sover.net> wrote in message news:hPeqc.2181$Hf.1277774@newshog.newsread.com... > Symon wrote: > > In the past, I've kept the entity ports as slv, just using unsigned etc. > > within the architecture. Partly because of reuse, easier for others to > > understand on a multiple person team, etc. Now that numeric.std has been > > standardised, I wonder if there's a reason to do this anymore? > > If you have unsigned as primary IOs on your FPGA, xilinx tools will > replace them with slv on the gate level model and break your testbench. This was part of my problem, one of the slv's was part of the input specification to the pwm unit (8 bits of 'current count' data), comparing an SLV to an unsigned gives an error message (something about 6 possible ways to interpret the result), even unsigned(slv) gives that error, but unsigned/unsigned compares work as do slv/slv compares. I was just curious if the slv/slv compare was done by default as signed or unsigned. --ChuckArticle: 69678
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:10ai4se7jrp67d7@corp.supernews.com... > I have read some CMU documentation but nothing > about blob analysis. I had believed that the CMU > can only track one blob whereas I need to collect > data about lots of blobs. That is basically true, but I expect it was a limitation of the compute cycles on the scenix processor more than anything else. > Center of gravity is good. > Long axis, area, etc. If you suggest I will look > deeper into the CMU docs and web sites. Thanks. > > What is iso-bar? Comes from the weather service, imagine that you have a "cloud" of pixels that you characterise by color (or some other attribute, intensity perhaps). Now all of the pixels that fall in the desired "range" get mapped with a line that defines the edge of the group (where a neighbor is not in the range) On a weather map you use pressure ranges, on a topographic map you use altitude, but the effect is the same, you define a blob by creating a closed line around all pixels that are "in range" This algorithm can convert raw video into something with "blob" semantics (a number of closed polygons), note however you can still get polygons within polygons (donuts). Back in the day at the Image Processing Institute at USC a couple of the grad students were using techniques like this to help generate maps from arial photographs. ETAK picked up the technology and did some of the first digital maps (actually DARPA used it first, but ETAK was the commercial application). Until you posted I hadn't really thought about building pixel engines in FPGAs for image processing type applications. (Which is silly considering I did some simulation work on Intel's 82786 Graphics chip which had a built in BLIT engine). The thing I can't visualize is how you could get the information out of the FPGA fast enough to act on it. > On one of your other post you are comparing > a std_logic_vector to another. I suggest you > repost and state what libraries you are using. > I remember a difficulty in the original VHDL > spec that didn't allow for this that may have > been patched up by a library. VHDL has > been a work in progress for many years with > most improvements added via libraries. This is one of those times where leaving it for a year or so and coming back to it has given me the opportunity to use better tools. Xilinx ships the Coolrunner II in a 56 ball grid array that is just 6 mm x 6 mm (yes about 1/4" on a side) and it occurred to me that you could use that to build a kick-arse PWM unit that was tuned to robotic motor applications. Mounting it on an 14 pin DIP carrier with appropriate 5v tolerance stuff should make it possible for non-SMT capable hobbiests to use it. Then with the left over gates I was thinking quadarature decoder/counter and it seems like a nice little bundle. So I did a quick layout in latest WebPack which insists on making inputs and outputs to VHDL modules Std_logic_vectors but my counter code was using unsigned. --ChuckArticle: 69679
"Philip Freidin" <philip@fliptronics.com> wrote in message
news:btnga0lfqn852p9rnj2ff1kjant6m4p76q@4ax.com...
> On Sun, 16 May 2004 23:59:33 GMT, "Chuck McManis" <devnull@mcmanis.com>
wrote:
> >
> > ....
> > cascaded devices with serial data In and Out, also considering
> > daisy chained clock. Freq is 400 KHz.
> > ....
> >
>
> A good example of how this is solved is the serial daisy chain
> configuration of the Xilinx FPGAs. It even uses one less pin than
> what you are thinking of, since there is no need for a clock out
> pin. The clock goes to all devices.
>
> What Xilinx does, is it samples the data coming into each chip on
> the rising edge, and the daisy chained data out is clocked on the
> falling edge.
An excellent example Philip. I've been re-reading Chang[1] on shift
registers as well. Chang's code for the "generic" shift register is :
1 entity SHIFTR is
2 port {
3 CLK, RSTn, SI : in std_logic;
4 SO : out std_logic;
5 }
6
7 architecture RTL of SHIFTR is
8 signal FF8 : std_logic_vector(7 downto 0);
9 begin
10 posedge: process (RSTn, CLK) is
11 begin
12 if (RSTn = '0') then
13 FF8 <= (FF8'range => '0');
14 elsif (CLK'event and CLK = '1') then
15 FF8 <= SI & FF8(FF8'length-1 downto 1);
16 end if;
17 end process;
18
19 SO <= FF8(0);
20 end RTL;
(typos are mine)
Where he uses concurrent assignment in line 19 to assign the Shift Out
signal to that of the last bit of the shift register.
The inferred hardware is a line of flip-flops configured as you would expect
Q->D from one to the next, clocks in parallel and resets in parallel.
This doesn't explicitly clock out SO on the falling edge, however SO should
have the correct value on the rising edge of a parallel clock right? Since
the propagation delay of the clocking in the new data is non-zero, is it
reasonable to assume that S0 will have the correct data on the rising edge?
> Depending on the length of the shift register within each device,
> the latency is N + 0.5 clock cycles per device. But this does not
> accumulate across devices, as the .5 cycle of latency is
> treated as part of the device to device delay.
This was where I get confused. Given that the clock is in parallel,
regardless of the length of the register, should the delay be simply 'x'
where X is the propogation of the Flip flop from D to Q ? I'm thinking that
on any clock the data that is going into the next flip flop is already
sitting on the Q output of its predecessor in the chain.
> Example of devices with 5 bits of SR.
[elided]
> Obviously it would be best if the original data
> source follows this protocol too, changing the
> source data at about the same time as the falling
> edge of the clock source. This is easily done even
> in a bit-banged micro interface.
That I think I can manage :-) The driver is probably some 8 bit micro like a
PIC or AVR chip. My next challenge is to figure out how to infer a
transparent latch so that I can clock in new data "behind" the old data and
then "expose" it all at once (keeps my PWM units in sync which is important
in some cases).
--Chuck
-----
[1] "Digital Systems Design with VHDL and Synthesis", K.C. Chang, Chapter 6,
Basic sequential circuits. Pb IEEE Computer Society, ISBN 0-7695-0023-4
Article: 69680
Hi all,
In my design, DLL is used to multiply the input frequency at the
factor of 2. Since the input source clock is from the external PLL
(Generates 2 different frequency---Change in input frequency), a
manual reset is mandatory. When I tried to generate an INTERNAL SIGNAL
and mapped to the reset signal (RST) of the DLL, there were errors as
mentioned below:
ERROR:NgdBuild:455 - logical net 'rst_in' has multiple drivers. The
possible
drivers causing this are:
pin G on block XST_GND with type GND,
pin PAD on block rst_in with type PAD
ERROR:NgdBuild:466 - input pad net 'rst_in' has illegal connection.
Would the design implementation in FPGA allow the user to map an
internally generated reset signal to the reset signal of the DLL?
Tool: Xilinx ISE 6.2i
Device: Spartan XC2S200
Eagerly waiting for your suggestions..
Thanks in advance
Regards
Rajesh
Article: 69681Ray Andraka wrote: > > Fred, > > Yes, I do remember you. We hit a couple of the wineries that Friday > afternoon with you. I realize now that I was also ambiguous. I meant why > generate a random netlist. I guessed it was for something with doing > studies with PAR, but wasn't sure. Yeah, it was cool (the wineries). So is the PAR world. Who'da ever thunk that generating random circuits was such a deep topic. Fred -- Fred Ma, fma@doe.carleton.ca Dept. of Electronics, Carleton University, Ottawa, Ontario, CanadaArticle: 69682
Hi, there: How do I perform simulation with Core Generator module? Where can I find the definition for BLKMEMDP_V5_0 anda MULT_GEN_V6_0? Best Regards, KelvinArticle: 69683
Okie I got it...I found Core Gen manual... Accidentally I generated DP-RAM in V5, but MULT in V6, will that hurt the simulation or synthesis? I use ISE 6.03i... Kelvin "Student" <student@nowhere.com> wrote in message news:40a9c333$1@news.starhub.net.sg... > Hi, there: > > How do I perform simulation with Core Generator module? Where can I find the > definition for BLKMEMDP_V5_0 anda MULT_GEN_V6_0? > > Best Regards, > Kelvin > > > >Article: 69684
Hi, using the WebPack 6.1, latest service pack I get the following error message: Started process "Translate". ERROR:Portability:90 - Command line error: Unexpected argument[11] "filename.ngc" found What have I done before: 1) have existing older project which compiled well before. 2) made a new empty project and added the *.vhd sources. 3) try to compile. It stops with the above error. Some time ago I had the same error with another project. There I had renamed some files and entities (not in the questioned project). I got finally rid of the error message when I took the original source and renamed step by step, without knowing what was actually the reason for the error message, it did not appear again. In this past case I had a 'working' version, one which compiled, as a start-off. Now I am starting with the error message right in the beginning. What can I change? Where can I have a look? Thank you for any effort. Regards KlausArticle: 69685
"Chuck McManis" <devnull@mcmanis.com> writes: > "Jeff Cunningham" <jcc@sover.net> wrote in message > news:hPeqc.2181$Hf.1277774@newshog.newsread.com... > > Symon wrote: > > > In the past, I've kept the entity ports as slv, just using unsigned etc. > > > within the architecture. Partly because of reuse, easier for others to > > > understand on a multiple person team, etc. Now that numeric.std has been > > > standardised, I wonder if there's a reason to do this anymore? > > > > If you have unsigned as primary IOs on your FPGA, xilinx tools will > > replace them with slv on the gate level model and break your testbench. > Yes - I tend to keep unsigned's for within module use, although I do use them on certain entity's that won't go to the outside. > This was part of my problem, one of the slv's was part of the input > specification to the pwm unit (8 bits of 'current count' data), comparing an > SLV to an unsigned gives an error message (something about 6 possible ways > to interpret the result), even unsigned(slv) gives that error, but > unsigned/unsigned compares work as do slv/slv compares. I was just curious > if the slv/slv compare was done by default as signed or unsigned. > If you're using the synopsys std_logic_[un]signed or arith libraries then it will get done however those libraries happen to do it - which I've never been clear on, as I stick to numeric_std! If you're using numeric_std, then I don't think slv/slv compares should work. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69686
Hello newsgroup users, I have made a timing simulation for my SRAM-Controller and an external asynchronous SRAM. I have used the FPGA Cyclone timing output file for my SRAM-Controller and the extra timing file for the SRAM model. Both components have been instantiated in a testbench. How reliable are such simulations? Where do come problems along with that kind of simulations ? Is it recommendable to simulate that way when connecting some synchronous design with some asynchronous component? I would appreciate your help or your field report about your timing simulation. Thanks a lot. RgdsArticle: 69687
jon@beniston.com (Jon Beniston) writes: > Petter Gustad <newsmailcomp5@gustad.com> wrote in message news:<m3isf0zoya.fsf@scimul.dolphinics.no>... > > But now I can't seem to find any Synopsys .db files in ISE 6.2i. Can I > > download these from the Xilinx Web site or order a CD? > See: > > http://www.xilinx.com/ise/partner_libraries/index.htm Thank you, just what I was looking for. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 69688
On Tue, 18 May 2004 04:32:17 GMT, "Chuck McManis" <devnull@mcmanis.com> wrote: >"Philip Freidin" <philip@fliptronics.com> wrote >> What Xilinx does, is it samples the data coming into each chip on >> the rising edge, and the daisy chained data out is clocked on the >> falling edge. > >An excellent example Philip. I've been re-reading Chang[1] on shift >registers as well. Chang's code for the "generic" shift register is : > >... > vhdl 8 bit shifter, doing right shifts, with shift out comming > directly from the LSB >... > >Where he uses concurrent assignment in line 19 to assign the Shift Out >signal to that of the last bit of the shift register. > >This doesn't explicitly clock out SO on the falling edge, however SO should >have the correct value on the rising edge of a parallel clock right? That is correct, SO will be updated on the rising edge of the clock. It has 1 full clock cycle to get to the input of the first flipflop of the next shifter in the next chip. >Since >the propagation delay of the clocking in the new data is non-zero, is it >reasonable to assume that S0 will have the correct data on the rising edge? This is not a good assumption, because you are going across a PCB. The clock could arrive early or late with respect to the destination of SO. Given your 2.5 us cycle time, the half clock trick burns half of the cycle to make this a non issue, as the data changes happen 1.25 us away from the clock rising edge, thus easilly meeting any setup and hold requirements at the destination, regardless of any reasonably conceivable clock and data skew. >> Depending on the length of the shift register within each device, >> the latency is N + 0.5 clock cycles per device. But this does not >> accumulate across devices, as the .5 cycle of latency is >> treated as part of the device to device delay. So the last FF in the SR (FF8(0)) changes on the rising edge. Take its output to another FF, clocked on the fallin edge. The output of this FF is the new, 1/2 cycle shifted SO signal. >This was where I get confused. Given that the clock is in parallel, >regardless of the length of the register, should the delay be simply 'x' >where X is the propogation of the Flip flop from D to Q ? The delay for any flop is CLK to Q, not D to Q. >I'm thinking that >on any clock the data that is going into the next flip flop is already >sitting on the Q output of its predecessor in the chain. That is right. This is even true of the SO FF I am describing, as it has had 1/2 a cycle (1.25 us) to get to the output FF. The latency I was describing is what you see while you are debugging with your Tek 465. If you look at the SO pin of (for example) a 5 bit shift register, you will see the data coming out 5.5 cycles after it went in, but you only use 1/2 a cycle to get to the next FF in the next chip, so over all, the shifter as seen from the sw point of view is oblivious to the extra SO FF, and the 1/2 cycle delay. > >--Chuck Philip Philip Freidin FliptronicsArticle: 69689
Hello, I want to configure the Micro bus for our application. I am using a C167CS micro with the SpartanII. The bus is a 8 bit using the external bus interface of the C167 (POL Address line, P0H Data line, CS4 ). Does any one have a good VHDL example for this application ? Thanks ItArticle: 69690
> Zigbee news from Atmel - what's key here, is a move from generic > uC/Chip sales, into also selling the Zigbee SW stack, so users have > minimal SW developments for their links. Trouble is, they're using a 900MHz radio, whereas everyone else in the ZigBee/802.15.4 world is doing 2.4GHz. I personally would recommend this device: http://www.oki.com/en/press/2004/z04017e.html (Disclaimer: I designed half of it ;) ) Cheers, JonBArticle: 69691
Hi all, I am targeting my design to XCS200 -5 fg256(SPARTAN device) . My OFFSET OUT timing constraints are very tight.So inorder to decrease the PAD delay i am forced to set the drive strength to 24 and SLEW=FAST. only 2 pins of the 137 I/O's which i am using have a drive strength of 24 rest of them have a DRIVE=12. Can anyone tell me what is the significance of this DRIVE strength in REAL time.Will it create any problems having a DRIVE=24 in real time??. Thanks n rgds, pravArticle: 69692
Hi, I have instantiated a dual port block ram through coregen with a 128 bit write only port and a 32 bit read only port. I am using chipscope to debug the FPGA and when I view all signals connected to ram, all write port signals are correct, but the data read out from read port is sometimes correct, and other times it is garbage data. Could somebody suggest a solution to this problem. Is it a timing problem? (the frequency of operation is low around 10 Mhz) -- Aniket Naik Computational Mathematics Laboratory, Tata Institute of Fundamental Research, India.Article: 69693
Our new Broaddown2 Spartan3 board might meet your expectations. It is either a PCI card or can stand alone on the bench. There is a significant high speed I/O available for your use. We are expecting to build the first production run in mid-late June. We have Spartan3 silicon already for this batch so subject to the availability of a couple of minor components that date should not move very much. If you are an educational user there are discounts available on the standard pricing. Details of Broaddown2 are here http://www.enterpoint.co.uk/moelbryn/broaddown2.html . John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Dave" <davegoogle99@hotmail.com> wrote in message news:1c21ab5c.0405170251.671c1c4a@posting.google.com... > Hi guys and gals, > > Could I call on your collective experience and expertise? > > I'd like to get hold of an FPGA development board for a data streaming > project. Requirements are as follows: > > - Low cost (around 200 UK pounds ideally). > - At least 16 i/os routed out to connectors. > - High speed cabled interface to a PC, capable of sustaining a > streaming rate of at least 15Mbits/s. I've been considering USB2 or > 100M Ethernet for this. > - Enough onboard RAM to ensure continuous data transfer to software > running on a Windoze PC. > - Single power supply @ 5V or 3.3V. > > The best boards I've found so far are: > > Cyclone FPGA + basio (too expensive + 10M Ethernet too slow) > http://www.jopdesign.com/cyclone/index.jsp > > Easy FPGA (USB too slow + not enough RAM for streaming) > http://www.easyfpga.com/ez2susb_features.htm > > NuHorizons Spartan 3 and others (no high speed interface) > http://www.nuhorizons.com/products/xilinx/spartan3/development-board.html > > Emulation Technology System board + Ethernet module (not enough RAM > for streaming) > http://www.emulation.com/catalog/off-the-shelf_solutions/devsystems/xilinx2.html > > Does anyone know of a board which might meet my requirements? Of the > above, the Emulation Technology solution provides the closest fit, if > only it had some onboard RAM. > > Cheers > DaveArticle: 69694
According to Xilinx all blocks related to 64B/66B is impossible to use for bitrates below 10.3Gbps. In my design I would like to use the scrambler/descrambler and the Block Sync functions of the 64B/66B encoding (not the 'coding table') at ~5Gbps. In the Rx path I would also like to use the stretch buffer to get into my system clock domain. If I have to design all the 64B/66B functions in FPGA fabric a separate clock domain is needed for each Rx path of the used MGTs, I will use 8 MGTs. The only usable part left of the MGT is the serdes function. Is this true? Has anyone used the 64B/66B in a design for bitrates below 10.3 Gbps? What can the reason(s) be to not support sub 10.3Gbps? Looking at the block diagram, the interface signals and the attributes the MGT seems very flexible but ...Article: 69695
Chuck McManis wrote:
> This was part of my problem, one of the slv's was part of the input
> specification to the pwm unit (8 bits of 'current count' data), comparing an
> SLV to an unsigned gives an error message (something about 6 possible ways
> to interpret the result), even unsigned(slv) gives that error, but
> unsigned/unsigned compares work as do slv/slv compares.
use IEEE.numeric_std.all;
if ((unsigned)some_slv = some_unsigned_vector) then
...
Just convert both vectors to the same type. It cost you a little time
for typing, but a well-defined behavior for unsigned / signed data.
Ralf
Article: 69696Hi, I am designing a decimation filter and use Leonardo Spectrum for synthesis. Leonardo Spectrum give me a report of 500 fanout for my clock. The clock has a frequecy response of 50Mhz and the speed of my clock is only 1.5Mhz. I was told that Leonardo Spectrum has the ability to generate the clock buffer to reduce the load of my clock. I set the limit of my load to be .1 and it gave me a fanout of 1 for my clock. Can I trust Leonardo Spectrum for its clock buffer trere or would it induce the slew and slow rising edge on my clock? If clock buffer from Leonardo Spectrum is not reliable what is the approriate way to manually adding a clock buffer since we don't have the tool to generate the clock tree. Thanks, EngArticle: 69697
"Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0405180353.48eef0f2@posting.google.com... > > Zigbee news from Atmel - what's key here, is a move from generic > > uC/Chip sales, into also selling the Zigbee SW stack, so users have > > minimal SW developments for their links. > > Trouble is, they're using a 900MHz radio, whereas everyone else in the > ZigBee/802.15.4 world is doing 2.4GHz. > > I personally would recommend this device: > > http://www.oki.com/en/press/2004/z04017e.html > > (Disclaimer: I designed half of it ;) ) > > Cheers, > JonB Looks like a neat device from the press release. It's too bad I have no idea what the part number or ballpark price might be - it seems the press release isn't geared much for the design engineer. :-/Article: 69698
Klaus, Have you been to the Xilinx website answer search thingy? I put ERROR:Portability:90 into the search and had four answers appear. Somewhere to start. Cheers, Syms.Article: 69699
Hello everybody, For a school project I use the Xilinx Coregen FFT core. It does work, but what does the output mean? Is the Real output the amplitude and the Imaginary output the phase? If anyone knows, please HELP!!! thanks, Sander Odekerken
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