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A good reference : http://www.andraka.com/dsp.htm=20 -----Original Message----- From: Rene Tschaggelar [mailto:none@none.net]=20 Posted At: Wednesday, May 12, 2004 4:16 AM Posted To: fpga Conversation: FPGA vs Microprocessor: newbie question Subject: Re: FPGA vs Microprocessor: newbie question Jos=E9 da Rocha wrote: > Hello. > I'm new at the FPGA world. I understand that a FPGA and a=20 > microprocessor are NOT similar physical devices. (With a FPGA we can=20 > design our own digital functions) >=20 > I would like to know what are the main reasons to use a FPGA instead=20 > of a microprocessor in a real world application ? > Can anyone describe me some real world applications where the use of a = > FPGA is a more suitable solution than the use of a microprocessor and = why? There are functionalities that are better done in software and there are = others that are better done in hardware. Point of interest may be the feasibility, power consumption, required = clock speed, .. Though not generally true, the more trivial the functionality, the = simpler it is to be made in an FPGA. The more complex the functionality, = the better it is done with software. As sidenote, there are microcontrollers available to be put into an = FPGA. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups = - http://www.talkto.netArticle: 69651
> > > "Jim Wu" <NOSPAM@NOSPAM.com> schrieb im Newsbeitrag > news:R8Umc.29892$wY.21792@nwrdny03.gnilink.net... > > > in order to verify the functionality of XILINX DCM, I have generated a > > > dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is > > > embedded into a simple top-level file that only connects the testbench > > > signals (in-clock and reset (=0) to the DCM-module. The DCM reset > > > signal is always set to '0'. > > > > > > > It would help if you can post the testbench code as well. Sometimes the > > generation of the inputs to the DCM may affect the behavior simulation > > model. I've seen that DCM model does not work if the input clock starts at > 1 > > at time 0. e.g > > > > process > > clock_in <= '1'; > > wait for 10ns; > > clock_in <= '0'; > > wait for 10ns; > > end process; > > Also check time resolution of the simulation is set to picoseconds - it should be if you launch the simulation from ISE, but if you are running Modelsim "manually" you need to do vsim -t ps, r regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 69652
"john jakson" <johnjakson@yahoo.com> wrote in message news:adb3971c.0405150534.318f41d1@posting.google.com... > "Dave Marsh" <me@privacy.net> wrote in message news:<40a4ce89$0$4587$db0fefd9@news.zen.co.uk>... > > "Andy Peters" <Bassman59a@yahoo.com> wrote in message > > news:9a2c3a75.0405131635.25f8ea90@posting.google.com... > > > "Leon Heller" <leon_heller@hotmail.com> wrote in message > > news:<40a0ebc8$0$25328$cc9e4d1f@news-text.dial.pipex.com>... > > > > > Perhaps one of those BlackNdecker toaster ovens will do the job since > they were mentioned awhile back as being useable for home based reflow > ovens in another thread on BGA pcb work. > > regards > > johnjakson_usa_com Yes, I was thinking about one of those too (just as long as they don't mind running constantly for 24 or 48 hours.) DaveArticle: 69653
raj wrote:
> Hi,
>
> I have a small doubt regarding the load seen by a primary global clock
> buffer in a FPGA.
>
> My design consumes 1940 flops out of 3072,and also the load in the
> BUFGP shows only 1940 flops .I thought as the clock tree is pre-synthesized,
> no matter how many flops are consumed, the clock signal is driven to each and
> every flop.Can anybody comment,how it is disabled in unused flops so that
> clock buffers do not see the load in unused flops.Is it same for GSR??
Howdy Raj,
The tools are pretty smart about only activating the parts of the
clock tree that are needed - it is one way to save power. And yes, the
GSR would only be activated to the FF's that actually use it.
Marc
Article: 69654Hi Martin, In the past, I've kept the entity ports as slv, just using unsigned etc. within the architecture. Partly because of reuse, easier for others to understand on a multiple person team, etc. Now that numeric.std has been standardised, I wonder if there's a reason to do this anymore? cheers, Syms. "Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:ulljrl4f2.fsf@trw.com... > Why not define these as "unsigned(31 downto 0)"? You're representing > real numbers after all, not just large collections of bits (which is > all a std_logic_vector implies). >Article: 69655
Two months after Xilinx acquired Triscend, it now seems they are planning to kill the Triscend products. We recently got the End-of-life notification for the A7 processor, and I guess the E5 is also going. Can anybody guess what their plans might be? What is the point of buying a company and dropping the products? Except for the purpose of getting irritated customers who will get enourmous redesign work using some other processor. I can't imagine that Triscend was a very big threat to the Microblaze market, to warrant shutting it down just to kill the competition. Does anybody know of a replacement for the Triscend A7 processor? We are using it together with a Xilinx FPGA (at least until now...) and have implemented a FIFO in the CSL to move data at high speed from the FPGA to external SDRAM (Up to 128 Mbits/second in packets of 8 32-bit words). This link seems to be difficult to implement using a "standard" ARM7 processor. Any suggestions and views are appreciated. /AndersArticle: 69656
Hello all... I am using a Xilinx Vitex II FPGA to unwrap a G.709 signal (OTU1) and output the underlying STM-16 (or other CBR2G5 signal). The synchronous payload case is easy- I can use a DCM to generate a clock from the incoming data's recovered clock, and use that to clock out the data from an asynchronous FIFO filled by the unwrapping logic. However, the asynchronous payload case seems undoable to me within the FPGA. Since the asynchronous payload could vary by +/- 65 ppm from the equivalent synchronous payload, I need to use the asynchronous data to generate a new clock, or use FIFO level measurement to fine tune the frequency of the outgoing clock. If I try to use the clock derived from the input clock, the FIFO could at worst start to over/underflow after about 1/10th second. Lastly, if it really can't be done in an FPGA, what type of part could be used in tandem that would allow clock generation from a data stream that is accompanied by a valid signal? Thanks!Article: 69657
Anders wrote: > Two months after Xilinx acquired Triscend, it now seems they are planning > to kill the Triscend products. We recently got the End-of-life > notification for the A7 processor, and I guess the E5 is also going. > > Can anybody guess what their plans might be? What is the point of buying a > company and dropping the products? Except for the purpose of getting > irritated customers who will get enourmous redesign work using some other > processor. > > I can't imagine that Triscend was a very big threat to the Microblaze > market, to warrant shutting it down just to kill the competition. > > Does anybody know of a replacement for the Triscend A7 processor? We are > using it together with a Xilinx FPGA (at least until now...) and have > implemented a FIFO in the CSL to move data at high speed from the FPGA to > external SDRAM (Up to 128 Mbits/second in packets of 8 32-bit words). This > link seems to be difficult to implement using a "standard" ARM7 > processor. > > Any suggestions and views are appreciated. > > /Anders > > > I did some design on Triscend A7. Very powerfull system, with their FAStchip software. Maybe, Xilinx wants to play in the TRUE Embedded world ! Merging Triscend software/hardware know-how with Coolrunner II techno, you move to a true SoC platform for Embedded porducts -> high speed and low power ! Buying Triscend, Xilinx may enter in the Embedded market very quickly. Laurent www.amontec.comArticle: 69658
Hello, I am a junior FGPA designer and am planning on attending some training to improve my design skills and FPGA knowledge. Can someone tell me if the courses offered by Xilinx are good courses? I am looking into the FPGA design flow (not VHDL classes) with courses like fundamental of FPGA design, designing for performance etc etc... Can anyone suggest other(better?) training classes for xilinx FPGA design Thanks a lot...Article: 69659
In the schematic editor menu bar go to: Options Export Netlist... In the save dialog box pull down the "Files of type" drop-down list and select "Vhdl [*.VHD]" This will take the project netlist and generate VHDL code. "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message news:<Rm5731$OEHA.2304@exchnews1.main.ntu.edu.sg>... > Hello, > > There are some schematic files (*.sch) developed using Xilinx Foundation > 4.2. > I am going to use those file using 3rd party software, which does not > recognized *.sch. > > Is there such away so that i can convert those *.sch files to *.vhd > files ? It seems like i could not find that function in Xilinx > Foundation 4.2 > > Kindly please advice. > > Thanks, > > -Basuki-Article: 69660
Hey Chuck, Always good to hear from fellow roboticist. I have read some CMU documentation but nothing about blob analysis. I had believed that the CMU can only track one blob whereas I need to collect data about lots of blobs. Center of gravity is good. Long axis, area, etc. If you suggest I will look deeper into the CMU docs and web sites. Thanks. What is iso-bar? On one of your other post you are comparing a std_logic_vector to another. I suggest you repost and state what libraries you are using. I remember a difficulty in the original VHDL spec that didn't allow for this that may have been patched up by a library. VHDL has been a work in progress for many years with most improvements added via libraries. Brad AiVision.com "Chuck McManis" <devnull@mcmanis.com> wrote in message news:IEypc.67566$HV1.30587@newssvr25.news.prodigy.com... > > "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message > news:10ad0596rrmu4da@corp.supernews.com... > > What I did for Google was this: > > > > FPGA OR ASIC "blob analysis" > > > > which gave about 165 hits, but none of them seem to > > point me in the direction of any source code or even to > > any theoretical discussions. If you think I should > > try another search then please do suggest something. > > Are you trying to what the CMU CAM does? Have you read the CMU papers? Blob > analysis doesn't mean anything to me so I'm guessing here, but perhaps you > meant center-of-mass type things? > > The image processing stuff is generally DSP based as the algoritms are to > delineate an area using a standard convolver algorithm and then to track its > "center of mass" using standard graphics techniques for finding the center > of a polygon. (See Eberly's FAQ for that code). > > Off the top of my head I'm guessing you could do some clever stuff whereby > you keep an array of pixels in a the block ram of an FPGA, and use some form > of iso-bar type system to connect regions with similar pixels. I'm not sure > what the logic would look like, something like > > for (pixel = 2048 downto 0) > begin > if ( NEIGHBOR(0,pixel) or > NEIGHBOR(1, pixel) or > NEIGHBOR(2, pixel) or > NEIGHBOR(3, pixel) or > ... > NEIGHBOR(7, pixel) ) then > group[pixel] <= group_id; > group_id++; > end if; > end for; > > Like I said, I'm no expert. Basically you want logic that creates a > comparator whose inputs are the logically adjacent pixels for each > individual pixel, and a second array which is the group membership function > (in or out). If you set a specific criteria for membership (like the pixel > is a particular color) then this will probably work for you. > > Then on each vertical retrace you need to compute the center of mass of > pixels in the "group." > > --Chuck > > > >Article: 69661
"Symon" <symon_brewer@hotmail.com> wrote in message news:<2gpvqkF5g3ujU1@uni-berlin.de>... > Hi Ed, > Well, if you use a DCM to manage your on chip clock, you should be able to > adjust the timing to whatever you want. For example on the output side, you > can set the DCM to eliminate any phase difference between the on-chip clock > and the SDRAM's clock. Use the IOB's output FFs. Then the delay introduced > by the FPGA is simply the 'clock CLK to PAD' IOB output delay, specified in > the data sheet, (<2ns at a guess), assuming you meet the setup > specification. Also, you can fiddle about with the DCM phase shift to > further optimise things, have a play! As for getting the data into the chip, > you need to consider the 'Pad to I output' .... etc.. > It's all in the manuals! > Cheers, Syms. If you are only adding one clock delay through the part, the input setup timing is important, too. Time from an input pad to an output flip-flop can be quite large depending on the pinout. You need to constrain input setup time which can be done globally in the .ucf file for the common clock signal like: OFFSET = IN 3 ns BEFORE "DRAM_CLK"; If your design is allowed two clock delays, using input and output flip-flops will no doubt do the trick, however with one clock delay you would need to balance input setup time against clock-to-output. In this case you may find that using an internal flip-flop gives a better balance, especially if the input and output pins are not near eachother. Another note on single-stage delays. When you tell the tools to place a flip-flop in the IOB, and the flip-flop's input and output connect to two pads, the tool will choose on its own whether to place it in the input or output IOB. Forcing the flip-flop to the other location would seem to be possible by placing a library component like OFD or IFD to specify the IOB, however an inspection of these macros shows they simply have a flip-flop with IOB=TRUE. To force the flop into the output I've found I have to place a flip-flop without IOB=TRUE and then enable packing registers into IOB for outputs only in the mapping options.Article: 69662
If you're using the recovered clock in an ITU compliant system requiring very small jitter, take a look at the icst.com clock recovery products to see about filtering a telecomm clock. They have SAW-based products that can keep jitter within spec. A Numerically Controlled Oscillator can produce your desired STM-16 payload frequency when you supply frequency adjustments based on your FIFO depth. That NCO can either generate a digital sinusoid and use a D/A to generate a sine wave at your desired output frequency or the MSbit of the NCO can be used to produce a jittered clock that is cleaned up by a PLL like the ones I mentioned from icst.com; less stringent jitter requirements need less expensive chips. If you only need to generate synchronous data and clock, don't bother recovering the clock but send out a gated clock with your gated data. So - what do you *need*? "Daniel Gowans" <chlump@yahoo.com> wrote in message news:Xns94EC73A2829D9chlumpyahoocom@198.60.22.31... > Hello all... > > I am using a Xilinx Vitex II FPGA to unwrap a G.709 signal (OTU1) and > output the underlying STM-16 (or other CBR2G5 signal). > > The synchronous payload case is easy- I can use a DCM to generate a clock > from the incoming data's recovered clock, and use that to clock out the > data from an asynchronous FIFO filled by the unwrapping logic. > > However, the asynchronous payload case seems undoable to me within the > FPGA. Since the asynchronous payload could vary by +/- 65 ppm from the > equivalent synchronous payload, I need to use the asynchronous data to > generate a new clock, or use FIFO level measurement to fine tune the > frequency of the outgoing clock. If I try to use the clock derived from > the input clock, the FIFO could at worst start to over/underflow after > about 1/10th second. > > Lastly, if it really can't be done in an FPGA, what type of part could be > used in tandem that would allow clock generation from a data stream that is > accompanied by a valid signal? > > Thanks!Article: 69663
Hi Erik, Another roboticist. Thanks so much. You are exactly right. I want an algorithm that is in sync with the pixel clock. This is generally how I think about and build all my algorithms. And so I would generally expect to keep a several lines of binarized data in the FPGA but not an entire frame. Or perhaps we could use line scan cameras and not be thinking in terms of frames at all. I could imagine having up to 100 blobs on any line and I don't see why I should limit myself there. The maximum number of active blobs would be one half the horizontal resolution. I have done some armchair thinking about how to keep and combine blobs if they should merge in susbsequent lines. This may be done by keeping start and stop points of the various blobs in a RAM LUT. But maybe this isn't the best approach? I saw mention of run length encoding in a web page by Wintress. I do not know what advantage that encoding has over a fifo that would give you the pixel threshold on every pixel clock. I do know that some camera manufacturers like Basler make cameras that threshold and run length encode their outputs presumably to cut down on cable bandwidth. I am not sure what you mean by the term non-convex. To a newbie that is concave but you don't use the word concave so perhaps this has a different meaning. I have also come across 4 neighbor or 8 neighbor terminology which I assume represent the rules for making a connection, based on a tic-tac-toe arrangement of pixels. I would suppose that the 8 neighbor approach would be a tad more robust but may lead to narrowly connected blobs with only a point in common. Whis is better? I do not need to "track across images" if you are talking about some sort of temporal tracking from one frame to the next. On my web searching I have tried to refine my search to just source code by using unique VHDL keywords like downto and inout. However I didn't find anything with this search: downto inout blob. Any suggestions to better search techniques or Verilog keywords will be appreciated. Do you want to share with the group what Birger does? Brad Smallridge AiVision.com "Erik Widding" <widding@birger.com> wrote in message news:afe40eec.0405161128.75b173ca@posting.google.com... > "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote... > > I have been doing some investigation into blob analysis algorithms > > and would like to know if there are any designs that have been > > rendered into FPGAs. > > Brad, > > We are doing some work in this area for a robotics application. When > we first started our investigation of the literature, we found that > the existing implementations did not meet with our requirements for > implementation in an FPGA. > > In our system we require that the pixels be presented to any image > processing engine only once, or we will get killed on memory > bandwidth. Most of the existing literature details algorithms that > are stack based that iterate through the image in a pattern that can > not be known a priori. Additionally, these algorithms tend to > require a variable amount of time, depending on the number of blobs > that are identified, and the shapes of these blobs. > > A run length encoding approach, which I have seen detailed in the > literature, is a good starting point for the requirements that we had, > especially since we could ignore non-convex blobs in our application. > Though, it should be noted, a linescan blob finder can find non- > convex blobs, as long as it is capable of merging two or more blobs > that are found to overlap later in the image. > > For any discussion to go forward, it would be helpful to understand > what your requirements are. If this is a commercial application, > please feel free to contact me offline, as we may be able to adapt > an existing core from our library. > > If this is to be a public exercise, please offer the group an idea > as to the following: > performance requirement > application > maximum number of objects that you wish to find in a given image > whether you need to just find objects, or track across images > do you need to find non-convex blobs? > > Blobfinding can be done in guaranteed time in a linescan fpga > implementation, the details of the implementation are highly > dependent upon the answers to the above questions. > > > Regards, > Erik Widding. > > --- > Birger Engineering, Inc. -------------------------------- 617.695.9233 > 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.comArticle: 69664
Hi, I have to design a low pass filter in VHDL. How can one go about designing such a filter when the medium is event driven and time domain based?? How should one decide on the filter characteristics if we just know the symbol time rate. If I am using standard VHDL and not AMS is it possible for me to design such a filter which is used in the recovery loops of receiver? Most of the references on filter and digital communications refer to frequency domain analysis. How can I go around this problem? If the input is a pulse then a low pass filter is an integrate and dump. However if I have a sampled sine wave how could I design a low pass filter? Could you please reply and let me know? I would grealty appreciate your reply. Looking forward to your replies, Thanks Viswanath PS: I would be needing a filter after the mixing of two sine waves to filter out the higher frequency componentsArticle: 69665
raj wrote: >Hi, > >I have a small doubt regarding the load seen by a primary global clock >buffer in a FPGA. > >My design consumes 1940 flops out of 3072,and also the load in the >BUFGP shows only 1940 flops .I thought as the clock tree is pre-synthesized, >no matter how many flops are consumed, the clock signal is driven to each and >every flop.Can anybody comment,how it is disabled in unused flops so that >clock buffers do not see the load in unused flops.Is it same for GSR?? > > The clock tree GOES out to every FF, but it doesn't get CONNECTED to the FF unless that flop needs that clock. So, there is some capacitive loading from the stubs, but not the loading of the FF's inputs on the flops not clocked from the GCLK. Anyway, one can presume Xilinx has run all versions of the chip with every FF on the entire chip clocked from the same GCLK, just to make sure the clock tree can handle that. JonArticle: 69666
Dave Marsh wrote: >"Leon Heller" <leon_heller@hotmail.com> wrote in message >news:40a0ebc8$0$25328$cc9e4d1f@news-text.dial.pipex.com... > > >>Reflow soldering without baking them (probably 120 C for 24 hours) might >>give problems. Hand soldering should be OK: I never have problems, anyway. >> >>Leon >>-- >>Leon Heller, G1HSM >>http://www.geocities.com/leon_heller >> >> >> > >Thanks Leon. That's interesting, as the first few are going to be hand >soldered (and I don't have a proper oven at the moment). > > I also have been hand-soldering various Xilinx and other chips for years. I've done Xilinx Spartan FPGAs in the PQ208 package without any problems, and 9500 and Spartan parts in the PC84 also. The chip never gets very hot in this process, maybe some local areas around the edge reach 100 C when I'm having trouble and clearing out some solder bridges. This is nowhere near the temperatures maintained when IR reflow soldering boards full of these components. Now, the lead-free stuff will push these processes to even higher temperatures. JonArticle: 69667
Alessandro, The external interrupt will not require drivers like other peripherals. It will, however, require an isr defined in your user application. I can send you an example project that does just this. Pls email me off-list and I can send it to you. Matt Alessandro Scaglione wrote: > Thanks for your answers, > > in Xilinx forum > http://toolbox.xilinx.com/cgi-bin/forum?50@60.SnQlabZvfnD.5@.ee82b9c I > read that someone uses uartlite driver instead generic driver to handle > interrupts. > > Another question on external interrupts: > I need to write a device driver for extenal interrupts, too?Article: 69668
I want my master input clock, which is on a dedicated pin, to clock most of my logic through a BUFG. I also want it to drive a CLKDLL so I can use the CLK90 output. After much head-banging I assert the following: On a Spartan IIE, an IBUFG output cannot be routed to both a CLKDLL input AND a BUFG input simultaneously. Synplicity will synthesize this setup beautifully, but the Xilinx Placer won't accept it. Yes, I know I could use the CLK0 output through a BUFG instead of my original clock, but my input clock can change speeds abruptly, which will cause the CLKDLL to unlock and exhibit undefined behavior until relocked. This makes me nervous and I'd rather just use my original input, thank you. A double mocha to he or she who can disprove my assertion. -tdArticle: 69669
Anders wrote: > Two months after Xilinx acquired Triscend, it now seems they are planning > to kill the Triscend products. We recently got the End-of-life > notification for the A7 processor, and I guess the E5 is also going. > > Can anybody guess what their plans might be? What is the point of buying a > company and dropping the products? Except for the purpose of getting > irritated customers who will get enourmous redesign work using some other > processor. > > I can't imagine that Triscend was a very big threat to the Microblaze > market, to warrant shutting it down just to kill the competition. > > Does anybody know of a replacement for the Triscend A7 processor? We are > using it together with a Xilinx FPGA (at least until now...) and have > implemented a FIFO in the CSL to move data at high speed from the FPGA to > external SDRAM (Up to 128 Mbits/second in packets of 8 32-bit words). This > link seems to be difficult to implement using a "standard" ARM7 > processor. > > Any suggestions and views are appreciated. > > /Anders I think Triscend was much less a threat to the MicroBlaze, than ARM offering a licensable ARM+FPGA flow, was to the FPGA market. This is also topical, from Altera : http://www.eet.com/semi/news/showArticle.jhtml;jsessionid=4H3QWGS4JU0YAQSNDBCSKHQ?articleID=20301002 " It now says it won't come out with a successor to its Excalibur line, which includes a hardwired ARM processor core. Excalibur is based on the company's older Apex FPGA architecture. The company said it prefers the flexibility of soft processor cores, which can handle more tasks at various points in the FPGA fabric. "We learned that putting in a hard core is tricky," Plofsky said. My reading was always that these 'System on Chip' offerings were more marketing and ego driven, than sound engineering decisions. "jack of all trades, master of none" is what you get, and they struggle to hit critical mass, so the big hurdle is not the first device, but getting to the 'next iteration'. [Atmel FPslic anyone ? ] So, you are left looking at Standard ARM offerings, and FPGA, or maybe NIOS II (etc). What you should do depends on your CPU/FPGA/Memory relative loadings. There are a LOT of Arm cores comming as MCU, with on chip FLASH, and that solves the smaller-memory end, by removing the memory BUS layout problems. Look at Philips LPC2xxx, STm STR7xxx, Analog Devices ADuC7xxx, TIs TMS470, Sony, etc for FLASH+ARM offerings, many with external memory interfaces. Then, there are the ARM MPUs (external code memory), with Atmel AT91RM9200, up to Intel's XScale families. What WOULD make sense, is a highspeed serial interface layer, on these ARM MCUs, so they can interface with FPGAs with reduced pin count :) - The SSC/i2s could approach that. Following that idea, a peek at Atmel's 9200, gives the MII interface at 100Mbaud, or the devices triple SSC/i2s channels as LPC-FPGA candiates. SSC specs as <= MCK/2, and I think MCK is 209MHz, so over 3 channels that's a peak of ~300MBaud ARM<->FPGA on a few pins. Might get close to your link needs ? -jgArticle: 69670
davegoogle99@hotmail.com (Dave) wrote in message news:<1c21ab5c.0405170251.671c1c4a@posting.google.com>... > > Does anyone know of a board which might meet my requirements? Of the > above, the Emulation Technology solution provides the closest fit, if > only it had some onboard RAM. > > Cheers > Dave I believe this board is made by Digilent, redistributed by Emulation. Digilent also sells SRAM expansion boards. WillArticle: 69671
Donald, Zigbee news from Atmel - what's key here, is a move from generic uC/Chip sales, into also selling the Zigbee SW stack, so users have minimal SW developments for their links. This will be key to their AVR sales, very like CypressMicrosystems promote their PsOC - they include Sw support flows, so customers need less skills. http://www.atmel.com/dyn/corporate/view_detail.asp?FileName=Zigbee.html http://www.atmel.com/dyn/resources/prod_documents/5056S.pdf $6.75/100K for a chipset is not super-cheap, but from a NZ standpoint, the Zigbee solution is probably better than Bluetooth. Zigbee is slower, but gives more range, and suits Alarms, Security, Wireless Logging and similar near-field applications. Would likely also make a great marine-instrumentation link on boats, for non-graphical interfaces. -jg Any price showing on the AT89S8253 yet ?Article: 69672
Fred,
Yes, I do remember you. We hit a couple of the wineries that Friday
afternoon with you. I realize now that I was also ambiguous. I meant why
generate a random netlist. I guessed it was for something with doing
studies with PAR, but wasn't sure.
Fred Ma wrote:
> Fred Ma wrote:
> > I'm actually not trying to model the ALU-like cell. I'm trying to
> > generate random netlist of those cells. However, a completely
> > random net list is not realistic.
>
> Ray Andraka wrote:
> > Why?
>
> Hi, Ray,
>
> Not sure if you remember, but we met (I think at FCCM) a few
> years back. Hope things are going well with you.
>
> Why am I trying to generate pseudorandom netlists? I'm testing out a
> placement algorithm for ALU arrays.
>
> Why is a random netlist not realistic? Designs usually have some kind
> of hierarchy (effective hierarchy, even if not explicit). I'm not an
> expert in this area, but I've looked at a few papers on graph
> clustering algorithms. Hierarchical information is often captured as
> a rooted tree, where each internal node represents a subgraph of the
> netlist with a somewhat minimal cutset (compared to an arbitrarcy cut
> at the same level of clustering). A truly random graph will probably
> not have the same degree of hierarchical structure. You can still
> force-feed it into a clustering algorthm to impose hierarchy, but the
> criteria for choosing subgraphs will probably not be that distinct
> between candidate subgraphs.
>
> Intuitively, I don't expect a totally random graph to be easily
> placable because there's too much random interdepedence between
> arbitrary nodes. A real netlist has more localization of
> interconnect.
>
> I'm currently looking through some papers on the topic of random graph
> generation by Hutton & Pistorius (upon their recommendation).
> However, they are meant for FPGAs, whereas the cell I mentioned in my
> original post is quite different. There are far fewer of them in a
> circuit, and there are many more inputs. I'm trying to get some
> guiding considerations to cobble my own quick-and-dirty code in
> matlab.
>
> Fred
> --
> Fred Ma, fma@doe.carleton.ca
> Dept. of Electronics, Carleton University, Ottawa, Ontario, Canada
> *| If I don't reply to your email, please sent it again. I may |*
> *| have erased along with the deluge of post-filter spam. |*
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 69673"Tony Dean" <td@emu.com> wrote in message news:33aa9b10.0405171520.7798497d@posting.google.com... > I want my master input clock, which is on a dedicated pin, to clock > most of my logic through a BUFG. I also want it to drive a CLKDLL so I > can use the CLK90 output. > > After much head-banging I assert the following: > On a Spartan IIE, an IBUFG output cannot be routed to both a CLKDLL > input AND a BUFG input simultaneously. > > Synplicity will synthesize this setup beautifully, but the Xilinx > Placer won't accept it. > > Yes, I know I could use the CLK0 output through a BUFG instead of my > original clock, but my input clock can change speeds abruptly, which > will cause the CLKDLL to unlock and exhibit undefined behavior until > relocked. This makes me nervous and I'd rather just use my original > input, thank you. > > A double mocha to he or she who can disprove my assertion. > > -td Tony, You should be able to do this: Connect the IBUFG to a BUFG. Connect the DLL input to the output of that BUFG. Use another BUFG on the DLL's 90deg output. BobArticle: 69674
I believe in VHDL you can create in effect a global signal by declaring it in a package and then including that package in all the places you want the scope of that signal to go. I think most synthesizers will choke on it, but for simulation/testbench it might be workable. -JCC
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