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Hi,
thank you about your reply.
But what about .vho file. What is this file for?
Rgds
Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0405101246.38545bef@posting.google.com>...
> ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0405100255.9edda8b@posting.google.com>...
> > Hi newsgroup people,
> >
> > I want to perform a timing simulation of an SRAM controller with
> > Modelsim (version Altera 5.7e)
> >
> > I am working with Altera QuartusII software (version 4.0 SP1).
> >
> > For the purpose of a timing simulation under Modelsim I would like to
> > know how to make settings in QuartusII to get the correct output files
> > and how to include them in Modelsim.
>
> I'm sure this is all documented somewhere, so it's clearly time to
> RTFM.
>
> Basically, the fitter spits out a Verilog or VHDL model of your
> design. This model has the port interface, but the innards are
> replaced with the particular FPGA's low-level features and the proper
> interconnects. By default, Quartus puts this file in the
> <design_root>\simulation\modelsim directory. Look for designname.vo.
> You'll also find the SDF (delay file) in that directory; it's called
> designname_v.sdo.
>
> Back to modelsim. Add the .vo file to your project, and compile it.
> [You may have to go in and edit out the line: initial
> $sdf_annotate("designname_v.sdo"); ModelSim complains about it) Then
> edit the simulation configuration and tell it to use designname_v.sdo
> with your chip design. I like to set all of the delays to MAX (I've
> been bitten by back-annotated simulations using "typical" delays.)
>
> Like I said, I'm sure that Altera's documention can tell you how to do
> this.
>
> -a
Article: 69426Bassman59a@yahoo.com (Andy Peters) writes: > I would imagine that the skills required to write an effective > FPGA-fitting algorithm are beyond those of the typical open-source > hacker. You should take a look at the source code for gcc sometime ;) > If such a hacker exists, then it seems to me (s)he'd be better off > working for Altera or Xilinx (or Mentor or Synplicity or Synopsys) > getting paid real money. Perhaps if you were in my shoes, you would have made that choice. I did not. ;) > I *do* care if they don't work, or are inadequate, because I have > work to do! If you're really pushing the limits of what reconfigurable logic can offer, the tools will *never* do everything you want. The question then becomes whether or not you will get sued for improving the tools to meet your needs. - aArticle: 69427
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:40A01F19.EDA80D9F@yahoo.com... > Tom Hawkins wrote: > > > > jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405070500.7c9c4bcc@posting.google.com>... > > > > Also, what's the status of open source tools? (I like to tinker on > > > > the software end of things, too, and I have a bad case of PowerBook > > > > envy, and I haven't seen any software available other than x86 and > > > > big-iron UNIX). Can they go from VHDL/Verilog all the way to > > > > downloading the file to the chip? I see that compilation (Icarus > > > > verilog) and downloading (found it in this group's FAQ) work, but what > > > > about place and route? Icarus' docs say it's a no-go for this; is > > > > there anything else, or must I use the Xilinx tools? (I guess I have > > > > a Xilinx bias -- it's all I've used, and I don't see much else for > > > > cheap development boards.) > > > > > > Why bother with Open Source stuff when various incarnations of > > > commerical tools are free to use? > > > > Because in the long term, an open-source tool chain can out perform a > > commercial tool. Case in point: how many Unix/C developers compile > > with a commercial alternative to GCC? > > I have been evaluating tools for the ARM MCU and all my info says that > gcc is a less efficient tool than the commercial ones. I guess it only What do you mean by "less efficient" ? There are big differences between run-time efficiency and develop-time efficiency, and the balance choosen between these will vary according to user and project. There is little doubt that there are commercial compilers that produce smaller and faster code than gcc for many processors (including arm), but developer efficiency can be a serious issue too. I write C code for five different processors, amongs other work - it is simply not economically feasible to buy top-of-the-range commercial compilers for all of these, while gcc works fine for me. I also find it in many ways to be a more advanced compiler than some compilers I have used (especially in terms of compile-time error checking). There are plenty of cases where commercial compilers would make most economic sense overall, but it is far from every case. > stands to reason that the commercial tools must be better, why else > would they sell well enough to keep the companies in business? > There is one, and only one, reason why any company stays in business - it is able to persuade enough people that its product is worth the money. It may or may not be the case that the product actually *is* worth the money (to the given customer), but the immediate technical qualities of the product are only one part of the sale - there are many other relevant issues such as support and upgrade paths, and many irrelevant issues such as the persuasiveness of the salesfolk, the guilibitity of the purchasing people, and the quality of their flashy power-point slides and free pens. I'm not trying to say that commercial compilers are not worth the money - I'm just pointing out the naivity of the "it costs more so it must be worth more" argument.Article: 69428
rickman <spamgoeshere4@yahoo.com> writes: > Tom Hawkins wrote: > > <snip> > > tools has been dismal. Icarus is the only open-source tool I know > > that attempts Xilinx synthesis. I believe it handles synthesis and > > technology mapping, but has little, if no optimization. > > I think John Jakson summed it up pretty well, open source FPGA tools are > not practical for a number of reasons that have been discussed here many > times before. Some people seem to think that FPGA and ASIC tools are > the same as compiliers, but in reality they are very different. > I think there's also the point that the intersection of the sets "compiler users" and "can write (and is interested in writing) software" is much larger than that for "FPGA place and route tool users" and the "writing software" sets. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69429
"jtw" <wrightjt @hotmail.invalid> writes: > Allan & Jason B. show the typical ways; alternatively, if you are using > numeric_std, you could write: > > counter <= std_logic_vector(to_unsigned(0,27)); > Personally, if I'm doing a counter I would use an unsigned type (or even an integer!) rather than "casting" to std_logic_vector all the time. After all, what you're representing is a number... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69430
hi,
can anybody here tell me how to instantiate an edn module with ise 6?
i tried so, but it didnot work:
.........
component uart_tx is
port ( din : in STD_LOGIC_VECTOR (7 downto 0);
write : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
en_16_x_baud : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC;
buffer_full : out STD_LOGIC);
end component;
begin
inst_uart_tx : uart_tx port map(
din => din;
write => write;
reset_buffer => reset_buffer;
en_16_x_baud => en_16_x_baud;
clk => clk;
serial_out => serial_out;
buffer_full => buffer_full);
.........
uart_tx is the name of the edn module. it is in the same directory as
the project's.
thanks.
with greeting
Article: 69431(My biggest pet-peeve is > FPGA synthesis. FPGAs have had dual-port RAMs for ~7 years now, yet > we still can't infer dual-port block RAM from HDL. Arggh!) Yes you can. > One hurdle to open-source synthesis and place&route is proprietary > architectures. The major FPGA vendors refuse to disclose the > underlying details needed to for a quality PAR tool or physical > synthesis. Well Magma & Synplicity seem to have got enough information to be able to make physical synthesis tools. > What can we do to improve open-source EDA? Nothing, hopefully. Some of us would still like to be able to earn a decent living from writing software, you know? ;) Cheers, JonBArticle: 69432
Hello. I’m new at the FPGA world. I understand that a FPGA and a microprocessor are NOT similar physical devices. (With a FPGA we can design our own digital functions) I would like to know what are the main reasons to use a FPGA instead of a microprocessor in a real world application ? Can anyone describe me some real world applications where the use of a FPGA is a more suitable solution than the use of a microprocessor and why? Thank you very much for your answer José da RochaArticle: 69433
hi all, I m looking for a FPGA with a SPI interface. The SPI interface needs to be able to send data at a high rate (10 Mbit/s). regards StijnArticle: 69434
José da Rocha wrote:
> Hello.
> I’m new at the FPGA world. I understand that a FPGA and a microprocessor are NOT
> similar physical devices. (With a FPGA we can design our own digital functions)
>
> I would like to know what are the main reasons to use a FPGA instead of a
> microprocessor in a real world application ?
> Can anyone describe me some real world applications where the use of a FPGA is a
> more suitable solution than the use of a microprocessor and why?
Howdy José,
This sounds a little too much like homework, so I'm not going to
completely answer your questions. I will give you a real-world example,
and hopefully *you* can explain why the FPGA is more suitable:
Suppose you need to design a simple card whose sole purpose is to block
Ethernet packets that begin with the byte 0xFF. Assume packets are 1500
bytes long and arriving at a full gigabit Ethernet rate (nearly 1000
Mbit per second when using large packets).
Why would an FPGA be more suitable? Items of interest: data bus speed
(vs. data bus width) and the number of processor instructions and bus
cycles required to get a packet DMA'ed into memory, inspect the first
byte, and then DMA'ed back out of memory.
Have fun,
Marc
Article: 69435Which VHDL Standard is supported by the Xilinx ISE 6.1 tool. I belive that there are 4 standards. 1987 1993 2000 2002 Regards SimonArticle: 69436
I don't think there are any FPGAs that have a hardwired SPI interface, if they
did it would be for programming. That said, any FPGA can be programmed with
an SPI interface. The interface is fairly simple to implement, and 10 Mbit/s
is easy to achieve. If you mean to use the SPI as a programming interface to
the FPGA, you'll have to use an external device to convert the SPI to one of
the programming formats recognized by the FPGA. A CPLD is sufficient for that
task.
Stijn Goris wrote:
> hi all,
>
> I m looking for a FPGA with a SPI interface. The SPI interface needs to be
> able to send data at a high rate (10 Mbit/s).
>
> regards
> Stijn
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 69437rickman <spamgoeshere4@yahoo.com> wrote in message news:<40A01F19.EDA80D9F@yahoo.com>... > Tom Hawkins wrote: > > > > jon@beniston.com (Jon Beniston) wrote in message [snip] > > > > > > Why bother with Open Source stuff when various incarnations of > > > commerical tools are free to use? > > > > Because in the long term, an open-source tool chain can out perform a > > commercial tool. Case in point: how many Unix/C developers compile > > with a commercial alternative to GCC? > > I have been evaluating tools for the ARM MCU and all my info says that > gcc is a less efficient tool than the commercial ones. I guess it only > stands to reason that the commercial tools must be better, why else > would they sell well enough to keep the companies in business? Certainly when a compiler targets a specific architecture, it can do a better job. But in terms of the number of supported platforms and its decent code optimization, it's hard to beat GCC. > > > > Unfortunately, the track record of open-source FPGA implementation > > tools has been dismal. Icarus is the only open-source tool I know > > that attempts Xilinx synthesis. I believe it handles synthesis and > > technology mapping, but has little, if no optimization. > > I think John Jakson summed it up pretty well, open source FPGA tools are > not practical for a number of reasons that have been discussed here many > times before. Some people seem to think that FPGA and ASIC tools are > the same as compiliers, but in reality they are very different. Sure the algorithms are different, but there are many similarities: Like a compiler, most logic optimizations are NP-complete, therefore many of the same strategies can be applied. Both a compiler and a synthesizer deal with dataflow analysis and resource allocation. Instruction reordering is similar to retiming. Memory and execution timing tradeoffs are somewhat analogous to tradeoffs with area and performance. I agree the closer you get to implementation, the less pratical an open source tool becomes. But where is the line drawn? Clearly synthesis falls on our side. Multi-chip partioning is certainly possible. And with the capabilities of UCF, I would argue placement is a canidate as well. > > > > I did start a Virtex2 packer/placer awhile back. I got as far as > > parsing the post-synthesis EDIF netlist and building a graph of FPGA > > primitives. The goal was to pack and place the CLBs, then update the > > UCF with LOC constraints. I still have the code lying around in case > > anyone is interested. > > > > BTW, Confluence can compile it for Mac X. It will solved your design, > > simulation, and verification problems, but for FPGA compilation, > > you're still locked into commercial tools. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 69438
Hi,
Here's a different but similar question: Is there a better way to do
the following (vector extension):
signal A,B: std_logic_vector(10 downto 0);
signal X: std_logic_vector( 7 downto 0);
A <= "000" & X; -- sometimes I use this
B <= (others => '0'); -- I've also tried this
B(7 downto 0) <= X;
Regards,
-rajeev-
-----------------------
"jtw" <wrightjt @hotmail.invalid> wrote in message news:<e2Xnc.7079$D17.4291@newssvr27.news.prodigy.com>...
> Allan & Jason B. show the typical ways; alternatively, if you are using
> numeric_std, you could write:
>
> counter <= std_logic_vector(to_unsigned(0,27));
>
> I have found this format useful on occasion where I want to load a constant
> that is not all 0's or all 1s.
Thanks for the tip. Handy indeed.
> Jason T. Wright
<...>
Article: 69439Jon Beniston wrote: >>One hurdle to open-source synthesis and place&route is proprietary >>architectures. The major FPGA vendors refuse to disclose the >>underlying details needed to for a quality PAR tool or physical >>synthesis. > > > Well Magma & Synplicity seem to have got enough information to be able > to make physical synthesis tools. Does Magma make tools for FPGA? I thought they were just asic oriented. Anyone who used it for FPGA care to comment? -JeffArticle: 69440
I have twenty Xilinx XC9572XL VQFP64. Their sealed package has been open two months, and stored in an office with no temperature/humidity control. Now I want to get these devices soldered in for a pre-production run. If I put these in without carrying out a baking cycle am I asking for trouble? What are the likely effects due to moisture, and what are people's real-life experiences? Many thanks, DaveArticle: 69441
Siddharth Rele <siddharth.rele@xilinx.com> wrote in message news:<40A01D4E.3040203@xilinx.com>... > Hi Dave: > > Have you tried using the -lc -lm -lc instead of -lm ? If this does not > fix your problem, could you send the entire error log instead of just a > snippet. > Usually the first error is of most interest. Cheers, JonBArticle: 69442
" > Anyone who know any good web based forums for FPGA developers??? http://groups.google.co.uk/groups?hl=en&lr=&ie=UTF-8&oe=UTF-8&group=comp.arch.fpga is pretty good. Cheers, JonBArticle: 69443
I want to use a RTL8019 chip and want to interface it with a SPI bus (datasheet: ftp://210.51.181.211/cn/nic/rtl8019as/spec-8019as.zip). I 'm having trouble finding a good way to make the SPI communication. Someone stated that an FPGA could do the conversion. Maybee you have a better idea? kind regards Stijn "Ray Andraka" <ray@andraka.com> wrote in message news:40A0CD8A.EF088741@andraka.com... > I don't think there are any FPGAs that have a hardwired SPI interface, if they > did it would be for programming. That said, any FPGA can be programmed with > an SPI interface. The interface is fairly simple to implement, and 10 Mbit/s > is easy to achieve. If you mean to use the SPI as a programming interface to > the FPGA, you'll have to use an external device to convert the SPI to one of > the programming formats recognized by the FPGA. A CPLD is sufficient for that > task. > > Stijn Goris wrote: > > > hi all, > > > > I m looking for a FPGA with a SPI interface. The SPI interface needs to be > > able to send data at a high rate (10 Mbit/s). > > > > regards > > Stijn > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 69444
Dave, The packages may have absorbed moisture, and if you put them through a normal solder wave machine, you will have popcorn. The devices are prone to crack, and shatter due to the moisture turning to steam, and having no where to go. Parts may be baked before assembly to remove the water. http://www.xilinx.com/bvdocs/whitepapers/wp192.pdf details some of the procedures. Austin Dave Marsh wrote: > I have twenty Xilinx XC9572XL VQFP64. Their sealed package has been open two > months, and stored in an office with no temperature/humidity control. Now I > want to get these devices soldered in for a pre-production run. > > If I put these in without carrying out a baking cycle am I asking for > trouble? What are the likely effects due to moisture, and what are people's > real-life experiences? > > Many thanks, > > Dave > > >Article: 69445
> A <= "000" & X; -- sometimes I use this > > B <= (others => '0'); -- I've also tried this > B(7 downto 0) <= X; I don't like the second description because in many cases it is NOT obvious that there is a default value ... Imagine someone who inserts something else between the "B" lines ... I've seen this in larger processes (default-values at the beginning and some declarations later on) ... not very easy to read ... :-( bye, MichaelArticle: 69446
Hi everyone, I'm near the completion of the final TCL flow for a Quartus II hierarchical design (based on a previous comp.arch.fpga discussion with the same subject). I ran into a problem while finalizing the TOP script, which is supposed to import the locked, back-annotated BOTTOM regions and simply connect them on a top level. The BOTTOM blocks, after they are fitted, are back-annotated and exported along with their routing information. This is desirable, because if the routing was not exported the final top-level performance would not be guaranteed. However, there is a conflict with the global clock networks. Specifically, when each BOTTOM block is compiled it automatically promotes its high fanout nets onto global clocks. This, again, is desirable. But if this process is done automatically by Quartus and independently for each BOTTOM entity, when the BOTTOM blocks are assembled by the TOP script the routing on the global clock networks makes the fit impossible: Quartus has used the same global resources for different top-level nets. Is there any way that I can assign a _specific_ global clock network to a design node? Note that while a BOTTOM entity is compiled, the source of this global clock is not yet known: in my case, this global clock network will be driven by a different BOTTOM entity which is the reset controller (or a PLL with many output clocks). Does Quartus support this? The assignments "global signal" and "auto global clock" simply declare that a signal will be promoted to a global clock network, but do not specify _which_ of the available global clock networks will be used. Does anybody know something on this? Thanks in advance, SpyrosArticle: 69447
"Austin Lesea" <austin@xilinx.com> wrote in message news:c7qnr5$n103@cliff.xsj.xilinx.com... > Dave Marsh wrote: > > I have twenty Xilinx XC9572XL VQFP64. Their sealed package has been open two > > months, and stored in an office with no temperature/humidity control. Now I > > want to get these devices soldered in for a pre-production run. > > > > If I put these in without carrying out a baking cycle am I asking for > > trouble? What are the likely effects due to moisture, and what are people's > > real-life experiences? > > > > Many thanks, > > > > Dave > > Dave, > > The packages may have absorbed moisture, and if you put them through a > normal solder wave machine, you will have popcorn. > > The devices are prone to crack, and shatter due to the moisture turning > to steam, and having no where to go. > > Parts may be baked before assembly to remove the water. > http://www.xilinx.com/bvdocs/whitepapers/wp192.pdf > details some of the procedures. > > Austin > Thanks Austin - It sounds like we we would definitely notice if there was a problem then?! From the white paper it suggests a minimum of a 12 hour cycle at 125degC is needed. DaveArticle: 69448
"Dave Marsh" <me@privacy.net> wrote in message news:40a0dd9d$0$15249$fa0fcedb@lovejoy.zen.co.uk... > I have twenty Xilinx XC9572XL VQFP64. Their sealed package has been open two > months, and stored in an office with no temperature/humidity control. Now I > want to get these devices soldered in for a pre-production run. > > If I put these in without carrying out a baking cycle am I asking for > trouble? What are the likely effects due to moisture, and what are people's > real-life experiences? Reflow soldering without baking them (probably 120 C for 24 hours) might give problems. Hand soldering should be OK: I never have problems, anyway. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 69449
On Mon, 10 May 2004 09:21:27 -0700, Jim Lewis <Jim@SynthWorks.com> wrote: >acm wrote: >> Easypath = EasyScrap... >> >> Hey, buy our excess scrapped inventory!!!! >> >What is wrong with taking lemons and making Lemonade? > >Xilinx has taken the enviromentally sound practice >of taking parts that would have otherwise gone to the >dump, making them into something useful, and selling >them. I don't believe they have, as I understand it, I don't believe the EasyPath parts have actually failed production test. As I recall, it was the full testing itself that was expensive, rather than the device failures. To take it to extremes, if you can churn out wafers full of good devices, but you have to leave each chip sitting on the tester for eight hours to prove it, then test costs would be a killer. That would give a LOT of scope for testing exactly what a customer wants, and no more, and passing on the reduced cost of test time. The difference is, the rest of the chip is POSSIBLY fully functional, but Xilinx haven't spent the money to prove it. >To me this reflects engineering brillance. Either way... - Brian
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