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Nachiket Kapre wrote: > xapp134 seems to be stupid when it comes to remembering active rows in > the banks being accessed. it forces each read/write operation to go > through a "row activation" phase which might not be necessary. all > that it needs to do is maintain 4 registers which hold the value of > the currently active rows in each of the banks to determine whether or > not to issue a new "row activation" command. the xess code does better > by remembering the active row within a bank, but surprisingly forces a > "row activation" on a bank change. this is clearly not required if the > row in the new bank has previously been activated. I wouldn't call XAPP 134 stupid but I would call it a rather simple implementation of a SDRAM controller which does make it easier to use and understand (one of the purposes of a reference design). That application note has been out for some time now and maybe 4 or 5 years ago, I made the modifications to that code for a project I was working on to allow for open page accesses of the SDRAM and while it does improve throughput for sequential, non-burst reads/writes it was not as trivial to modify as you suggest and does make timing somewhat harder to meet for faster implementations. You do need to store last access address as you suggest but I also had to build a fast comparator (at the time, I had to build it structurally), make several modifications (more complex state transition logic) to the state-machine, I had to keep track of whether a refresh was issued since the last read/write to the RAM, I had to dynamically modify the data buffering in the SRLs to adjust to the proper wait states depending on whether a precharge is needed or not, as well as a few other details that probably escape me right now. The data paths did get longer with my implementation of open page accesses so timing was harder to hit but I did meet my targets after some coaxing with the code. Any ways, the great thing about a reference design with open code like this is if you do not like what you see, modify it to what works best for you. For applications that make somewhat random access to the memory, or where latency is not the utmost concern, I found that controller to work very well but of coarse every design has its own requirements and one generic implementation will not fit all of them. I am not sure what is causing the fatal error of the original poster. I have seen strange things like control charcters or corrupted files cause this sort of thing but the thing about fatal errors is the program that generates it does not know what caused the problem or else it would have given a better message so not much can be said about the message itself other than the program got broadsided with something it was not expecting and could not handle it gracefully. -- Brian > > i guess if you are worried abt ur memory bandwidth, u are better off > handtweaking the code to enable this. > > nachiket. > >Article: 68401
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<406CD985.7070708@designtools.co.nz>... > Chris Balough wrote: > > > Hi Hendra, > > > > Hope you won't mind my providing some clarification regarding > > availability of ModelSim from Altera. Your post suggested we don't > > provide ModelSim, when in fact we do. > > > > At Altera, one way we provide our software development tools is > > through the Altera Subscription program (more details at > > http://www.altera.com/products/software/order/ord-subscription.html > > and http://www.altera.com/products/software/pld/products/partners/eda-ms.html). > > In addition to our Quartus II software development tool, this > > subscription *does include* an Altera-only version of ModelSim. > <snip> > > Hi Chris, > An earlier poster in this thread made this claim > > ".. AHDL is being abandoned even by Altera's newer tools." > > Can you comment on that ? AHDL will/does support MAX II, for example ? > > I know designers who use AHDL, and find it very productive > in the CPLD space, and there must be large numbers of legacy designs > coded in AHDL out there. > > -jg Hi Jim, Altera will continue to support AHDL for the foreseeable future in Quartus II. Not only for existing devices, but for any new devices we introduce, such as Max II ChrisArticle: 68402
"Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<106p5chij03th48@news.supernews.com>... > Hello, > > I'm having a problem reading a single one byte register on a Nios/Cyclone > board. I've seen this on the devkit board as well. Every time I read a > single memory location, the Nios is automatically generating reads for the > next 3 locations as well. > > This causes bad things to happen when you are reading a location that is > within 3 bytes of a location that does not want to be read. > > There doesn't appear to be a setting in the SOPC User Logic GUI. Is there a > .ptf file entry I can edit to stop this behavior? > > The UL has 5 address bits, 8 databits, (RD#,WR#,CS#) and is an Avalon Memory > Slave. > > Thanks, > Ken Ken, Others have explained what is going on, but there are some subtle changes that can be made to your system to get the behavior you want. When you add your peripheral, I am presuming you are using the 'interface to user logic' wizard. If so, be sure you're selecting "Avalon Register Slave" (as opposed to memory slave). In the case of a 32-bit master, this has the effect right-shifting the address bus going to the slave by two bits (this does not occur if you are going through a tri-state bus bridge.. you can do so on your own by connecting address line A2 from Nios to A0 on your peripheral manually). The Avalon reference manual describes this in more detail. The reasoning behind this feature is to cover this very case -- where register access to a peripheral of a 'strange' width may upset other registers that happen to be inadvertently accessed. It also allows a peripheral to have a register that is 1 bit wide, followed by one that is 5 bits, or 30 bits, etc. With this, a master can then read *or write* a peripheral register of any bit width (up to the master's width) by presenting a word-aligned address (0, 4, 8...). On the slave side, the corresponding registers are decoded as 0..1..2... (again, the above example is based on a 32-bit wide master). One last note: Turning this feature on turns *off* the dynamic bus sizing feature of Avalon. Hope this is of some help to your design. Regards, Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 68403
Hi, I have stored YUV422 16 bit data from Philips SAA7111A. The Y data and UV data in 2 files. Now how to combine Y and UV into RGB format for display on PC? Please reply to fwang11@pub3.fz.fj.cn Thanks in advance. Wang, FengArticle: 68404
Hi folks, Most companies that sell EDA tools, such as Xilinx, Altera, Synopsys, Synplicity, Model Technology etc require you to renew the license annualy. Can anyone give a good reason for this? I mean, other very expensive software, such as Microsoft Office Professional, I can just install it once and it will run forever. With EDA tools, I have to renew the license every year, why is that? HendraArticle: 68405
..and no matter what you do, the problem still exists! Traffic lights don't fix it, UK roundabouts don't! There are always those 'should I stay or should I go' moments. cheers, Syms. > Once driving out in the middle of nowhere (cornfields in Illinois) > three cars came to a four way stop at (almost) exactly the same > time. It took a long time to figure out who should go first. > > It does make a good, everyday life, example... > > -- glen >Article: 68406
Actually.. in a few years all software will be on a one year license.. maybe not the OS... but MS has already looked into subscription based licenses and offers them to businesses. But the theory behind it... good or bad... is that they have staff to pay... and people want updates... and tech support ... so is a simple case of supply and demand... Xilina and Altera also have free versions so you can get the web pack and pay nothing... Modelsim even have a free .. if limited version of their simulator (for xilinx) so its a feast or famine. It all comes down to who wants to pay and who complains the most. Altium (Protel) tried to go subscription based... I was paying about $500 a year in upgrades before that and I chose when to get the upgrade... the subscription based was $1000 per year... the result as I think, as many a user also felt by the mailing list, was that why bother? their last version, although it has a few bugs (most well known) was extremely stable and very productive, so we all told Altium that subscription = no more $$$$.. Altium in the end backed down and you have a choice of $1000 per year and unlimited number of updates and free next versions or just free service packs and $2000 for the next revision (when you want it). So the main reason they choose subscription is people want to pay them subscriptions... or collectively (or individually) they have decide everybody else does in our field... so we can. Lets face it.. its good for business... who wants a customer who only pays you when they decide, its not good for cashflow. Subscriptions keep banks and accountants happy and in the end, ensure that the EDA companies keep turning out new bugs/updates on a regular basis to keep you, the end user, happy. "Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:c4lbpk$6igo9$1@hades.csu.net... > Hi folks, > Most companies that sell EDA tools, such as Xilinx, Altera, Synopsys, > Synplicity, Model Technology etc require you to renew the license annualy. > Can anyone give a good reason for this? I mean, other very expensive > software, such as Microsoft Office Professional, I can just install it once > and it will run forever. With EDA tools, I have to renew the license every > year, why is that? > > Hendra > >Article: 68407
> ".. AHDL is being abandoned even by Altera's newer tools." > > Can you comment on that ? AHDL will/does support MAX II, for example ? > > I know designers who use AHDL, and find it very productive > in the CPLD space, and there must be large numbers of legacy designs > coded in AHDL out there. > Jim, You are correct, many designers use AHDL, specially for simple, CPLD type designs. Some use it even for large FPGAs (at least for portions of it). We probably still have IP written in AHDL. And if nobody else, we still use it internally for many many of our regression tests. There is no benefit in removing a widely used, very stable feature (that also has good name recognition). I am sure it will be years before we even consider removing it. AHDL is basically a family independent language and therefore, supports all of our device families. Therefore, it works just as well for MAX7000B, MAX II, or even Stratix II. -David Karchmer Altera Corp.Article: 68408
Hal Murray wrote: >>Now, the people who try to use C as a hardware description language >>are the ones I really don't understand. Two that I know about >>(though not much about) are Handel C and Transmogrifier C. > What's wrong with c for "describing" hardware? You just need > a good library. The actual code is just subroutine calls and > argument shuffeling. Using c might be slightly less dense than > better approaches, but it works fine. To me, it encourages the idea that you can use existing algorithms in C for hardware implementation. Hardware design is inherently parallel, and C is inherently serial. If that doesn't bother you any, then I suppose it is fine. The beginning of the thread was commenting that verilog's similarity to C could be confusing to users, though I don't believe anyone would expect to port a C program directly to verilog. Try to imagine a C compiler that would accept a C program where assignment statements were like the verilog continuous assignment. Which one should be executed first? -- glenArticle: 68409
'it allows for almost direct "brain-to-PC" connection' which surely is the whole point (well, 99%) of a schematic editor. it sounds as though you have an unconventional but near-ideal solution - be proud! Just don't get me started on schematic editors and how bad they are, why... (I said don't...!) Bedrich's original message re-formatted: You may wonder but we make almost all our designs in OrCAD SDT 386+. For us (no flame, please! ;-) it is the best design entry tool ever. We drawn compact libraries for Spartan2+ and Virtex FPGAs, we modified the EDIF 2 0 0 netlister and we created an interface for embedding VHDL blocks into the schematics. Although this old program has some disadvantages in today's Windows envirinment, it allows for almost direct "brain-to-PC" connection than other, not so user's friendly tools before we will create our own one. And the 2D schematics is significantly more suitable for parallel tasks in FPGA than text files description. Last note - even large projects are composed from small block, so I do not agree the argument that schematics is not well suited for large designs...Article: 68410
"Jesse Kempa" <kempaj@yahoo.com> wrote in message news:95776079.0404021757.302101b5@posting.google.com... > "Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<106p5chij03th48@news.supernews.com>... > > Hello, > > > > I'm having a problem reading a single one byte register on a Nios/Cyclone > > board. I've seen this on the devkit board as well. Every time I read a > > single memory location, the Nios is automatically generating reads for the > > next 3 locations as well. > > > > This causes bad things to happen when you are reading a location that is > > within 3 bytes of a location that does not want to be read. > > > > There doesn't appear to be a setting in the SOPC User Logic GUI. Is there a > > .ptf file entry I can edit to stop this behavior? > > > > The UL has 5 address bits, 8 databits, (RD#,WR#,CS#) and is an Avalon Memory > > Slave. > > > > Thanks, > > Ken > > Ken, > > Others have explained what is going on, but there are some subtle > changes that can be made to your system to get the behavior you want. > When you add your peripheral, I am presuming you are using the > 'interface to user logic' wizard. If so, be sure you're selecting > "Avalon Register Slave" (as opposed to memory slave). > > In the case of a 32-bit master, this has the effect right-shifting the > address bus going to the slave by two bits (this does not occur if you > are going through a tri-state bus bridge.. you can do so on your own > by connecting address line A2 from Nios to A0 on your peripheral > manually). The Avalon reference manual describes this in more detail. > > The reasoning behind this feature is to cover this very case -- where > register access to a peripheral of a 'strange' width may upset other > registers that happen to be inadvertently accessed. It also allows a > peripheral to have a register that is 1 bit wide, followed by one that > is 5 bits, or 30 bits, etc. With this, a master can then read *or > write* a peripheral register of any bit width (up to the master's > width) by presenting a word-aligned address (0, 4, 8...). On the slave > side, the corresponding registers are decoded as 0..1..2... (again, > the above example is based on a 32-bit wide master). > > One last note: Turning this feature on turns *off* the dynamic bus > sizing feature of Avalon. > > Hope this is of some help to your design. > > Regards, > > Jesse Kempa > Altera Corp. > jkempa at altera dot com Hi Jesse, I thought I read somewhere that a Register Slave wouldn't work with the dma. (maybe not?) Anyway, thanks to you and David for your insight. With this understanding I am happily dma'ing at full speed with no lost bytes. Will the NiosII allow unaligned reads? (if its not a secret :) ) KenArticle: 68411
heya ppl i was wondering if any one could help me figure out out to wokr the DI05-CLPD board using the D2-FPGA board the specufication for these boards kind be found at https://digilent.us/Materials/current.html any help would be greatly appreacited.. maybe an example as well.. basically i was try to work with the switches and hte leds on the CPLD board.. Thnx in adv! TyronArticle: 68412
On 2 Apr 2004 11:09:14 -0800, agwsu@yahoo.com (Andy) wrote: >Hi everybody, Could you people help me choose between Altera's Stratix >and Xilinx Vertex II...also as how to analyze the datasheet to >conclude the pros and cons of both the architectures? >thanks >-andy If you have a design underway, one method is to take a representative chunk of that design and implement it, using the free tools (or the real tools with an evaluation license) for that architecture. I needed arithmetic, so I chose a square root unit as a non-trivial test. That will give you a basis for comparing gate counts, speed, capacity, -and the reliability and usefulness of the tools- for both architectures. - BrianArticle: 68413
Hendra Gunawan wrote: > Hi folks, > Most companies that sell EDA tools, such as Xilinx, Altera, Synopsys, > Synplicity, Model Technology etc require you to renew the license annualy. > Can anyone give a good reason for this? I mean, other very expensive > software, such as Microsoft Office Professional, I can just install it once > and it will run forever. With EDA tools, I have to renew the license every > year, why is that? Not really. I was told the purchased full version of Quartus runs forever. It then doesn't support the latest chips though. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 68414
"none" <none@none.net> wrote in message news:406f12d7$0$709$5402220f@news.sunrise.ch... > Hendra Gunawan wrote: .......>>> I mean, other very expensive > > software, such as Microsoft Office Professional, I can just install it once > > and it will run forever. With EDA tools, I have to renew the license every > > year, why is that? > > > Not really. > I was told the purchased full version of Quartus runs forever. > It then doesn't support the latest chips though. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net Rene is correct. The full version of Quartus received when an annual subscription is purchased, will run forever, with the license provided at the time of the subscription purchase. You do NOT have to renew your license annually to use the version of Quartus that you received as part of the subscription. For example, lets say you purchased an annual subscription for Quartus in February 2004. Your license file will contain an entry 2005.02. What this means that you will be able to use any version of Quartus released before and including February 2005 for as long as you please. This includes the versions of Quartus to be released between now and February 2005, Quartus II 4.0, 4.0 SP1, Quartus II 3.0, Quartus II 2.2, .... Purchasing an annual subscription provides access to new versions of Quartus during the subscription period. These new versions of Quartus provides support for the new device families introduced when the subscription is in effect, in addition to the improvements in the software. - Subroto Datta Altera Corp.Article: 68415
Ha, I think you know the answer. The issue isn't "logic", it's what maximizes revenue and what the market will bear. Software vendors also like the financial model, because it's easier to predict revenues and they are less bursty and dependent upon revisions. Stockholders don't like to be surprised from quarter to quarter. In some cases it makes sense for the customer. Old versions of Synplify aren't much good if they only support Xilinx 4000-series chips. In other cases, the customer doesn't neet an update. For example, for most people, the 1997 version of Microsoft Excel is just as good as the newest version. They don't need updates. However, Microsoft would like to get annual revenue for it, so they are making businesses get subscriptions and they have leverage because they have a monopoly. Another thing they do it make it obsolete by making the new versions incompatible, so when you get a spreadsheet from a new customer you can't look at it in Excel '97. So in some cases the obsolescence is manufactured, while in others it is created by other market forces (like Spartan-XL becoming obsolete). -Kevin "Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:c4lbpk$6igo9$1@hades.csu.net... > Hi folks, > Most companies that sell EDA tools, such as Xilinx, Altera, Synopsys, > Synplicity, Model Technology etc require you to renew the license annualy. > Can anyone give a good reason for this? I mean, other very expensive > software, such as Microsoft Office Professional, I can just install it once > and it will run forever. With EDA tools, I have to renew the license every > year, why is that? > > Hendra > >Article: 68416
Subroto Datta wrote: <snip> >>Not really. >>I was told the purchased full version of Quartus runs forever. >>It then doesn't support the latest chips though. >> >>Rene > > Rene is correct. The full version of Quartus received when an annual > subscription is purchased, will run forever, with the license provided at > the time of the subscription purchase. You do NOT have to renew your > license annually to use the version of Quartus that you received as part of > the subscription. > > For example, lets say you purchased an annual subscription for Quartus in > February 2004. Your license file will contain an entry 2005.02. What this > means that you will be able to use any version of Quartus released before > and including February 2005 for as long as you please. This includes the > versions of Quartus to be released between now and February 2005, Quartus II > 4.0, 4.0 SP1, Quartus II 3.0, Quartus II 2.2, .... Sounds good. Timed licenses have many pitfalls. One is version control - suppose you archive your source, _and_ the tools ( as many do, on passing into production), then 3-4 years later a fix/rev comes along, and suddenly the tools you thought were archived, are useless.... Another is the tutor who arrives for the CPLD LAB, only to find that since last year, the SW has timed out, and he has to scramble to find someone who knows how to get & fix the license whilst the students [twiddle their thumbs / study diligently / riot ] <= select appropriate. Q: Do Altera have a web-stub that has the 'museum versions' of their SW, as I see more companies doing. It is not unique to hear - 'Gee, this code does not fit on the new version..' -jgArticle: 68417
In article <406e46d6@news.actrix.gen.nz>, Simon Peacock wrote:
> Actually.. in a few years all software will be on a one year license..
^^^
Well, perhaps all non-free software.
- Larry
Article: 68418Not a great thrill but I've made some improved Xilinx Parallel 3 clones if anyone is interested. Improvements: R/C followed by Schmitt trigger on TCK Simple shunt voltage regulator on local power allowing use of HC with approx TTL input thresholds instead of HCT logic so it works reliably with from 2.5V to 5V JTAG VIO Price $9.95 assembled (no cables) $2.00 bare PCB Also a simple CPLD card for $9.95 assembled $2.00 bare PCB XC9572XL-PC44 CPLD 2 x 26 pin I/O connectors - all I/O available 4 speed R/C oscillator 4 buffered LEDS Optional 48 MHz Xtal OSC add $4 (13.95 assembled) pushbutton. Peter WallaceArticle: 68419
I am using iMPACT trying to download to a Spartan II-E FPGA on a digilent D2E board, but for some reason every time I download this particular code's bit file I got "Programming Failed". I have downloaded other bit files and they programmed fine but this particular file I have problem with. All the synthesis and place and route steps were fine. PROGRESS_START - Starting Operation. Validating chain... Boundary-scan chain validated successfully. Validating chain... Boundary-scan chain validated successfully. '1':Programming device... done. INFO:iMPACT:579 - '1': Completed downloading bit file to device. INFO:iMPACT:580 - '1':Checking done pin ....done. '1': Programming terminated, Done did not go high. PROGRESS_END - End Operation. Elapsed time = 9 sec.Article: 68420
"Joelle" <joelle_yf@yahoo.ca> wrote in message news:26449685.0404032118.3f163a01@posting.google.com... > All the synthesis and place and > route steps were fine. How do you know that the synthesis and place/route work fine? Did you actually look at the text file of synthesis and place/route report and make sure there are no errors or warning? When you sythesize and place/route, are you sure you specified the right chip? One other thing, I think that particular board has problem in multiple consecutive download process. Sometimes, unplugging and replugging the power suppy fix the problem. HendraArticle: 68421
Brian Philofsky <brian.philofsky@no_xilinx_spam.com> wrote in message news:<c4l1sh$dt65@xco-news.xilinx.com>... > > I wouldn't call XAPP 134 stupid but I would call it a rather simple > implementation of a SDRAM controller which does make it easier to use > and understand (one of the purposes of a reference design). my apologies. the idea that i wanted to convey was that the controller was too simplistic in its assumption that row activations are necessary for every row access. when you look at altera's sdram controller core, "activation" as a separate command suddenly makes the xilinx controller look foolish. its probably not that hard for even a novice to figure out that "activations" shouldn't piggyback each read/write commands. of course the novice now has to start remembering which rows did he keep active in which banks...etc. but, you take a look at the xess code to see how to keep the interface simple .. only read/write and yet automate a lot of the sdram operations internally, yet intelligently. so the bottomline is xilinx should really try and tweak the code to allow easy extensibility of their vhdl. > That > application note has been out for some time now and maybe 4 or 5 years > ago, I made the modifications to that code for a project I was working > on to allow for open page accesses of the SDRAM and while it does > improve throughput for sequential, non-burst reads/writes it was not as > trivial to modify as you suggest and does make timing somewhat harder to > meet for faster implementations. You do need to store last access > address as you suggest but I also had to build a fast comparator (at the > time, I had to build it structurally), make several modifications (more > complex state transition logic) to the state-machine, I had to keep > track of whether a refresh was issued since the last read/write to the > RAM, I had to dynamically modify the data buffering in the SRLs to > adjust to the proper wait states depending on whether a precharge is > needed or not, as well as a few other details that probably escape me > right now. The data paths did get longer with my implementation of open > page accesses so timing was harder to hit but I did meet my targets > after some coaxing with the code. i was almost tempted to modify the code myself. but then i stumbled across the xess controller which i guess probably wan't available 4-5 years ago. and i think i am reasonably happy with it. > > Any ways, the great thing about a reference design with open code like > this is if you do not like what you see, modify it to what works best > for you. For applications that make somewhat random access to the > memory, or where latency is not the utmost concern, I found that > controller to work very well but of coarse every design has its own > requirements and one generic implementation will not fit all of them. true. but, i am skeptical about how easy the xilix code is to allow modification. again when you look at xess' code it is far better commented and the signals/state encoding makes more sense than the xilinx coding style in xapp134. and i agree with your concern for meeting timing and there might be some tricks required to get it working. nachiket.Article: 68422
In article <80e4f9e8.0404021523.856f188@posting.google.com>, spanchag <spanchag@yahoo.com> wrote: >Hi > >I would like to find out if there is some sort of an equation where we >give the size of the two inputs and it tells us how many flip flops it >is going to use to implement the multiplier function. For the multiplier function produced by compiling Verilog a <= b*c for my Spartan 2, it seems to use a little over n^2 flip-flops, but there are serious arrangement constraints: to use the carry chains, it builds columns of height n/2. So that's not very helpful to see how many multipliers fit on chip: it's not clear that I could fit much more than three 16x16->32 on the XC2S150 before I run out of columns. I've not tried fitting more than one. Of course, those are full-parallel multipliers, and a serial one taking n cycles requires roughly 3n flip-flops, again arranged in columns to use the carry chain for the accumulator. [my dev board has arrived; I may shortly start asking some incredibly newbie questions about why horribly-naive designs don't work ...] TomArticle: 68423
"Hendra Gunawan" <u1000393@email.sjsu.edu> writes: > Most companies that sell EDA tools, such as Xilinx, Altera, Synopsys, > Synplicity, Model Technology etc require you to renew the license annualy. They don't require you to do that. You just don't get support and upgrades if you don't have a maintenance contract. You can e.g. contact Synopsys and tell them that you will cancel you maintenance contract. You will get a new license file that is valid "forever" (it's typically 20 years or so). However, you will not receive support or free upgrades of the software. If you want to continue your maintenance contract you will have to pay for the missing period and possibly some extra fee as well. Check with your vendors to get the figures. It can be somewhat difficult to operate a tool chain without a maintenance contract since your next design will use the Virtex VII (and you're using the old ISE 6.4SP11), or your just purchases IP block uses features found in Verilog 2005 (and you have a Verilog 2001 based simulator), etc... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 68424
A. Because Jeopardy is my favorite game show. Q. Why doesn't top posting both me? -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Petter Gustad" <newsmailcomp6@gustad.com> wrote in message news:87fzbkdku9.fsf@zener.home.gustad.com... > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?
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