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Magnus, I'm not sure about the 64B/66B encoder, but in 8B/10B mode, the extra bits are sent/received on TX/RXCHARDISPMODE and TX/RXCHARDISPVAL The following app note outlines the connections http://www.xilinx.com/bvdocs/appnotes/xapp649.pdf I'd assume that the 64B/66B mode is similar. Cheers, Meng www.wmsdesigns.caArticle: 68651
Hi folks,
I have seen several people here posted waveforms in text format.
/-----\ /---------\ /-----\
data < outx X in data X out x
\-----/ \---------/ \-----/
How do I draw the waveform quickly? Is there any free tool that I can use to
draw the waveform quickly in text format or do I have to do it manually by
hand?
Thanks in advance!
Hendra
Article: 68652Can you check that the ddr_v1_00_b_virtex2_async_fifo.edn file is located in the <proj>/implementation directory? I think problem is when you do an export-to-projnav flow, XPS has location pointers to all your wrapper NGC files, but not the BBD specified netlists. So if you run projnav in a directory other than <proj>/implementation, you won't pick up the BBD netlists. It's just a matter of moving ddr_v1_00_b_virtex2_async_fifo.edn to directory where you kick-off ngdbuild. This is fixed in EDK.6.2i. Antti Lukats wrote: > Hi > > A SoC done with EDK 6.1 using OPB_DDR core works OK in XPS but when the SoC > is used in ISE flow the Xilinx OPB_DDR doesnt pass translate stage with > error that asyn_fifo edif can not be loaded due to pin name mismatch! > > how to make it work? there should be some fix, but can not find in Xilinx > answer database at least! > > thanks! > > Antti > http://xilinx.openchip.org > > -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 68653
I've purchased the Memec V2Pro board and Xilinx EDK. Can I use my Parallel Cable III, or is the IV required? Thanks. -DaveArticle: 68654
SD, Responding to your points . . . 1. I/O was not taken into account on the benchmarks that we published. Altera has run numersous experiments to measure the impact of I/O constraints on fMAX performance. We found that typically these constraints change the relative performance advantage (or disadvantage) by less than 5%, or had relatively minimal impact. We left them out of this analysis for 2 reasons - 1st we do not have I/O constraints for all of our designs (not all customers provide them to us) and 2nd they add complication to (Altera's internal) goal of automating this benchmark process so that it is repeatable with each new software release or new silicon architecture. 2. We add designs to our benchmark suite as we get them (after they go through a rigorous process of optimizing the HDL code for both Altera and competitive architectures and verifying the results to ensure that any outlying results are legitimate). 3. We do not use any manual placement for these benchmarks. Reason here is again need to have a methodology that is both automated and repeatable. Critical path information is a critical tool utilized for improving place & route / fitting algorithms - so we regularly analyze this information, though not from the context of evaluating improvement through manual placement. Dave Greenfield Altera Product Marketing > I had three points relating to the seminar in question that I hope you > can address: > > 1) Was I/O timing taken into account at all for the benchmarks? Did > the designs have I/O constraints? I would have liked to see both the > Tsu and Tco on the critical path, instead of just the Fmax, since > these can be traded off in many situations. In fact, a higher core > Fmax at the expense of system Fmax may be useless in many > applications. > > 2) How long has Altera had these 75 designs? Part of the discrepancy > in performance between the two vendors may be that the tools, and > possibly even the architectures, have been tuned to their in-house > designs. > > 3) For your "best effort" comparision, did you use any manual > placement/routing for either of the tools? Did you analyze the > critical path of either vendor for possible improvement through manual > intervention? > > SD > > >Article: 68655
Thanks, you must be right : I assumed that 6.2 was just an update for 6.1. I need to install the CDs first and then the service pack. Arthur "Jim Wu" <NOSPAM@NOSPAM.com> wrote in message news:amuec.39052$1y1.3707@nwrdny03.gnilink.net... > . > > > > You need to install ISE 6.2 first before you can install the service pack 1. > > HTH, > Jim > jimwu88NOOOSPAM@yahoo.com > http://www.geocities.com/jimwu88/chips > > >Article: 68656
>1. I/O was not taken into account on the benchmarks that we published. >Altera has run numersous experiments to measure the impact of I/O >constraints on fMAX performance. We found that typically these >constraints change the relative performance advantage (or >disadvantage) by less than 5%, or had relatively minimal impact. We >left them out of this analysis for 2 reasons - 1st we do not have I/O >constraints for all of our designs (not all customers provide them to >us) and 2nd they add complication to (Altera's internal) goal of >automating this benchmark process so that it is repeatable with each >new software release or new silicon architecture. What if I want to change the code in an existing board? That seems like a reasonably common case. I'd expect you would want to cover it. (But maybe I missed the big picture that started this discussion.) If your current set of tests doesn't have that info, you might be able to run place/route once, capture the pin locations, and then run p/r again with that pinout. (Or perhaps scan it manually and clean things up if they are too ugly. Or get a PCB guy to check it...) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68657
you should be good to go "Dave" <apple2ebeige@yahoo.com> wrote in message news:d4aa8e8a.0404121553.780bebf0@posting.google.com... > I've purchased the Memec V2Pro board and Xilinx EDK. Can I use my > Parallel Cable III, or is the IV required? Thanks. > > -DaveArticle: 68658
Hal, > What if I want to change the code in an existing board? That seems > like a reasonably common case. I'd expect you would want to cover it. > (But maybe I missed the big picture that started this discussion.) > > If your current set of tests doesn't have that info, you might be > able to run place/route once, capture the pin locations, and then > run p/r again with that pinout. (Or perhaps scan it manually > and clean things up if they are too ugly. Or get a PCB guy to > check it...) [My response is in the context of internal benchmarking for the purposes of Quartus QoR (Quality of Results) improvement -- that is, comparing Quartus to Quartus. Competitive benchmarking is much more complicated due to the varying capabilities and behaviours of different CAD tools and device architectures, and I'm not familiar with the exact details of this process, except to say that there is a lot of thought that goes into the settings used.] We typically internally benchmark our Quartus p&r with randomly selected pin placements. This mimics the situation you point out above, where I/O locations are selected and locked down before the design has been fully implemented. In reality, a pinout isn't completely randomly placed, since there will be some correlation of pin placement and logical function (memory buses together, etc.), but in the absence of user-supplied pin outs, it's a good pessimistic way to ensure that the CAD tool does a good job of optimization in the presence of arbitrary pin assignments. An alternative approach (as you suggest) is to use an optimized pin placement that we lock down and then run another placement run with a different random seed. We also run tests on Quartus where pins are free to move, and ensure that yes, it actually does a better job optimizing Fmax, Tco, and Tsu as a result. We will sometimes arbitrarily set various I/O standards for the I/Os to make sure we can handle complicated I/O placement cases. And we run p&r experiments with both I/O constraints and core Fmax constraints, or just some of each, to make sure Quartus behaves well under different constraint conditions. I bet half our office heat comes from the 100s of dedicated CPUs crunching away on various QoR sweeps 24 hours a day! As David points out, there are a lot problems with getting real customer pinouts and/or I/O constraints. Besides the primary problem that we often don't receive these with the design, we are also using many designs that weren't originally targeted at the device we're testing. For example, during Stratix II development many of the designs we were using for benchmarking were originally targeted at APEX, Stratix, various Xilinx parts, and even some ASICs. Regards, Paul Leventis Altera Corp.Article: 68659
"Hendra Gunawan" <u1000393@email.sjsu.edu> schrieb im Newsbeitrag news:c5c9lk$6lunr$1@hades.csu.net... > Hi folks, > My laptop does not have a parallel port. So, I bought this PCMCIA to > parallel port converter. http://www.quatech.com/catalog/parallel_pcmcia.php > It claims to work exactly like a native parallel port. But I have problem > using it with my FPGA. > 10% of the time, it works perfectly. But 90% of the time, I get an error > while downloading the bit stream to the FPGA. Impact gives me the following > error messages: > > Device #1 selected > //*** BATCH CMD : Program - p 1 > PROGRESS_START - Starting Operation > Validating chain... > Boundary-Scan chain validated successfully. > '1':Programming device... > done. > INFO:iMPACT:579 - '1':Completed downloading bit file to device. > INFO:iMPACT:580 - '1':CHecking done pin ... done. > '1': Programming terminated, Done did not go high. > PROGRESS_END - End Operation. > Elapsed time = 10 sec. > > All the download attempts, the successfull and un-successfull one, use the > same bitstream file. My FPGA is D2E from digilent.cc. I have Webpack 6.2i > with latest service pack installed, Windows XP Professional, PIII 700MHz and > 256 MB RAM. Does anyone have any suggestion on how to fix the problem? Is > there any other PCMCIA to parallel port converter, other than spp-100 from > Quatech, that is available in the market? > Please help, I really need to use this FPGA for doing my work! > Thanks a lot in advance! > > Hendra > > Hello, 1.) what are the parallel port settings You use? SPP, PS2, EPP or ECP mode? If possible, try all in above order. Most incompatible mode is ECP mode. We randomly suggested Quatech SPP-100 to our customers using our parallel-port based products, never had problems... 2.) what kind of download cable do You use? Xilinx parallel cable III (DLC5) or newer cable (parallel cable IV)? This newsgroup tells that DLC5 may have some problems depending on PC, setup and circomstances. But never had those problems ourselves. Try to find hints in the newsgroup archieve, some people use a cap at a pin.... with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 68660
"Paulo Dutra" <paulo.dutra@xilinx.com> wrote in message news:407B22FE.1080307@xilinx.com... > Can you check that the ddr_v1_00_b_virtex2_async_fifo.edn file > is located in the <proj>/implementation directory? > > I think problem is when you do an export-to-projnav flow, XPS has > location pointers to all your wrapper NGC files, but not the BBD > specified netlists. So if you run projnav in a directory other > than <proj>/implementation, you won't pick up the BBD netlists. > It's just a matter of moving ddr_v1_00_b_virtex2_async_fifo.edn > to directory where you kick-off ngdbuild. > > This is fixed in EDK.6.2i. Thanks!!!! it was so simple !! AnttiArticle: 68661
The main problem with C is that it is an 'unconstrained type' language. Java is a better solution as I believe it locks types and forces type conversion. If you think it doesn't matter.. remember hardware executes in parallel... so try debugging it! Simon "ram" <ramntn@yahoo.com> wrote in message news:61c2cc9d.0404120732.756330d9@posting.google.com... > Hi Group, > Lately there is a lot of talk about System C, is Xilinx or Altera > planning to consider System C. I heard Forge tool from Xilinx is meant > for Java programmers to do hardware designs, is xilinx/altera coming > up with thier own tool set for doing design with C/C++. > having said that I also want to know how complicated/easy it gets to > design systems completely using C/C++ and letting the software takes > care of diving the system into hardware modules and software programs. > Streams C based product from Impulse Tech supports both Xilinx/altera > soft processor cores,have anyone designed system with that. > > I started working with Virtex2pro ( thats my introduction into the > world of FPGAs and embedded systems ) for over a year and now > cosidering to start exploring ways to configure FPGAs. Actually I am a > student doing my master's so I would like to think about how the > growth will be on designing systems with C/C++ - its obvious using > high level languages makes life much easier but not sure abt the > difficulties > your suggestions, criticism are all welcome > > Regards > > RamArticle: 68662
We have a graph and nodes in the graph are to be placed onto a layout. The layout has to be partitioned vertically as well as horizontally several times till it generates one slot per node. Nodes are to be assigned to vertical and horizontal partitions such that the number of edges crossing the partition is minimized. Can anybody suggest an effective procedure to deal with this problem? As an example if we have a graph with sixteen nodes then layout has to be partitioned vertically and horizontally till the time it creates sixteen slots one per node. The idea is to decide which slot would go to which node by following the above criteria( i.e number of edges crossing a partition is minimized. Thanks.Article: 68663
Hello, I would like to design a card with one FPGA XC2V2000, two 18V04 and two ZBT RAMs of 512*36 each... Could you help me to find any solution to connect my FPGA to the EEPROMs and to the ZBT RAMs... Thank you very much for your comprehension and for your help... Please answer me at drms@alinto.com Yours, SaleemArticle: 68664
Dude, Since we're not doing the same coursework you are, the verbage is a bit hard to follow. I know what a graph is and vertical or horizontal partitions make sense... but how do nodes have edges in this context? What's a slot, now? Perhaps there's more appropriate help available through the academic channels that posed this problem than in comp.arch.fpga where we try to help each other solve real-world problems. "Chris Jones" <chjones@dacafe.com> wrote in message news:8090cd3b.0404130521.61eb9b1f@posting.google.com... > We have a graph and nodes in the graph are to be placed onto a layout. > The layout has to be partitioned vertically as well as horizontally > several times till it generates one slot per node. Nodes are to be > assigned to vertical and horizontal partitions such that the number of > edges crossing the partition is minimized. Can anybody suggest an > effective procedure to deal with this problem? > > As an example if we have a graph with sixteen nodes then layout has to > be partitioned vertically and horizontally till the time it creates > sixteen slots one per node. The idea is to decide which slot would go > to which node by following the above criteria( i.e number of edges > crossing a partition is minimized. > > Thanks.Article: 68665
Dave,
If I have offended anyone, I apologize.
However, I do not appreciate the mis-quote of this newsgroup in your
slides at the presentation. Odd how my comment was distorted and then
made it into the presentation. Makes me wonder.
But, all of that aside, you will be happy to know that I no longer will
comment on software, or software performance in this forum. We have
someone who is now tasked with that subject. I am not an expert in that
field (as I so amply demonstrated by opening my mouth and letting
everyone know): all I can do is repeat what I hear from our customers,
and our own engineers. They can do a much better job.
The questions I posed are legit, however. As well as comparing 90nm to
90nm ('Our latest announced yet to be shipped chip is better than your 2
year 130nm technology chip...')
I will continue to monitor the group for the questions that I can shed
some light on: signal integrity, IO modeling, IC Design, etc.
Now you have a (mis) quote from me in your slides on a subject that I
have publicly stated I am not an expert in.
Austin
Article: 68666> "Chris Jones" <chjones@dacafe.com> wrote in message > news:8090cd3b.0404130521.61eb9b1f@posting.google.com... >> We have a graph and nodes in the graph are to be placed onto a >> layout. The layout has to be partitioned vertically as well as >> horizontally several times till it generates one slot per node. Nodes >> are to be assigned to vertical and horizontal partitions such that >> the number of edges crossing the partition is minimized. Can anybody >> suggest an effective procedure to deal with this problem? >> >> As an example if we have a graph with sixteen nodes then layout has >> to be partitioned vertically and horizontally till the time it >> creates sixteen slots one per node. The idea is to decide which slot >> would go to which node by following the above criteria( i.e number of >> edges crossing a partition is minimized. >> >> Thanks. Try doing a search on the terms "graph partitioning optimization". You should find a lot of algorithms and heuristics. If you don't want to weed through all the alternatives, then try the Lin-Kernighan technique. It's fast and usually finds good solutions that are within a few percent of the optimum. -- || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 || || devb@xess.com PO Box 33091 || || http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||Article: 68667
Hi Saleem, Firstly - unless there are reasons you haven't yet explained I would use the platform flash parts for configuration, not the XC18V04. The XC2V2000 requires 7.5Mbits of config memory so you would be able to use a single 8Mbit part with no problems at all. The platform flash parts are cheaper and available in much larger sizes (see here: http://www.xilinx.com/publications/matrix/prom_color.pdf) Regarding the ZBT RAMS - please take a look at the following apps note: http://www.xilinx.com/bvdocs/appnotes/xapp136.pdf Although it was written for Virtex and Spartan series parts, it should give you some ideas. There is also a link to a reference design at the bottom of the pdf. There is also a very good apps note (XAPP802) covering all sorts of memory interfaces here : http://www.xilinx.com/bvdocs/appnotes/xapp802.pdf Alternatively, Xilinx have a Logicore available here : http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?BV_SessionID=@@@@0715852257.1081871973@@@@&BV_EngineID=ccchadclejekjfkcflgcefldfhndfmo.0&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=null&category=&iLanguageID=1&key=opb_zbt_controller I hope that helps, Best Regards -- Steve Merritt BEng (Hons) CEng MIEE XILINX Gold Certified Field Applications Engineer Insight MEMEC Click link below for more information on : XILINX Free Training <http://www.xilinx.com/support/training/europe-home-page.htm> XILINX Design Services <http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service s> 10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm> Or Tel - 08707 356532 for more information "MS" <drms@alinto.com> wrote in message news:ee83c0f.-1@WebX.sUN8CHnE... Hello, I would like to design a card with one FPGA XC2V2000, two 18V04 and two ZBT RAMs of 512*36 each... Could you help me to find any solution to connect my FPGA to the EEPROMs and to the ZBT RAMs... Thank you very much for your comprehension and for your help... Please answer me at drms@alinto.com Yours, SaleemArticle: 68668
Just to add to Matts reply... the parallel III cable should work fine for the VIIPro boards however it wasn't really intended for 2.5v JTAG - see here : http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=8096 The only other point to note is that the parallel IV cable is significantly faster than the parallel III Regards, -- Steve Merritt BEng (Hons) CEng MIEE XILINX Gold Certified Field Applications Engineer Insight MEMEC Click link below for more information on : XILINX Free Training <http://www.xilinx.com/support/training/europe-home-page.htm> XILINX Design Services <http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service s> 10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm> Or Tel - 08707 356532 for more information "Matt" <bielstein2002@comcast.net> wrote in message news:zWKec.25456$wP1.64895@attbi_s54... > you should be good to go > > "Dave" <apple2ebeige@yahoo.com> wrote in message > news:d4aa8e8a.0404121553.780bebf0@posting.google.com... > > I've purchased the Memec V2Pro board and Xilinx EDK. Can I use my > > Parallel Cable III, or is the IV required? Thanks. > > > > -Dave > >Article: 68669
It takes about 8 minutes to finish PAR. ISE 6.1 SP#3 is about 10
minutes. The design is for a XC2VP40-FF1152 with pins and timings
constrained and very little floor planning:
Device utilization summary:
Number of External DIFFMs 99 out of 344 28%
Number of External DIFFSs 99 out of 344 28%
Number of External IOBs 96 out of 692 13%
Number of LOCed External IOBs 96 out of 96 100%
Number of MULT18X18s 188 out of 192 97%
Number of RAMB16s 3 out of 192 1%
Number of SLICEs 8139 out of 19392 41%
Number of BUFGMUXs 3 out of 16 18%
Number of TBUFs 784 out of 9696 8%
-Qlyus
Article: 68670Brijesh, Although Plat Gen only supports XST, that's not a problem for you. EDK will synthesise the processor part of the design using XST (despite the fact that you have ISE without XST). EDK still has access to XST even if you don't.... All you need to do then is take your HDL, create black boxes (for the processor cores & peripherals) inside the design, Synthesise as normal using Synplify, then let ISE tie everything together for you. So in answer to your last question - yes, you can still use Synplify just slightly further into the loop. Best Regards, -- Steve Merritt BEng (Hons) CEng MIEE XILINX Gold Certified Field Applications Engineer Insight MEMEC Click link below for more information on : XILINX Free Training <http://www.xilinx.com/support/training/europe-home-page.htm> XILINX Design Services <http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service s> 10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm> Or Tel - 08707 356532 for more information "Brijesh" <brijesh_xyz@cfrsi.com> wrote in message news:c54fmf$pkv$1@solaris.cc.vt.edu... > Was going through the Documentation. Buried deep within I found this > > "Currently, Platform Generator only supports XST (Xilinx Synthesis > Technology)." > > Guess Iam stuck. Unless there is a tutorial that does not use the > Platform Generator. Is there a way to change the Synthesis tool option > once the project is generated using the Platform Generator. > > Or more basic question does EDK support Synplicity at all? > > Thanks > brijesh > > > Brijesh wrote: > > > Hi, > > > > My set up is > > EDK 6.1 > > ISE 6.1 (no XST) > > Synplicity > > Memic VitexII Pro Dev board P4 FG 456 > > > > The tutorial expects you to use Xilinx synthesis tool XST. During > > initial XPS wizard didnt give me an option to choose the synthesis tool. > > The Drop down menu had only one option "None". > > > > I went ahead with the steps and managed to export the project to ISE > > project Navigator. Had to manually add the system.vhd and other files. > > Then I had the following problems. > > > > 1) The bus format in the UCF files had to be changed from <> to (). > > 2) Got stuck with this error messages > > > > ERROR:NgdBuild:704 - The BRAM instance > > 'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0' > > could not be found in the netlist. Please verify the instance name in > > the BMM file and the netlist. > > > > ERROR:NgdBuild:604 - logical block 'system_dcm' with type > > 'system_dcm_wrapper' could not be resolved. A pin name misspelling can > > cause this, a missing edif or ngc file, or the misspelling of a type > > name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'. > > > > The "synthesis" folder does have the file "system_dcm_wrapper_xst.srp". > > I guess the last _xst is for XST specific. Do I just rename the file? or > > how do I move ahead with the tutorial using Synplicity for my synthesis. > > > > Any clues on how to proceed would be appreciated. > > Thanks > > brijeshArticle: 68671
What a waste of time and bandwidth. I ask a simple question about SPI ports on Nios and I get an unrelated link to read as a response. ARGHHHHH!!!!!!!!!!!!!!!!!!!!!!!!! KenArticle: 68672
Hi, I am fairly new to FPGAs. I am trying to write the constraints for the PCI module on an Altera Stratix device. I am using QuartusII for all synthesis and P&R. The PCI spec says I need to ensure a setup time of 7ns for all pins. The PCI clock itself works at 33Mhz. I want to know the following: 1) Is it okay if I just constraint the PCI clk of my design to 50Mhz (30ns for the 33Mhz clock and another 10ns to ensures that the setup time is met)? I realise this will be an overkill on the internal logic but may save me some effort. 2) The other way I think to do this is to constraint the PCI clk to 33MHz and specify the external delay on all the PCI signals to 7 or 8ns. While setting PCI clk to 33Mhz I also ticked the option of including external delays in the frequency calculation. Is this the correct approach? OR do I need to setup the tco. Thanks in advance. Regards TushitArticle: 68673
Dave, Thanks for your response. If I may address some of these points one last time... 1. I understand that you don't have constraints for all these designs, but for the designs you ran the benchmarks on, wouldn't it be more thorough to include the I/O timing for the critical path as well? Since you already have the data, it shouldn't be much more effort. Would it be possible to at least show an average Tsu/Tco change on the critical paths for the benchmark designs? I'm not disputing your claims of a 5% difference, but without that data, I'm only getting numbers for the middle slice of the path. 2. Could you provide the approximate average age of these designs? Also could you comment on whether you think some of the discrepancy in the benchmarking results is due to tool/architecture tuning to these designs? If the designs were used during Altera's tool/architecture development, then they should (and hopefully would) favor an Altera implementation. 3. Sounds reasonable enough :) SD davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0404121927.578e3c74@posting.google.com>... > SD, > Responding to your points . . . > 1. I/O was not taken into account on the benchmarks that we published. > Altera has run numersous experiments to measure the impact of I/O > constraints on fMAX performance. We found that typically these > constraints change the relative performance advantage (or > disadvantage) by less than 5%, or had relatively minimal impact. We > left them out of this analysis for 2 reasons - 1st we do not have I/O > constraints for all of our designs (not all customers provide them to > us) and 2nd they add complication to (Altera's internal) goal of > automating this benchmark process so that it is repeatable with each > new software release or new silicon architecture. > > 2. We add designs to our benchmark suite as we get them (after they go > through a rigorous process of optimizing the HDL code for both Altera > and competitive architectures and verifying the results to ensure that > any outlying results are legitimate). > > 3. We do not use any manual placement for these benchmarks. Reason > here is again need to have a methodology that is both automated and > repeatable. Critical path information is a critical tool utilized for > improving place & route / fitting algorithms - so we regularly analyze > this information, though not from the context of evaluating > improvement through manual placement. > > Dave Greenfield > Altera Product Marketing > > > > I had three points relating to the seminar in question that I hope you > > can address: > > > > 1) Was I/O timing taken into account at all for the benchmarks? Did > > the designs have I/O constraints? I would have liked to see both the > > Tsu and Tco on the critical path, instead of just the Fmax, since > > these can be traded off in many situations. In fact, a higher core > > Fmax at the expense of system Fmax may be useless in many > > applications. > > > > 2) How long has Altera had these 75 designs? Part of the discrepancy > > in performance between the two vendors may be that the tools, and > > possibly even the architectures, have been tuned to their in-house > > designs. > > > > 3) For your "best effort" comparision, did you use any manual > > placement/routing for either of the tools? Did you analyze the > > critical path of either vendor for possible improvement through manual > > intervention? > > > > SD > > > > > >Article: 68674
Rajeev, although I can't disclose the detailed roadmap here, I can tell you that demand for DSP Builder continues to increase rapidly and we plan to have multiple product releases this year. These product releases will fix issues found by users and add new features to improve the capabilities and ease of use of this tool. Brian Jentz Altera DSP Product Marketing rrr@ieee.org (Rajeev) wrote in message news:<c0f37b00.0404120503.173ee3a3@posting.google.com>... > Hello, > > Welcome aboard, Dave. > > davidg@altera.com (Dave Greenfield) wrote in message > news:<5c156a0b.0404091635.6091f8fe@posting.google.com>... > > > While I don't know what "PM" means, there was no applicable follow-up > > In this context PM appears to be Pure Marketing. > > > Altera will respond to technical issues on this newsgroup (ideally > > Altera's increased activity over the past 18 months has positively > > contributed to this group). We will generally refrain from providing > > I for one have been delighted to see more Altera presence at this group. > Greg, Vaughn, Paul, Hong and others have provided valuable support in > this forum. > > It bears mention, however, that I have a paid Quartus subscription > and an active mySupport account ! Yet the caliber of support I can > get here, both from Altera and non-Altera folk, far surpasses what > your company sees fit to provide through mySupport. > > For example, I posted 4 mySupport requests during the month of March. > One generated a response "I submitted a Software Problem Report for > this issue. It will be resolved in a future release of DSP Builder". > Another -- in regard to AsyncClear on registered ports of Stratix > memory blocks -- got me after 3 weeks a response "Asynclear is not > support is stratix memory block", which I believe to be factually > in error. The other two queries are gathering dust. > > The upshot of this is that you have a user like myself, who is happy > with the Stratix chips and likes the Quartus software, yet I would > not hesitate to do my next design in Xilinx. > > > marketing information here ? though we may point requesters to a > > location where they can get marketing data. However, we will > > selectively respond with marketing information where it is warranted > > (i.e. when responding to direct competitive questions, incorrect > > information, or competitor's claims). > > > And this certainly applies to postings from any individual who > > consistently uses a cloak of being just a technical person while > > regularly dishing marketing data. > > I for one have not been put off by marketing content from Austin, > nor for that matter from your colleagues at Altera. > > And here is a marketing question for you: > > What are Altera's plans with regard to DspBuilder ? I find it a > buggy product, to the point where I find it amazing that it has been > brought to us by the same team that brought us MaxPlusII and Quartus > II -- both of which are truly first-rate. Is DspBuilder going to > languish as a marketing counterpoint to Xilinx SystemGenerator, or > is it going to brought up to the standard of Quartus ? > > Sincerely, > -rajeev-
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