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I should interface the my SoC with an HITACHI SP14Q005 display, 320x240 pixel. There is someone who could tell me what to do to write text on display?Article: 79451
Hello Piotr, With a 1C20, speedgrade 6 and Quartus physical synthesis, I achieve 116 MHz (fast-fit in contrast: 92MHz), with speedgrade 8 (a bit cheaper...) this drops to 89 MHz (typical design, with SDRAM-controller). The real fmax of course depends on your design, e.g. which periperals you are using, how full your chip is, etc. If you need the CPU only for simple control tasks, you might also considering to use our ERIC5 (www.entner-electronics.com). However, there is no support for fast multiplications and divisons, it is more comparable to a ATMEL AVR in performance (but higher fmax). Regards, Thomas "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> schrieb im Newsbeitrag news:cv63gb$to$1@news.dialog.net.pl... > Hello, > > how fast a Nios processor can be if embedded > in a speed grade 6 Cyclone FPGA? What is the > approximate maximum reachable clock frequency? > > Best regards > Piotr Wyderski >Article: 79452
Marco wrote: > I should interface the my SoC with an HITACHI SP14Q005 display, 320x240 pixel. > > There is someone who could tell me what to do to write text on display? http://www.fpga4fun.com/GraphicLCDpanel3.html rickArticle: 79453
Kevin Neilson wrote: > There was a thread recently about how to protect IP, and one respondent said > that it is too much trouble to worry about protecting IP and a better model > is to just sue anybody that steals it. This seemed perhaps naive since > there are places where IP rights are not respected and attempts to sue will > probably be fruitless. Here is an excerpt from an article in the NY Times > that illustrates this: > > > "The Chinese are adept at copying and quite loose in their interpretation of > intellectual property rights. One of Mr. Fishman's more striking examples is > the auto industry, which looms large in China's economic plans. American and > Japanese companies spend $1 billion to $2 billion to develop a new car. The > Chinese, by forcing foreign car companies to form joint ventures with their > companies and to share their technology in order to enter China, hope to > leapfrog over those kinds of development costs. > Foreign companies, salivating at the thought of 100 million Chinese > customers, cannot stop themselves from signing on the dotted line. > Sometimes, rude surprises await. At the 2003 Shanghai auto show, G.M. > executives unveiled a new $9,000 small family van, only to discover an > identical vehicle, priced at $6,000, at a Chinese booth in the same row. The > clone was made by Chery, a Chinese company owned in part by Shanghai Auto, > G.M.'s joint-venture partner. " > > I think the next generation of FPGAs with encrypted bitstreams will delay the opposition by a few months at least and allow developers to get their product to market ahead of their rivals. However, I cannot help feel that a lot of companies in Europe and America participate in "reverse engineering" as a means of understanding a rivals technology rather than invest in research themselves. So although this article has specifically mentioned China, engineers all around the world are working with their IP lawyers in ways to "work-around" other peoples IP. In order to protect IP you are far better off placing a lot of dummy components and FPGAs in your design. This will not only confuse your rivals, it will also impress the management. ;-) Regards BenArticle: 79454
Peter Alfke wrote: > Here are the answers from our spreadsheet: > Assuming 70% device utilization (which has an impact on jitter) and a > -11 speedgrade, > a 100 MHz clock multiplied by 3, divided by 1 in FX mode generates a > jitter of 29% or 987 ps. > Duty-cycle distortion is a non-issue in Virtex-4, where it is very > small. > I do not have data for the jitter toleance of your receiving SERDESes. Thanks a lot for the fast feedback. Maxim specifies for a bit rate of 600 Mbps (datarate 500Mbps) a tightened upper Limit of marginal jitter: 468 ps. So it will require another way of clock generation. Probably I can use the CLK2X output a DCM, and use a 150Mhz external clock (150Mhz = CLKIN_FREQ_DLL_LF_MS_MAX ...). The total jitter will then be ±200 ps generate by the DCM. I can't find the duty-cycle distortion of the CLK2X output, the Virtex-4 Data Sheet is somewhat vague here. It's say in Table 36 of ds302.pdf that CLKOUT_DUTY_CYCLE_DLL = +- 150ppm for DLL outputs CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. Further it says CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE). So for CLK2X, CLK2X180, and CLKDV the spec is +- 150ppm? Then, in total the jitter will be 200+150=350ps, leaving 100ps margin for external imperfections, like the cable (will be short), seems to be ok. Another option would be using a 300Mhz external LVDS oscillator, however that will cost as much a bunch of external serialisers. Any other idea's? RoelArticle: 79455
hi Is someone aware that distributed shared memory machine has been implemented in Xilinx FPGA and reported. If yes, could you pointing me ? Thankyou for any resource, information and your guide.Article: 79456
probably something like
---------------------------------
signal cpt : integer range 0 to 15; --i'm not sure for this declaration
usually i use only std_logic with convertion
signal temp : std_logic_vector( 15 downto 0);
process(clk)
begin
if rising_edge(clk) then
cpt <= cpt +1 ;
if cpt = 0 then
temp <= in_parallel;
end if;
out_serie <= temp(cpt);
end if;
end process;
----------------------------------------
there is many others way to do it you just have to test different solution
to get the better and have imagination...
alexis
"bob" <kmart@nospam.com> a écrit dans le message de news:
jgpb11pishb8c3lqkt6s49lo7hhve16674@4ax.com...
> Shift register example?
> Hi I am looking for a parallel in serial out latching shift register
> in VHDL.
> I want 16 bits but any example would be appreciated.
>
> Thanks
>
Article: 79457Don't forget about XESS website (http://www.xess.com). They have a VGA display example on their Examples webpage: http://www.xess.com/ho03000.html The file links are: http://www.xess.com/appnotes/an-101204-vgagen.pdf http://www.xess.com/projects/an-101204-vgagen.zip It is intended for their products but it is generic enough where it can be used with other designs. Derek FAS3 wrote: > Hello: > > Does anyone have a opb vga core for the MicroBlaze? > > ThanksArticle: 79458
Does there is a free version of EDK and Microblaze , because some month ago i bought a digilent spartan3 form an non official distributor of xilinx (lextronic.fr) board but at this time there were no cd given with it. so can I download a version in xilinx's website?? Because I didn't find a link as for ISE foundation Thank you Alexis.Article: 79459
Hello Piotr, With a 1C20, speedgrade 6 and using Quartus physical synthesis, I achieve 116 MHz (using fast-fit, in contrast: 92MHz), with speedgrade 8 (a bit cheaper...) this drops to 89 MHz (typical design, with SDRAM-controller). The real fmax of course depends on your design, e.g. which periperals you are using, how full your chip is, etc. If you need the CPU only for simple control tasks, you might also considering to use our ERIC5 (www.entner-electronics.com). However, there is no support for fast multiplications and divisons, it is more comparable to a ATMEL AVR in performance (but higher fmax). Regards, Thomas P.S.: This is the 2nd try, the first one did not pop-up here. If you get it twice, please execuse... "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> schrieb im Newsbeitrag news:cv63gb$to$1@news.dialog.net.pl... > Hello, > > how fast a Nios processor can be if embedded > in a speed grade 6 Cyclone FPGA? What is the > approximate maximum reachable clock frequency? > > Best regards > Piotr Wyderski >Article: 79460
Thanks a lot Jon, I missed that, or maybe I was too lazy to read manual ;-) Regards, Moti.Article: 79461
Hi, I'm a student new to fpga design and am trying to design a board with a spartan-3, 2x(1Mx16) SRAM's, a 2Mx16b FLASH, and a coolrunner-II cpld; all sharing a common address/data bus. I'm interested in accomplishing the following: 1. The ability to configure the spartan-3 from FLASH using the CPLD. 2. Access to SRAM, FLASH, and a few memory mapped cpld registers using the Xilinx EDK/EMC core. My confusion is with regards to how the address bus should be connected to the FLASH and SRAM's. The design's I have seen seem to connect the FLASH A0 to A1 or A2 of the FPGA address bus. Similarly the RAM is then connected to A2. My suspsion is that this is related to the data width of each device or the size of the data that is allowed to be written? I should note that my SRAM's are being used as a single 32b-wide memory and the FLASH and CPLD are only 16b wide. Anyway if someone could clarify the issue it would be much appreciated. MattArticle: 79462
Hi all I re-found once again my own "Rules of Life" what I first published 21 aug 2001 1 No Promises. 2 Keep Promises. 3 Give away what you do not need. 4 Do what you want to do. 5 Be Happy. In order to comply with Rules [5], [4] and specially [3] from the above list, I am giving a promise (those braking rule #1) that I will make all projects of my past live available as public domain. That includs all I can publish (ie all that IP that belongs to me and is not covered by 3rd party agreements), with the exception of maybe a few selected projects I am actually working on at the moment. In order to comply with [2] first project is made public today at: http://gforge.openchip.org there is OPB I2C IP-Core that uses the OpenCores I2C Core by implementing a OPB 2 Wishbone adapter. There seems to be still ongoing interest in OPB Wishbone wrappers so that sounded like a good thing to start! Antti PS as per rule #2 there is no fixed timeline how fast I will upload the projects, I started the process and will keep it going but it may take time :)Article: 79463
"Matt" <mhilt1@binghamton.edu> schrieb im Newsbeitrag news:1108831530.424417.75300@z14g2000cwz.googlegroups.com... > Hi, > > I'm a student new to fpga design and am trying to design a board with a > spartan-3, 2x(1Mx16) SRAM's, a 2Mx16b FLASH, and a coolrunner-II cpld; > all sharing a common address/data bus. I'm interested in accomplishing > the following: > > 1. The ability to configure the spartan-3 from FLASH using the CPLD. there are several appnotes with hdl source for this > 2. Access to SRAM, FLASH, and a few memory mapped cpld registers using > the Xilinx EDK/EMC core. its doable > My confusion is with regards to how the address bus should be connected > to the FLASH and SRAM's. The design's I have seen seem to connect the > FLASH A0 to A1 or A2 of the FPGA address bus. Similarly the RAM is > then connected to A2. My suspsion is that this is related to the data > width of each device or the size of the data that is allowed to be > written? I should note that my SRAM's are being used as a single > 32b-wide memory and the FLASH and CPLD are only 16b wide. Anyway if > someone could clarify the issue it would be much appreciated. > > Matt the EDK bus-bit ordering IS confusing, in most cases it causes problem at first trial attempt. Also note that the EMC core has a bug when using Flash that is not 32 bit wide the bus-widht matching logic generates 2 CEn pulses per 16bit memory access to additional logic that filters the second pulse out is required if you want to program the flash from the microblaze AnttiArticle: 79464
Thanks Antti! You are a very generous person. There is a philosophy that you reap what you sow. It will be interesting how this comes back to you. -Newman "Antti Lukats" <antti@openchip.org> wrote in message news:cv7qqk$7le$02$1@news.t-online.com... > Hi all > > I re-found once again my own "Rules of Life" what I first published 21 aug > 2001 > > 1 No Promises. > 2 Keep Promises. > 3 Give away what you do not need. > 4 Do what you want to do. > 5 Be Happy. > > In order to comply with Rules [5], [4] and specially [3] from the above > list, I am giving a promise (those braking rule #1) that I will make all > projects of my past live available as public domain. That includs all I > can > publish (ie all that IP that belongs to me and is not covered by 3rd party > agreements), with the exception of maybe a few selected projects I am > actually working on at the moment. > > In order to comply with [2] first project is made public today at: > http://gforge.openchip.org > > there is OPB I2C IP-Core that uses the OpenCores I2C Core by implementing > a > OPB 2 Wishbone adapter. > > There seems to be still ongoing interest in OPB Wishbone wrappers so that > sounded like a good thing to start! > > Antti > > PS as per rule #2 there is no fixed timeline how fast I will upload the > projects, I started the process and will keep it going but it may take > time > :) > >Article: 79465
Roel wrote: > Peter Alfke wrote: > >> Here are the answers from our spreadsheet: >> Assuming 70% device utilization (which has an impact on jitter) and a >> -11 speedgrade, >> a 100 MHz clock multiplied by 3, divided by 1 in FX mode generates a >> jitter of 29% or 987 ps. >> Duty-cycle distortion is a non-issue in Virtex-4, where it is very >> small. >> I do not have data for the jitter toleance of your receiving SERDESes. > > Thanks a lot for the fast feedback. > > Maxim specifies for a bit rate of 600 Mbps (datarate 500Mbps) a > tightened upper Limit of marginal jitter: 468 ps. > > So it will require another way of clock generation. Probably I can use > the CLK2X output a DCM, and use a 150Mhz external clock (150Mhz = > CLKIN_FREQ_DLL_LF_MS_MAX ...). The total jitter will then be ±200 ps > generate by the DCM. I can't find the duty-cycle distortion of the CLK2X > output, the Virtex-4 Data Sheet is somewhat vague here. It's say in > Table 36 of ds302.pdf that CLKOUT_DUTY_CYCLE_DLL = +- 150ppm for DLL > outputs CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. Further > it says CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, > CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE). So for > CLK2X, CLK2X180, and CLKDV the spec is +- 150ppm? > > Then, in total the jitter will be 200+150=350ps, leaving 100ps margin Oops, 150ppm is not 150ps but 0,5ps in the case of 300Mhz. Roel > for external imperfections, like the cable (will be short), seems to be ok. > > Another option would be using a 300Mhz external LVDS oscillator, however > that will cost as much a bunch of external serialisers. > > Any other idea's? > > RoelArticle: 79466
Thanks for the reply. I think however that my concern at this point is less with the EMC and more with how the address signals should be connected on the board. Should the address bus look like: Flash_A0 --- SRAM_A0 --- FPGA Flash_A1 --- SRAM_A1 --- FPGA Flash_A2 --- SRAM_A2 --- FPGA ... or ( as I've seen it elsewhere) Flash_A0 --- FPGA Flash_A1 --- SRAM_A0 --- FPGA Flash_A2 --- SRAM_A1 --- FPGA ... MattArticle: 79467
Let me know, I'd like to think we can look these things up very quickly to at least let you know which fab, which assembly (packaging house), etc. Austin IgI wrote: > No, there isn't any reason, I simply forgot. We had to solve the problem the > fastest we could, because the customers are waiting for the products. And > the fastest way was to exchange the chips with the "good" ones. I still have > 5 PCBs with problematic chips. We will analyze them further on Monday. If we > don't come up with some reasonable explanation, I will open a web-case. > > Igor Bizjak > > "Austin Lesea" <austin@xilinx.com> wrote in message > news:cv5nkc$qgu1@cliff.xsj.xilinx.com... > >>Igor, >> >>Any reason why you haven't open a web-case? Or called the hotline? >> >>With your "lines down" situation, you should be moved to the head of the >>line, and be given the highest level of service. >> >>Let me know, >> >>Austin >> >> >> >>IgI wrote: >> >>>Hi! >>> >>>I'm using Virtex-II (XC2V1000-FF896-4C) in one of the product which we > > have > >>>been selling for over 3 years. Recently we got "new" batch of Virtex-II >>>chips and problems started to arise. So far I have isolated PCBs with > > three > >>>different batch of Virtex-II chips: >>> >>>Batch A: >>>XC2V1000 >>>FF896AFT0301 >>>F1247582A >>>4C >>>Philippines >>> >>>Batch B: >>>XC2V1000 >>>FF896AGT0409 >>>D2169507A >>>4C >>>Taiwan >>> >>>Batch C: >>>XC2V1000 >>>FF896AFT0205 >>>F1205613A >>>4C >>>Philippines >>> >>>All the chips in batch A have the suffix AFT301, all the chips in batch > > B > >>>have the suffix AGT0409,... >>>PCBs with chips from batch B and C are working fine, on the other hand > > none > >>>of the 42 PCBs, where chips from batch A are used are working. PCBs are > > the > >>>same (same revision) for all the products, all other components > > (ZBTRAMs, > >>>DDR SDRAMS, passive components,....) are the same. All voltages are > > within > >>>the safe margins, all input clocks are clean. All the affected boards > > pass > >>>the JTAG test, in other words we didn't find any soldering errors, short >>>circuits, vias without metallization, wrong resistors or capacitors, >>>incorrectly oriented diodes or capacitors... or any other error we could >>>think of. We got all the chips in a sealed package. PCBs were tested at >>>different temperatures (from 8 degrees Celsius to 46). Only the PCBs > > with > >>>chips from batch A don't work. Let me explain what precisely is not > > working. > >>>I'm using 6 DCMs to generate clocks for ZBTRAM, DDR, System, > > ConfigBus,... > >>>and two DCMs don't set the locked signal after I release them > > sequentially > >>>from reset. I don't know if other parts of the design (the parts which > > don't > >>>use ZBTRAM clock) don't work either, because the missing clock is a > > fatal > >>>error and I didn't have the time to investigate further in that > > direction. > >>>Working freq. of ZBTRAM is 120MHz, DDR is working at 166MHz, System at >>>100MHz, ConfigBus at 10MHz,... >>> >>>We are currently using ISE 5.2 SP3 for this design. I have verified the > > bit > >>>stream by reading it back from the chip and it's ok. >>>Two coworkers, guys from the production and I are working on solving > > this > >>>problem for the last two days and we are almost out of ideas what else > > we > >>>could try, except replace the problematic chips with the > > non-problematic. I > >>>can't use ISE 6.1 or newer because the routing is not successful or ISE >>>simply doesn't meet the timing constraints (the chip is 99% full). >>> >>>Have you experienced anything similar in the past? How did you solve the >>>problem? Do you have any ideas/suggestions what else I could try? I > > couldn't > >>>find any document on the xilinx web site explaining the detailed chip >>>signatures. I would like to know, what AFT0301 stands for? Is this the >>>product date, production line, factory code...? I would like to know, > > when > >>>the chips have been manufactured (how old are they)? >>> >>>I guess we'll have a competition in the company next week. And the goal > > will > >>>be; who can throw virtex-II the farthest... Ok, I'm just joking, but I >>>needed to vent...argh... >>> >>> >>>Igor Bizjak >>> >>> > > >Article: 79468
Kenneth Land wrote:
> The data master of the Nios is not latency aware and even hand assembly
> coded back to back reads to sequential addresses in sdram will be no
faster
> than 11+ clocks per read.
That's bad, why hasn't Altera done something with this?
> So heres the answer: dma's, and all writes are fast.
> Avoid non-dma reads whenever possible.
I'm going to use intensively the internal RAM blocks.
> Hope this helps.
Of course, thanks!
Best regards
Piotr Wyderski
Article: 79469Paul, To save you the embarrasment, I sent my reply to you directly. Austin Paul Leventis (at home) wrote: >>I am sorry, but you have never run a spice simulation of midox pass >>transistor vs thin ox. > > > I am sorry Austin, but how exactly is it that increasing oxide thickness > does not decrease transistor speed? Increased tox = decreased beta = > decrease Ids. And the Vt increases with tox too, unless you adjust the > implant levels for those transistors (at the expensive of another mask and > processing step). If there were truely no speed implications of using > thicker oxide transistors, we'd all be using thick oxide transistors > everywhere and bragging about are "Single Gate Oxide" technologies!. > > There are places where slower transistors (be it longer gates, higher Vt, or > thicker oxide) are more tolerable than others. For example, the > configuration rams (no impact on speed). Are the pass gates one of those > places? Maybe -- depends on speed vs. leakage goals and the exact result > you get from your sim. Arguing that there is no speed loss and no > complexity increase whatsoever though is silly. > > Regards, > > Paul Leventis > Altera Corp. > >Article: 79470
Thanks Newman, I think you are right. My problem is how I interpret the waveforms not with the FIFO simulations themselves. There is something else wrong with my design, but I now have both the behaviour and the PAR sims working the same way. BradArticle: 79471
Well there are some things you need to figure out yourself, others cant know what you want todo. If you want to play with ML310, then do so! Just grab some IP cores and try them out! There is plenty of stuff around. But you must do something yourself. As of being freelancing hardware developer, you would need a real long real life experience before, and even so its not an easy life. AnttiArticle: 79472
Hi, Why do you need a FIFO? Is it similar to GBUF, IBUF for clocks to buffer the signals for stability or more like temporary memory? If it's more like temporary memory, then why not just use intermediate signals to store input signals and delay them (use shift register) a specific number of clocks if needed? Also, is FIFO a Xilinx primitive component available with Webpack? ThanksArticle: 79473
"Matt" <mhilt1@binghamton.edu> wrote in message news:1108840197.634046.211860@l41g2000cwc.googlegroups.com... > Thanks for the reply. I think however that my concern at this point is > less with the EMC and more with how the address signals should be > connected on the board. Should the address bus look like: > > Flash_A0 --- SRAM_A0 --- FPGA > Flash_A1 --- SRAM_A1 --- FPGA > Flash_A2 --- SRAM_A2 --- FPGA ... > > or ( as I've seen it elsewhere) > > Flash_A0 --- FPGA > Flash_A1 --- SRAM_A0 --- FPGA > Flash_A2 --- SRAM_A1 --- FPGA ... > > Matt > I really think that the answer requires reading the data sheet of the particular memory devices you want to use. For two TH50VSF2881AASB 16 bit SRAM/FLASH devices for a Big Endian Bus, I have FPGA_sram_addr<29> AB_MemChip_A0 FPGA_sram_addr<28> AB_MemChip_A1 ..... FPGA_sram_data<31> B_MemChip_DQ0 FPGA_sram_data<30> B_MemChip_DQ1 .... FPGA_sram_data<15> A_MemChip_DQ0 FPGA_sram_data<14> A_MemChip_DQ1 .... FPGA_sram_cen<0> AB_MemChip_CE1SN FPGA_sram_cen<1> AB_MemChip_CEFN FPGA_wen AB_MemChip_WEN FPGA_oen AB_MemChip_OEN FPGA_sram_ben<1> A_MemChip_LBN FPGA_sram_ben<0> A_MemChip_UBN FPGA_sram_ben<3> B_MemChip_LBN FPGA_sram_ben<2> B_MemChip_UBN I did this by hand, so there may be typo's -NewmanArticle: 79474
Unfortunatly you cannot use shift registers where you need to transfer data from a high speed input to a low speed output for example.The uses of fifos are too numerous to list here but they are very useful so thats why people use them,and have done for many years its just that xilinx have them as part of some of their FPGAs.
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