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thanks for the tip.. I found thin on the net and it work pretty well In the meantime, you can use the following flow to instantiate the ILA core in an EDK design. To use this flow, you must have EDK 6.2 and ChipScope Pro 6.2i with the latest Service Packs for both. If you are NOT using the MDM Debugger (Xilinx Answer 19412) NOR any ChipScope Cores (such as IBA or VIO) in your EDK design, you can follow these steps: 1. Create your EDK design using XPS. 2. Go to "Tools" and "Generate Netlists". 3. Exit XPS. 4. On the command line, go to the <project_directory>/implementation. 5. Enter the following command: ngcbuild -i system.ngc system_all.ngc This command links your top-level with all of the IPs instantiated in your EDK design to produce one large netlist. 6. Run ChipScope Inserter 6.2i. 7. Select the "system_all.ngc" file as your input netlist. 8. Select the "system.ngc" file as your output netlist (this overwrites the "system.ngc" file created by XPS). Make sure that the folder is still <project_directory>/implementation. 9. Use the online ChipScope Pro 6.2i User Manual to connect your clock/triggers/data: http://www.support.xilinx.com/literature/literature-chipscope.htm 10. Save the project with File ->Save As. This command creates a CDC file that is required for ChipScope Pro Analyzer. 11. Exit ChipScope Inserter. 12. Run XPS. 13. Go to "Tools" and "Generate Bitstream". 14. Run the FPGA Editor and open the "system.ncd" file in <project_directory>/implementation. 15. Go to "Tools" and "ILA" to make sure that the ILA is correctly implemented in your design. If a message occurs stating "There is no ILA core", check the component list for instances starting with U_icon_pro or U_ila_pro. If you have these instances, the ILA is correctly implemented. 16. Finally, you can run ChipScope Pro Analyzer 6.2i (follow the ChipScope User Manual for this tool) to program the FPGA using the "system.bit" file in project_directory>/implementation, and start debugging your design. You can also import the CDC file saved previously in the ChipScope Inserter to recover the name of your signals NOTE: One limitation is that every time you modify the MHS file in XPS, you must run NGCBuild on the command line (ngcbuild -i system.ngc system_all.ngc) , and run ChipScope Inserter, since XPS will overwrite the "system.ngc" file. regards Jonathan "newman" <newman5382_nospam@yahoo.com> a 閏rit dans le message de news: euoTd.105556$qB6.91444@tornado.tampabay.rr.com... >A while back, I tried adding chipscope to an existing PPC design, and it >broke the design. I ended up using the ChipSope Inserter tool instead, and >was happy with the results. > As a first attempt, I would use the inserter method. > > - Newman > > "Jonathan Dumaresq" <jdumaresq@cimeq.qc.ca_nospam> wrote in message > news:e9oTd.46341$6f.18104@charlie.risq.qc.ca... >> Hi all, >> >> I try to make a system with a chipscope in it. >> >> I want to try it to know if this tools what we think they suppose to do. >> >> So here what i have done: >> >> 1 - create a new system with a microblaze in it. >> 2- debug to none >> 3- memory blok 8K >> 4- i juste take the default peripheral in the rest of the wizzard >> 5-put the chiscope_icon >> 6- put the chipscope_ila >> 7- try to make the bitstream >> >> and the result: >> >> ERROR:NgdBuild:455 - logical net 'ilmb_LMB_BE<0>' has multiple drivers. >> The >> >> possible drivers causing this are: >> >> pin G on block XST_GND with type GND, >> >> pin O on block >> >> chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/chipscope_ila_0/i_no_d/u_il >> >> a/u_dout with type LUT3 >> >> I don't know how to correct this error. >> >> Do I have to change something else in the ilmb ? >> >> regards >> >> Jonathan >> >> >> >> > >Article: 79826
gretzteam wrote: > Hi, > We are using a virtex4 FPGA to prototype a DSP processor to be > implemented in an ASIC. We are using the ISE flow and everything works > fine except that we can't prototype at full speed. We are only able to > run at about 65MHz, which is far from the 150MHz target. The longest > combinationnal path is in the MAC, which contains a 28x28 multiplier > followed by a 56x56 adder. I created the multiplier and the adder > using Core Generator. > > Is there a way to speed this up? The virtex4 have those Xtreame DSP > slices, but I can't find a way to to make good use of them, since our > datapath is so large. > > Thank you, > David > If you use the Xtreme DSP slices properly, with all of their dedicated interconnects, you should be able to do a 34x34 multiply using 4 pipelined slices at full rate (450-500MHz, depending upon part speed). You might need an extra two slices to do the 56-bit accumulate. Look for the "XtremeDSP Design Consdierations" guide on the Xilinx site and it describes how to do this. I'm not sure exactly what CoreGen is producing but it might not be completely optimized. It might be using CLB fabric for some of the operations. -KevinArticle: 79827
I am designing usin an xc9500 Xilinx PLD and i observed some strange behavior, wondering if anyone can confirm or deny. It appears that a macrocell is used for each output pin (or bidirectional). I get a summery like this: Total Macrocells Available 216 Registered Macrocells 124 Non-registered Macrocells driving I/O 48 My design has about 120 macrocells, and these 48 dirving are bothering me. Why does it need a macrocell for the I/O. I put the chip in low power output mode, hoping that would free them up, but no luck. Mike DArticle: 79828
Today I searched google news for Altera and found the news saying that Altera signed contract with Digikey in Feb. 15th, 2005. Now hobbists don't need to ask where to buy Altera again on the list. Still expensive though. vax, 9000Article: 79829
And Altera is notorious for end of life problems. We use xilinx exclusively because we have been burned by altera a number of times. Mike DArticle: 79830
Hi Antti,
it was very nice to meet you at the Embedded World. I have rechecked my last
MAXII-ERIC-version (as mentioned, it is not supported in the moment, but
could be "revitalised"): It needs 120 LCs (50%), when I removed some
debug-signals, I got even down to 109 (45%). This includes 9bit output-ports
and 9bit input-ports and NO RAM, just the 3 internal registers. As
mentioned, the missing RAM blocks of MAXII will reduce the usefulness of a
CPU in this "CPLD" as RAM is very expensive, even with your tricks.
The core has changed a bit since the MAXII-implemention, so LC-count might
differ slightly (up or down) if we would redo it. The Cyclone-version needs
about 110 LCells, for MAXII we can remove the PC of our core, but need to
add the UFM-flash-interface.
Even if ERIC5 gets no commercial success (how can it, at this pricing ;-),
we will survive, dont worry... Our main business is camera-design (where we
use ERIC5 for our own products) and FPGA-design.
Regards,
Thomas
www.entner-electronics.com
P.S.: The exact resource usage summary:
Logic cells 109 / 240 ( 45 % )
Registers 103 / 240 ( 42 % )
Total LABs 16 / 24 ( 66 % )
Logic elements in carry chains 14
User inserted logic cells 0
Virtual pins 0
I/O pins 20 / 80 ( 25 % )
-- Clock pins 0
Global signals 1
UFM blocks 1 / 1 ( 100 % )
Global clocks 1 / 4 ( 25 % )
Maximum fan-out node clk
Maximum fan-out 104
Total fan-out 601
Average fan-out 4.62
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
news:cvc4va$2li$04$1@news.t-online.com...
> "Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag
> news:42176496$0$33864$91cee783@newsreader01.highway.telekom.at...
>> Hello Piotr,
>>
>> With a 1C20, speedgrade 6 and using Quartus physical synthesis, I achieve
>> 116 MHz
>> (using fast-fit, in contrast: 92MHz), with speedgrade 8 (a bit
>> cheaper...)
>> this
>> drops to 89 MHz (typical design, with SDRAM-controller). The real fmax of
>> course depends on your design, e.g. which periperals you are using, how
> full
>> your chip is, etc.
>>
>> If you need the CPU only for simple control tasks, you might also
>> considering to use our ERIC5 (www.entner-electronics.com). However, there
> is
>> no support for fast multiplications and divisons, it is more comparable
>> to
> a
>> ATMEL AVR in performance (but higher fmax).
>
> Hi Thomas,
>
> could you please give Quartus resource utilization for ERIC5 when
> targetting EPM240 and executing from UFM?
> On your website you claim it would be 50% and that ERIC5 was
> initially targetted for MAX2. I am just curious to see that report :)
>
> Antti
> PS the two other companies that used to offer 9-Bit processors
> IP-Cores are now dead and vanished, hope you have better luck!
>
>
Article: 79831
In fact you want to know the number of bit at level '1' ? if is that what
you want do try :
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity essai is
Port ( clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(249 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end essai;
ARCHITECTURE Behavioral OF essai IS
signal data_in_reg : unsigned(255 downto 0);
signal result_level1: unsigned(255 downto 0);
signal result_level2: unsigned(191 downto 0);
signal result_level3: unsigned(127 downto 0);
signal result_level4: unsigned(79 downto 0);
signal result_level5: unsigned(47 downto 0);
signal result_level6: unsigned(27 downto 0);
signal result_level7: unsigned(15 downto 0);
signal resultat :std_logic_vector( 8 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
data_in_reg <= "000000" & unsigned(data_in);
--1st level
for i in 0 to 127 loop
result_level1(2*(i+1)-1 downto 2*i) <= ('0'& data_in_reg(2*i)) + ('0' &
data_in_reg(2*i+1)) ;
end loop;
--2st level
for i in 0 to 63 loop
result_level2(3*(i+1)-1 downto 3*i) <= ('0'& result_level1( 4*i+1 downto
4*i)) + ('0' & result_level1((4*i+3) downto (4*i+2) )) ;
end loop;
--3st level
for i in 0 to 31 loop
result_level3(4*(i+1)-1 downto 4*i) <= ('0'& result_level2( 6*i+2 downto
6*i )) + ('0' & result_level2((6*i+5) downto (6*i+3) )) ;
end loop;
--4st level
for i in 0 to 15 loop
result_level4(5*(i+1)-1 downto 5*i) <= ('0'& result_level3( 8*i+3 downto
8*i )) + ('0' & result_level3((8*i+7) downto (8*i+4) )) ;
end loop;
--5st level
for i in 0 to 7 loop
result_level5(6*(i+1)-1 downto 6*i) <= ('0'& result_level4( 10*i+4 downto
10*i )) + ('0' & result_level4((10*i+9) downto (10*i+5) )) ;
end loop;
--6st level
for i in 0 to 3 loop
result_level6(7*(i+1)-1 downto 7*i) <= ('0'& result_level5(12*i+5 downto
12*i)) + ('0' & result_level5((12*i+11) downto (12*i+6) )) ;
end loop;
--7st level
for i in 0 to 1 loop
result_level7(8*(i+1)-1 downto 8*i) <= ('0'& result_level6(14*i+6 downto
14*i)) + ('0' & result_level6((14*i+13) downto (14*i+7) )) ;
end loop;
resultat <= std_logic_vector(unsigned('0' & result_level7(7 downto 0)) +
unsigned('0' & result_level7(15 downto 8)) );
data_out <= resultat(7 downto 0);
end if;
end process;
end Behavioral;
data_in is your 250bits input and data_out is the number of bit of data_in
at '1'
the result arrived 8cycle afters presented.
but you should have a package with enought pins
Regards,
Alexis
"blackduck" <rg66@le.ac.uk> a 閏rit dans le message de news:
1109255857.861718.71530@l41g2000cwc.googlegroups.com...
> Hi KCL,
>
> The design only receives 250 bits as inputs which are the incoming
> impulses to lowpass filters (250), these filters produce an output
> which has to be added to get the total response, then this total
> response in sent to a comparator, indication if the total response is
> greater to some value. Then in the first clock cycle, the comparator
> has zero as input from the filters, the second clock cycle, the
> comparator receives the total response from the filters and compares
> this against a value, and this process should be repeated each clock
> cycle. The device is able to run at 300 MHz, but the time required to
> get the total response is of course slower than this (plus internal
> delays), therefore I am trying to carry this process as fast as
> possible. The design has 250 bits as inputs and 1 bit output.
>
> Sorry if initially sounded as a 8000 input design.
>
> Thanks
>
Article: 79832Hi I am making a VGA display IP (receive caracter code in a buffer and display it on a VGA screen) , yet it's nearly finish (make some last parameters generics and make a documentation+ more commentary of my code) So my questions are *What kind of licensing you recommend to me (if you think it should) , I dont want to make money, I make it just for educative purpose (and also to make me a name in FPGA world :) ) *I wanted to post it on opencores.org but the website seems to be laggy :/ anywhere else where I can post it?? As I finish that IP I 'm looking for new and interesting project does anyone have any idea of IP, I can do and test at home (I 've got the digilent spartan 3 board) ?? I was thinking of doing a PS/2 keyboard interface and RS/232 port for trying to make a kind of SoC , what do you think about that?? Regards, AlexisArticle: 79833
MikeD wrote: > I am designing usin an xc9500 Xilinx PLD and i observed some strange > behavior, wondering if anyone can confirm or deny. > > It appears that a macrocell is used for each output pin (or > bidirectional). I get a summery like this: > > Total Macrocells Available 216 > Registered Macrocells 124 > Non-registered Macrocells driving I/O 48 I think beyond this 48 pins you have other pins that are driven by registed macrocells too. > > > My design has about 120 macrocells, and these 48 dirving are bothering > me. Why does it need a macrocell for the I/O. I put the chip in low > power output mode, hoping that would free them up, but no luck. I read the XC9500 user manual and I think it is designed so that you need one macrocell for each output pin. vax, 9000 > > > Mike DArticle: 79834
Kim, Yes, the Rapid Chip. Even the though the physical amount of memory is about the same (9 Mb), I need more granularity. If I remember correclty, that 9 Mb is spread over 300 - 400 RAMs, while the 2S180 has 700+ RAMs. JohnArticle: 79835
I found 2 version of this reference design on Xilinx website. ftp://ftp.xilinx.com/pub/applications/xapp/xapp661.zip (Use for EDK3.2) http://www.xilinx.com/bvdocs/appnotes/xapp661.zip (Use for EDK6.1) Anyone know is the version for EDK6.3 is available? I choose the one for EDK6.1 and try to open the "system.xmp" file by EDK6.3, the error was found as below.. Can anyone suggest how to fix it? Congratulations!! Your project has been successfully updated to EDK 6.3 PM_SPEC -- Xilinx path component is <E:/EDA/EDK> WARNING:MDT - K:\DG_IP\xapp661_2\pcores\clk_startup_v1_00_a\data\clk_startup_v2_1_0.mpd:3 Options can not be specified in the same line as "BEGIN <ipname>" WARNING:MDT - K:\DG_IP\xapp661_2\pcores\plb_icap_top_v1_00_a\data\plb_icap_top_v2_1_0.mpd:3 Options can not be specified in the same line as "BEGIN <ipname>" WARNING:MDT - K:\DG_IP\xapp661_2\pcores\plb_mgtbert_v1_00_a\data\plb_mgtbert_v2_1_0.mpd:3 Options can not be specified in the same line as "BEGIN <ipname>" ERROR:MDT - Can not find valid MPD for Ip ppc405 1.00.a INFO:MDT - Check the following for possible causes of not finding MPD: - If HW_VER is specified in MHS, it must follow literal form X.YY.Z - There is no Ip with given name - Ip exists but not that version - Ip (directory) exists but 2.1.0 MPD file is not available - Ip exist in myip directory (only pcores is supported) ERROR:MDT - Can not find valid MPD for Ip jtagppc_cntlr 1.00.a INFO:MDT - Check the following for possible causes of not finding MPD: - If HW_VER is specified in MHS, it must follow literal form X.YY.Z - There is no Ip with given name - Ip exists but not that version - Ip (directory) exists but 2.1.0 MPD file is not available - Ip exist in myip directory (only pcores is supported)Article: 79836
Hi everyone, I have a state machine which creates the following INFO when synthesised using Xilinx ISE6.1. INFO:Xst:1813 - Unable to extract FSM on signal <state> : outputs depend on both state and next state. Is this something I should be concerned about? THanksArticle: 79837
I have one of the Stratix II development kit with the EP2S60. Just out of curosity I wanted to see if how many processors I could fit on a device like that. I was able to add sixteen of the fast processors. I gave each a little on chip RAM and ROM to bootstrap with. And I implemented a SDRAM controller. That used up approximatel 78 % of the device. The discouraging factor from my little experiment was that SOPC Builder became almost impossibly slow. SOPC Builder is a JAVA application. It spent a lot of time looking for conflicts. When I have the time my next little experiment is to create a working dual or quad processor. My long term goal is create a single chip, multiprocessor, 3d - graphics system with a similar api as OpenGL. Without having researched or done it yet I would have to say that the system controller and memory is implementation dependent on the designer. DerekArticle: 79838
Thomas Entner wrote: > Hi Antti, > > it was very nice to meet you at the Embedded World. I have rechecked my last > MAXII-ERIC-version (as mentioned, it is not supported in the moment, but > could be "revitalised"): It needs 120 LCs (50%), when I removed some > debug-signals, I got even down to 109 (45%). This includes 9bit output-ports > and 9bit input-ports and NO RAM, just the 3 internal registers. As > mentioned, the missing RAM blocks of MAXII will reduce the usefulness of a > CPU in this "CPLD" as RAM is very expensive, even with your tricks. That was one of Altera's big mistakes on MAX II, they did not see the opening of state-rom and tiny-cpu coding, or Smart-UART areas, and so designed a part with no RAMs and cripled Code-FLASH.... > The core has changed a bit since the MAXII-implemention, so LC-count might > differ slightly (up or down) if we would redo it. The Cyclone-version needs > about 110 LCells, for MAXII we can remove the PC of our core, but need to > add the UFM-flash-interface. Another option to consider would be to add support for Serial memory, like Ramtrons FM25x devices. These allow any mix of RAM and CODE, and are variable sized from 4Kb..256Kb, and have 25MHz serial bus speeds. -jgArticle: 79839
appreciate. the 70 cents quote was from a Xilinx distributor in taiwan. it took me quite some effort to get this quote. So was wondering if someone has already done this research, that would save me tons of time. thanks againArticle: 79840
kowari wrote:
> INFO:Xst:1813 - Unable to extract FSM on signal <state> : outputs
> depend on both state and next state.
>
> Is this something I should be concerned about?
Not if state and next state are register outputs.
-- Mike Treseler
Article: 79841KCL wrote: > I am making a VGA display IP (receive caracter code in a buffer and display > it on a VGA screen) , yet it's nearly finish (make some last parameters > generics and make a documentation+ more commentary of my code) > So my questions are > *What kind of licensing you recommend to me (if you think it should) , I > dont want to make money, I make it just for educative purpose (and also to > make me a name in FPGA world :) ) There are a couple of common licenses that may be appropriate - some of them may even be in use (modified) for use specifically with ip cores - opencores.org should have some :) (IIRC). You could consider the (or a) BSD-style license - This basically lets anyone do anything with the code - they just have to retain your copyright notice on it (AFAIU). (http://www.opensource.org/licenses/bsd-license.php) or you could consider a GPL-style license - This puts several restrictions on what people may do with it - such as requiring them to release source if they modify it, and restricting what they can integrate it in to without releasing source. (http://www.gnu.org/copyleft/copyleft.html) One thing I guess you could consider is that the GPL can make things difficult for companies that want to integrate your IP block into a commercial product, because of the requirement to redistribute source code. You could also just make the code completely public domain (or write your own license)- there are pros and cons to each of these approaches. Good luck :) JeremyArticle: 79842
Oh ok. Next state is not a registered output. The state machine is a 2 process state machine ie the clocked process registers state from next state, and the next state process is a combinatorial process. Can you help me to understand the problem and what has been synthesised? ThanksArticle: 79843
Hi, Try an ASCII terminal implemented on the Spartan-3 Starter Kit. Go to http://www.engr.sjsu.edu/crabill and look at Lab #7. It is a fun project. I tried it myself, using PicoBlaze. Eric KCL wrote: > > Hi > > I am making a VGA display IP (receive caracter code in a buffer and display > it on a VGA screen) , yet it's nearly finish (make some last parameters > generics and make a documentation+ more commentary of my code) > So my questions are > *What kind of licensing you recommend to me (if you think it should) , I > dont want to make money, I make it just for educative purpose (and also to > make me a name in FPGA world :) ) > *I wanted to post it on opencores.org but the website seems to be laggy :/ > anywhere else where I can post it?? > > As I finish that IP I 'm looking for new and interesting project does anyone > have any idea of IP, I can do and test at home (I 've got the digilent > spartan 3 board) ?? > I was thinking of doing a PS/2 keyboard interface and RS/232 port for trying > to make a kind of SoC , what do you think about that?? > > Regards, > > AlexisArticle: 79844
I am basicaly trying to find what is the maximum current that will ever be needed for the FPGA I/0. I know it differs on application, but based on the maximum current required, I can choose the most efficient voltage regulators. The other constraint I have is the real-estate space that would be needed for heat sinking the voltage regulators For that purpose swiching regulators would be preferred. In case of TI TPS75003, its does have buck regulators for the core and I/O but it also has (I think its "inbuilt") Linear Regulator which would need heat sinking area. Maybe I am missing something totally obvious here as well. I dont have much experience in using Voltage Regulators. My basic constraint is of course is board space and I am trying to find ways to get around that.Article: 79845
DerekSimmons@FrontierNet.net wrote: > I have one of the Stratix II development kit with the EP2S60. Just out > of curosity I wanted to see if how many processors I could fit on a > device like that. I was able to add sixteen of the fast processors. I > gave each a little on chip RAM and ROM to bootstrap with. And I > implemented a SDRAM controller. That used up approximatel 78 % of the > device. The discouraging factor from my little experiment was that SOPC > Builder became almost impossibly slow. SOPC Builder is a JAVA > application. It spent a lot of time looking for conflicts. > > When I have the time my next little experiment is to create a working > dual or quad processor. My long term goal is create a single chip, > multiprocessor, 3d - graphics system with a similar api as OpenGL. > > Without having researched or done it yet I would have to say that the > system controller and memory is implementation dependent on the > designer. While the very largest FPGAs look like they could hold perhaps 1 cpu per BlockRam (perhaps even upto 100 or more), I think the middle size part will be a better fit, price closer to the min possible per BlockRam in vol, more BlockRams per 1KLuts, more total system IOs etc and more place to throw off heat and closer to higher vol price. The other question is what type of cpu arch to use, answer seems obvious to me, one that supports concurrency right in its architecture rather than foisting it on top of something with no idea what a process is. So far only the Transputer has shown how easy it is to put together 100s of cpus and how to program them. Ofcourse in an FPGA it would have to be a modern register style ld/st RISC. So what are you doing with your 160TP array and how would the perf compare with the same app running on 1 2-3 GHz x86, and did you check out the other NG? regards johnjakson at usa dot com > > DerekArticle: 79846
Hi, My goal is to use XPower to estimate the average and the peak power for a given run of a system with at least a reasonable level of accuracy. Tools used are: Xilinx Platform Studio 6.2.03i Xilinx Project Navigator 6.2.03i ModelSim SE 5.7g In order to test out the framework for evaluating power (Xpower), I have designed a Microblaze-based system with a C-application containing simple multiplication of two numbers. The whole system along with its simulation model was generated using XPS. I am using the post-place&route simulation model to generate the VCD file. The system is triggered with its external inputs clk and rst (using a testbench.vhd) and simulation is run till the software (that was hard-coded in bram_init.vhd) produced the expected output. The commands used to add signals (before simulation) to VCD are as follows: --------------------------- vcd file system.vcd vcd add testbench/uut/* --------------------------- Then I tried running XPower with the generated VCD file with '-v -a' option. Some of the warnings reported were as follows: WARNING:Power:760 - Only 10% of the register output signals have been set. WARNING:Power:762 - Only 12% of the design signals have been set. WARNING:Power:763 - Only 6% of the design signals toggle. INFO:Power:556 - Estimate is inaccurate based on analysis of the design, user input and characterization data. ------------------------------------------------------------ XPower generated the power numbers but with an inaccurate confidence level. Here are my questions: (1) How to achieve a confidence level of at least "reasonable" if not "accurate"? Observation: A file called "systemfailed.txt" was also generated reporting "activity not set" error messages for a lot of signals. The error messages were like (Signal "opb_mdm_0/bscan_update" has not had its activity set.) (2) The system clock frequency is 50 MHz. However, there were several warnings reported of the kind: "WARNING:Power:91 - Can't change frequency of net sys_clk to 5000.00Mhz." I don't know what to infer from there? Please let me know if I am missing something while setting up the framework for running XPower. Thanks and Regards, Partha.Article: 79847
Thanks all of you! I had solve the problem. And I had write something about this topic. But I writen it in chinese. Hope it useful for the newbie of EDA like me. You can find the document at : www.cnblogs.com/wantfei -- newbie in EDA Willie CHEN KMUST, CHINA "willie CHEN" <changewhere@126.com> 写入消息新闻:cvjr1m$1tb$1@mail.cn99.com... > Hi, > In my project,there's a xilinx IP core. I want to use the synplify7.7 > to synthesize it, but there's a warning when synthesize . > The warning is : > @W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":29:10:29:19|Unbound > component counter_11 mapped to black box > @W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":37:10:37:18|Unbound > component counter_4 mapped to black box > > my project nane is itu656_dec : a decoder for itu 656 video > The following code has been used in my project: > > component counter_11 > port ( > Q: OUT std_logic_VECTOR(10 downto 0); > CLK: IN std_logic; > CE: IN std_logic; > ACLR: IN std_logic); > end component; > > component counter_4 > port ( > Q: OUT std_logic_VECTOR(3 downto 0); > CLK: IN std_logic; > CE: IN std_logic; > ACLR: IN std_logic); > end component; > > Can anybody help me? Give me some suggestion to deal with this kind of > warning. > You'd better send me some document of how to using xilinx ip core and hwo > to synthesize it with synplify. > Thank's a lot!!! > willie CHEN >Article: 79848
Andr閟 wrote:
> Hello newsgroup people,
>
> I am facing some problems when having the following pin declarations in
> my VHDL top level file.
>
> (ispLEVER version 4.2)
> (device LFEC20E-5F672CES)
>
> ATTRIBUTE PINL : STRING;
> ATTRIBUTE PINL OF Rst : SIGNAL IS "V25";
> ATTRIBUTE PINL OF Clk_board : SIGNAL IS "V20";
> ATTRIBUTE PINL OF Sdram_clk_out_p : SIGNAL IS "A15";
> ATTRIBUTE PINL OF Sdram_clk_out_n : SIGNAL IS "B15";
> ATTRIBUTE PINL OF Sdram_cke : SIGNAL IS "E17, B17";
> ATTRIBUTE PINL OF Sdram_csn : SIGNAL IS "A24, A23";
> ATTRIBUTE PINL OF Sdram_wen : SIGNAL IS "B22";
> ATTRIBUTE PINL OF Sdram_casn : SIGNAL IS "A22";
> ATTRIBUTE PINL OF Sdram_rasn : SIGNAL IS "A21";
> ATTRIBUTE PINL OF Sdram_addr : SIGNAL IS "D19, A18, E20, E18, B18,
> F18, D18, F19, C18, G18, A19, G19, B19";
> ATTRIBUTE PINL OF Sdram_ba : SIGNAL IS "B20, B21";
> ATTRIBUTE PINL OF Sdram_dqm : SIGNAL IS "E16, F15";
> ATTRIBUTE PINL OF Sdram_dqs : SIGNAL IS "A20, G15";
> ATTRIBUTE PINL OF Sdram_dq : SIGNAL IS "C17, D17, C16, D16, F17,
> G17, F16, G16, C15, B16, C14, E14, D15, E15, F14, G14";
>
> When compiling I get the following warning message:
> >Warning, attribute PINL given large bit vector width, potentially
> >unacceptable by place and route tools. Consider a string attribute
> >instead
>
> Unfortunately I cannot find any answer in the HELP menu.
>
> Has someone of you faced a similar problem ?
>
> Thank you in advance.
>
> Rgds
Hi Andre,
I used the following syntax with the standard development board without
any problems once I had upgraded to SP1.
entity Flashing_LED is
port(Sys_Clk : in Std_Logic;
Rst : in Std_Logic;
D1,D2: out Std_Logic;
D3,D4: out Std_Logic;
D5,D6: out Std_Logic;
D7,D8: out Std_Logic);
attribute LOC : string; -- PIN Assignment String
attribute LOC of D1 : signal is "G1";
attribute LOC of D2 : signal is "G2";
attribute LOC of D3 : signal is "H1";
attribute LOC of D4 : signal is "H2";
attribute LOC of D5 : signal is "K1";
attribute LOC of D6 : signal is "K2";
attribute LOC of D7 : signal is "J1";
attribute LOC of D8 : signal is "J2";
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
attribute LOC of Sys_Clk : signal is "V1"; -- Global Clock
-----------------------------------------------------------------------------
-- The Reset button is definetly @A19
-----------------------------------------------------------------------------
attribute LOC of Rst : signal is "A19"; -- System Reset
end Flashing_LED;
The only potential problem occurs when you try and use the Pre-Map
Preference Editor at the same time.
I hope this helps
Regards
Ben
Article: 79849Greetings! After taking an interesting course that partly involved using FPGAs I decided to buy a development board to continue tinkering around with them on my own. I've singled out the Digilent "D2SB" product with the "DIO4" daughterboard, but I'm wondering if anyone here can share their experience with this particular board (is it reliable?) or this manufacturer in general (are they reputable?). Is there another board I should be looking at? I was attracted to the D2SB due to the price and the wide range of addons available. The board is available at http://www.digilentinc.com My apologies if this is off-topic. Please ignore this post if so. -FM
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