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Hi FYI
I found this on the web and it is the same part that I use when I do
this with hardware.
However like the real part there is no reset. Do you think that the
lack of reset condition will cause problems other than simulation with
an unknown initial condition on the serial output pin?
As for the use it is to impliment a simple SPI output of a 16 bit
counter that I had sent to a seven segment decoder than an lcd but now
want to transfer into my PC.
Thanks
--
-- ls165.vhd
--
-- Description: This is a VHDL synthesizable description of the
74LS165
-- 8-Bit Parallel-to-Serial Shift Register.
--
--
-- Author: Wilson Li
-- Date: March 27, 1997
--
--
library ieee;
use ieee.std_logic_1164.all;
entity ls165 is
port(
p: in std_logic_vector(7 downto 0);
pl: in std_logic;
ds: in std_logic;
cp1: in std_logic;
cp2: in std_logic;
q7: out std_logic;
q7_bar: out std_logic
);
end ls165;
architecture ls165_body of ls165 is
signal q_buf: std_logic_vector(7 downto 0);
signal gated_clk: std_logic;
begin
q7 <= q_buf(7);
q7_bar <= not q_buf(7);
gated_clk <= cp1 or cp2;
process(gated_clk)
begin
if gated_clk'event and gated_clk = '1' then
if pl = '0' then
q_buf <= p;
else
-- shift by 1 bit
--
q_buf(0) <= ds;
q_buf(1) <= q_buf(0);
q_buf(2) <= q_buf(1);
q_buf(3) <= q_buf(2);
q_buf(4) <= q_buf(3);
q_buf(5) <= q_buf(4);
q_buf(6) <= q_buf(5);
q_buf(7) <= q_buf(6);
end if;
end if;
end process;
end ls165_body;
On Fri, 18 Feb 2005 07:57:10 -0500, bob <kmart@nospam.com> wrote:
>Shift register example?
>Hi I am looking for a parallel in serial out latching shift register
>in VHDL.
>I want 16 bits but any example would be appreciated.
>
>Thanks
Article: 79601
"Erik Widding" <widding@birger.com> schrieb im Newsbeitrag
news:1109017970.523487.109230@l41g2000cwc.googlegroups.com...
> > 1) for EDK the _I _O _T useage is required to be "EDK compliant" -
> this
> > issue has nothing todo with XST inout handling
>
> Actually EDK can handle tristate buffers declared inside of a pcore.
> The syntax for the MPD is as follows:
>
> PORT AD = "" , DIR=inout, VEC=[31:0], 3STATE=FALSE,
> IOB_STATE=BUF
>
> This exists because some IP is very tightly bound to its IO pin type,
> such as PCI or DDR SDRAM. We requested this feature from Xilinx a few
> years ago specifically so that we could use the PCI logicore netlist
> inside of a wrapper in EDK, without hand editing the top level VHDL.
>
>
> Regards,
> Erik.
Hi Erik,
YES and NO.
EDK can work as described, YES.
but the IO buffers are NOT inside the PCI logicore netlist!
----------------------------------------------------------------------------
------------------
XPCI_ADB0 : IOBUF_PCI33_3 port map
( O => AD_I0 , IO => AD_IO( 0), I => AD_O0 , T =>
_ADO_B );
----------------------------------------------------------------------------
------------------
PCI IO buffers for Xilinx OPB PCI core are instantiated in the VHDL code
as can be seen above and NOT inside the PCI logicore netlist!
and as of DDR SDRAM core there the _I _O _T is used as normal
DDR_DQ_o => DDR_DQ_o ,
DDR_DQ_i => DDR_DQ_i ,
DDR_DQ_t => DDR_DQ_t ,
Antti
Article: 79602Antti Lukats wrote: > Hi > > finally I can announce it: > > http://www.eubus.net/hydraXC > > Reconfigurable "dream" - small and fully reconfigurable computing module. Does the IrDA optics HW support FIR ( 4Mb/s) and VFIR (16 Mb/s) ? ( and/or Remote control ? ) Been interested in testing VFIR, but as yet, not much in the HW support, but the newest optics do. -jgArticle: 79603
Antti Lukats wrote: > Hi > > finally I can announce it: > > http://www.eubus.net/hydraXC Small oops - I see the Web table excludes USB-480Mb on the Model 10, but the PDF info includes that ? Which is correct ? -jgArticle: 79604
A quick question, based on one of yesterday's threads on DCM jitter - Does static timing analysis (timingan) factor in DCM jitter? The Xilinx timing analyser help states under 'Guaranteed Setup and hold requirements' that 'Timing will not include ....., and jitter into guaranteed setup and hold requirements', but it also states elsewhere that clock uncertainty is calculated from INPUT_JITTER and SYSTEM_JITTER - I couldn't seem to find the clock uncertainty figure in my timing report. So far, I've treated the timing analyser as a 'golden checker' for my timing requirements - should I then be factoring in, say 200ps of jitter in synth, p&r and timing analysis? I'm running at 100MHz in a Spartan-3. I'd also be interested in any other fine details of doing these analyses that you folks have to offer - in some of these cases, the devil seems to be in the details :) I'm semi-sure that I've read something somewhere (I couldn't relocate it) about leaving a certain amount of the timing budget left over - ie if you are 1 ps within budget, then you cannot strictly guarantee that the device will work as expected, but I couldn't find any recommendation of this sort in the Timing Closure TechXclusive. Thanks, JeremyArticle: 79605
I've noticed that "Timing Uncertainty" is only shown for paths that are printed in the error or verbose timing reports. You won't see a global figure for each constraint. A snippet: Timing constraint: COMP "mv_ld_shft_l" OFFSET = OUT 8 nS AFTER COMP "fpga_sysclk" ; 1 item analyzed, 1 timing error detected. Minimum allowable offset is 8.270ns. -------------------------------------------------------------------------------- Slack: -0.270ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: u_mv40_control_readout (FF) Destination: mv_ld_shft_l (PAD) Source Clock: fpga_sysclkb rising at 0.000ns Requirement: 8.000ns Data Path Delay: 8.227ns (Levels of Logic = 1) Clock Path Delay: 0.043ns (Levels of Logic = 3) Clock Uncertainty: 0.000ns Note that the uncertainty is 0.000 If you want to see the figure used, select the verbose report style with at least one path per constraint. Jeremy Stringer wrote: > A quick question, based on one of yesterday's threads on DCM jitter - > > Does static timing analysis (timingan) factor in DCM jitter? > > The Xilinx timing analyser help states under 'Guaranteed Setup and hold > requirements' that 'Timing will not include ....., and jitter into > guaranteed setup and hold requirements', but it also states elsewhere > that clock uncertainty is calculated from INPUT_JITTER and SYSTEM_JITTER > - I couldn't seem to find the clock uncertainty figure in my timing report. > > So far, I've treated the timing analyser as a 'golden checker' for my > timing requirements - should I then be factoring in, say 200ps of jitter > in synth, p&r and timing analysis? I'm running at 100MHz in a Spartan-3. > > I'd also be interested in any other fine details of doing these analyses > that you folks have to offer - in some of these cases, the devil seems > to be in the details :) I'm semi-sure that I've read something > somewhere (I couldn't relocate it) about leaving a certain amount of the > timing budget left over - ie if you are 1 ps within budget, then you > cannot strictly guarantee that the device will work as expected, but I > couldn't find any recommendation of this sort in the Timing Closure > TechXclusive. > > Thanks, > Jeremy -- Q: What is the most annoying thing on usenet and in e-mail? A: Bottom-posting. Q: Why is Bottom-posting such a bad thing? Read the rest of this message... (30 more lines)Article: 79606
> VHDL level simulation of JOP is now available ;-) > > The actual version of JOP at the usual download page > http://www.jopdesign.com/download.jsp > now contains (hopefully) all necessary file to run a > simulation with ModelSim or a different VHDL > simulator. > > A (very) simple step-by-step introduction can be found at: > http://www.jopdesign.com/simulation.jsp > I've added a simulation version of the uart module (sim_uart.vhd) to speed-up the simulation a little bit. It's too monotonous to watch the simulation generating the output at 115kbaud ;-) MartinArticle: 79607
Christian Schneider wrote: >> Also for reset what is the best synchronous or asynchronous?? because >> synchronous reset seems to need less ressource?? > > I have read a lot about resets in this newsgroup and I really do not > understand why so few people use the "reset on configuration": When > you download the bitstream everything has its default, so what else > do you want? You can just program it as asynchronous reset and the > tools do the rest (nearly). The reset on configuration is not guaranteed to be fast enough (in all chips) to bring everything out of reset at the same time. This can cause problems if your code expects this. Xilinx specifically recommends that you not use GSR in the Virtex, at least, because of the amount of skew. In addition - I'm not clear whether asynch. resets are covered by timing analysis. If it's not, then that leads to the same problem. Somebody else might be better equipped to comment on this. JeremyArticle: 79608
For reset as Chris says if there is no reset you will have problem for simulate There is some problems in the code there is no counter to control the load of the data so you must take care when p is set to 1 (this is the condition for load ) and when the data will have been sent you will send ds signal so be sure of what you wanna sent after your data word and finnally preferably than writing > q_buf(0) <= ds; > q_buf(1) <= q_buf(0); > q_buf(2) <= q_buf(1); > q_buf(3) <= q_buf(2); > q_buf(4) <= q_buf(3); > q_buf(5) <= q_buf(4); > q_buf(6) <= q_buf(5); > q_buf(7) <= q_buf(6); you could write q_buff <= q_buff(6 downto 0 )& ds; that a little bit faster to write ;) Regards alexis "bob" <kmart@nospam.com> a écrit dans le message de news: jjhk119tkkb1vmhv13jeevr5ctup00djs3@4ax.com... > Hi FYI > I found this on the web and it is the same part that I use when I do > this with hardware. > However like the real part there is no reset. Do you think that the > lack of reset condition will cause problems other than simulation with > an unknown initial condition on the serial output pin? > As for the use it is to impliment a simple SPI output of a 16 bit > counter that I had sent to a seven segment decoder than an lcd but now > want to transfer into my PC. > Thanks > > -- > -- ls165.vhd > -- > -- Description: This is a VHDL synthesizable description of the > 74LS165 > -- 8-Bit Parallel-to-Serial Shift Register. > -- > -- > -- Author: Wilson Li > -- Date: March 27, 1997 > -- > -- > > library ieee; > use ieee.std_logic_1164.all; > > > entity ls165 is > port( > p: in std_logic_vector(7 downto 0); > pl: in std_logic; > ds: in std_logic; > cp1: in std_logic; > cp2: in std_logic; > q7: out std_logic; > q7_bar: out std_logic > ); > end ls165; > > > architecture ls165_body of ls165 is > > signal q_buf: std_logic_vector(7 downto 0); > signal gated_clk: std_logic; > > begin > > q7 <= q_buf(7); > q7_bar <= not q_buf(7); > gated_clk <= cp1 or cp2; > > process(gated_clk) > > begin > > if gated_clk'event and gated_clk = '1' then > > if pl = '0' then > > q_buf <= p; > > else > > -- shift by 1 bit > -- > q_buf(0) <= ds; > q_buf(1) <= q_buf(0); > q_buf(2) <= q_buf(1); > q_buf(3) <= q_buf(2); > q_buf(4) <= q_buf(3); > q_buf(5) <= q_buf(4); > q_buf(6) <= q_buf(5); > q_buf(7) <= q_buf(6); > > end if; > > end if; > > end process; > > end ls165_body; > > > > > On Fri, 18 Feb 2005 07:57:10 -0500, bob <kmart@nospam.com> wrote: > >>Shift register example? >>Hi I am looking for a parallel in serial out latching shift register >>in VHDL. >>I want 16 bits but any example would be appreciated. >> >>Thanks >Article: 79609
>> So where are the prices ? I've found EUR 295,- for a S3-1000 populated board at the hydraXC shop (but it's in german - easy for me ;-) >> >> Seems this would have a range of prices, as the FPGA changes, >> so the smallest one would suit JOP ? > 1808 LCs, 47% of the S3-200, as ported to the S3 Starter Kit ;-) For Antti's board we would need a few LCs more for the SDRAM controller. BTW: Are there SDRAM, USB and Ethernet controller (in VHDL) available for your board? > At boot the FPGA is loaded either from onboard flash or > from miniSD, after the configuration FPGA has full access > to all connected peripherals and resources, ie can continue > boot by loading OS image from onchip flash or from miniSD > card, after OS comes alive it can load secondary hardware > and probably second OS over LAN, then request reboot > from system management controller. > if the second configuration should be faulty the system > management controller restores known good configuration As, I'm also considering an SD card for the FPGA configuration and user data I'm very interested in your solution. How do you manage the fall back configuration? All this is done in a CPLD? You're doing a minimal FAT in the CPLD? MartinArticle: 79610
> I have read a lot about resets in this newsgroup and I really do not > understand why so few people use the "reset on configuration": When > you download the bitstream everything has its default, so what else > do you want? You can just program it as asynchronous reset and the > tools do the rest (nearly). > So if i use asynchronous reset, all internal signal will be set at the reset value at the startup of the fpga?? > A shift register would have been much faster, and uses much less logic > resources. I have check , and I have nothing else to add that you are right, little padawan have a lot to learn^^ I have dl the xilinx synthesis design guide, now let's read it (400p ->thales's guide was smaller... : ~ ) > Yes you are right, the task is not completely mentioned. > I just wanted to correct the source code, sorry for the harsh tone. > > No problem for the "the harsh tone", I just have some problem with critics even more actually because I'm tired of those french firm that take no risk with young graduates like me and prefer older engineer without skill. :# Regards AlexisArticle: 79611
"Antti Lukats" <antti@openchip.org> writes: > finally I can announce it: > http://www.eubus.net/hydraXC Looks nice. Is there a pricing and availability page in English? Thanks, EricArticle: 79612
OK, found it. Thank you :) Now to start plugging in figures... Jeremy Gabor wrote: > I've noticed that "Timing Uncertainty" is only shown for > paths that are printed in the error or verbose timing reports. > You won't see a global figure for each constraint. > > A snippet: > > [SNIP] > > Note that the uncertainty is 0.000Article: 79613
M.Randelzhofer wrote: > > The compiler producing 'wrong code' isnt effected by how much logic > > optimisation is performed I suggest you look elsewhere for the cause of > > your problems. > > > > Maybe i'm dreaming... > > This is the VHDL code with the interesting 4bit counter ptc: > > if (prc = 7) then > hf2 <= '0' ; > keyf2 <= '0' ; > ptc <= (others => '0') ; > if (ps2c_f = '1') then -- init hf2 during startbit > hf2 <= '1' ; > end if ; > else > if (ps2c_f = '1') then > ptc <= ptc + 1 ; > case ptc is > when "0001" | "0010" => > if (sdat = '0') then > hf2 <= '0' ; > end if ; > when "0000" | "0011" | "0100" | "0101" | "0110" | "0111" => > if (sdat = '1') then > hf2 <= '0' ; > end if ; > when "1000" => > keyf2 <= hf2 ; > when others => > end case ; > end if ; > end if ; > > This translation is ok with not setting the wysiwyg flag: > FDCPE_ptc0 behaves exactly how it should. > > FDCPE_ps2c_f: FDCPE port map (ps2c_f,ps2c_f_D,bsysclk,'0','0'); > ps2c_f_D <= (NOT ed_ps2(0) AND ed_ps2(1)); > > FDCPE_ptc0: FDCPE port map (ptc(0),ptc_D(0),bsysclk,'0','0'); > ptc_D(0) <= ((ptc(0) AND ps2c_f) > OR (NOT ptc(0) AND NOT ps2c_f) > OR (prc(0) AND prc(1) AND prc(2))); > > FDCPE_ptc1: FDCPE port map (ptc(1),ptc_D(1),bsysclk,'0','0'); > ptc_D(1) <= ((NOT ptc(0) AND NOT ptc(1)) > OR (NOT ptc(1) AND NOT ps2c_f) > OR (ptc(0) AND ptc(1) AND ps2c_f) > OR (prc(0) AND prc(1) AND prc(2))); > > FTCPE_ptc2: FTCPE port map (ptc(2),ptc_T(2),bsysclk,'0','0'); > ptc_T(2) <= ((ptc(0) AND ptc(1) AND NOT prc(0) AND ps2c_f) > OR (ptc(0) AND ptc(1) AND NOT prc(1) AND ps2c_f) > OR (ptc(0) AND ptc(1) AND NOT prc(2) AND ps2c_f) > OR (ptc(2) AND prc(0) AND prc(1) AND prc(2))); > > FTCPE_ptc3: FTCPE port map (ptc(3),ptc_T(3),bsysclk,'0','0'); > ptc_T(3) <= ((prc(0) AND prc(1) AND ptc(3) AND prc(2)) > OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(0) AND ps2c_f) > OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(1) AND ps2c_f) > OR (ptc(0) AND ptc(1) AND ptc(2) AND NOT prc(2) AND ps2c_f)); > > > This output is wrong, with the wysiwyg flag enabled: > The FTCPE_ptc0 flipflop has a completely unrelated signal on it. > > FDCPE_ps2c_f: FDCPE port map (ps2c_f,ps2c_f_D,bsysclk,'0','0'); > ps2c_f_D <= (NOT ed_ps2(0) AND ed_ps2(1)); > > FTCPE_ptc0: FTCPE port map (ptc(0),iff1(4).EXP,bsysclk,'0','0'); It's kind of hard to tell. I assume the unrelated signal you are talking about is iff1(4).EXP. I do not see it in the exerpt, but it might be an intermediate term that is generated in another macro-cell that is a function of the HDL. Did you do a functional simulation of the logic? Does the post synthesis design simulate as expected for both the wysiwyg and non wysiwyg. Are there any synthesis warnings concerning latches. Transparent latches are usually undesirable. Are you getting logic failures in hardware that could be speed related, cause I would guess that the wysiwyg could possible be slower. Good-luck -Newman > > FDCPE_ptc1: FDCPE port map (ptc(1),ptc_D(1),bsysclk,'0','0'); > ptc_D(1) <= ((NOT ptc(1) AND NOT ptc(0)) > OR (NOT ptc(1) AND NOT ps2c_f) > OR (ptc(1) AND ptc(0) AND ps2c_f) > OR (prc(2) AND prc(1) AND prc(0))); > > FTCPE_ptc2: FTCPE port map (ptc(2),ptc_T(2),bsysclk,'0','0'); > ptc_T(2) <= ((ptc(2) AND prc(2) AND prc(1) AND prc(0)) > OR (ptc(1) AND NOT prc(2) AND ptc(0) AND ps2c_f) > OR (ptc(1) AND ptc(0) AND NOT prc(1) AND ps2c_f) > OR (ptc(1) AND ptc(0) AND NOT prc(0) AND ps2c_f)); > > FTCPE_ptc3: FTCPE port map (ptc(3),ptc_T(3),bsysclk,'0','0'); > ptc_T(3) <= ((ptc(3) AND prc(2) AND prc(1) AND prc(0)) > OR (ptc(2) AND ptc(1) AND NOT prc(2) AND ptc(0) AND ps2c_f) > OR (ptc(2) AND ptc(1) AND ptc(0) AND NOT prc(1) AND ps2c_f) > OR (ptc(2) AND ptc(1) AND ptc(0) AND NOT prc(0) AND ps2c_f)); > > Any hints ? > > MIKEArticle: 79614
I just bought a Spartan-3 Starter Kit along with the CoolRunner Design Kit for $100US. Go to the Xilinx web site and look under Dev boards. Pretty good deal. Madhu ec wrote: > Hi all > > My name is Eliahu from Israel . > > After some years in the software field I want to > come back again to the harware era . > > I want to start again doing FPGA designs . > I feel that XILINX "speaks" to me . > > My question is : What low cost deseign kit might be right for > a "comeback" to the fpga filed ? > > Any ideas ? > > Thanks in advance > EC > > > > > > >Article: 79615
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:421a51aa$1@clear.net.nz... > Antti Lukats wrote: > > > Hi > > > > finally I can announce it: > > > > http://www.eubus.net/hydraXC > > Small oops - I see the Web table excludes USB-480Mb on the Model 10, but > the PDF info includes that ? Which is correct ? > > -jg > S3-1000 fitted module includes USB AnttiArticle: 79616
What is available in india? I would like to try out some design.. AnkurArticle: 79617
Ankur, I assume that you would be able to order one from the Xilinx Online store. I don't know if the procedure is different if one is overseas, never had the opportunity. You said you would like to try out some design. Is it OK to ask if you are an engineer or hobbiest, and what kind of work you do? I've heard people ask what it is like to work in San Jose, California USA, but I never heard of anyone saying what it is like to work in India. Regards, -Newman Link to store : http://www.xilinx.com/xlnx/xebiz/categoryview.jsp?sGlobalNavPick=PURCHASE&sSecondaryNavPick=&category=-1210687&iLanguageID=1&category=/Xilinx+Products/Design+Resources/Design+Starter+Kits -Newman <akuchlous@gmail.com> wrote in message news:1109053960.103574.72310@z14g2000cwz.googlegroups.com... > What is available in india? > > I would like to try out some design.. > > Ankur >Article: 79618
Hi I work for a EDA company, working on FPGA synthesis tool. Two fpga tool lead in market. One is our company( to keep company name out), and other is from synplicity. An under-grad approached me for help in getting his design into an FPGA, and verify it. So I thought it would be a good exercise for me to do some pure design stuff and verify it. As for work, I am satisfied out here, for I get to do the best stuff in EDA, and given the opportunity and salary out here, it was a wise decision to move back to India. -Ankur mail me at gmail.com@akuchlous, if u have any more questions. (reverse the email id).Article: 79619
Hi all, I have a signal algorithm implementation design on FPGA. I simulated the design in Modelsim and now I want to export the output values and compare with those of the Matlab. Can somebody suggest me how to do that? I read the input values of my testbench from the same input file which I use for Matlab input. I tried using VIEW --> LIST and then dragging the signals I want to the LIST window but that doesnt seem to be solving the problem. It creates duplicate input values too whenever the "DELTA" value is high. I dont understand whats DELTA in the LIST window? I would appreciate if somebody could comment on this??? Thanks in advance. SDArticle: 79620
Hi there, I plan to use a limited number of Spartan3 FPGA's. The various voltages/ramping/currents required by my circuitry seem to be perfectly covered by the TI TPS75003RHLR chip with adequate periphery. My current project needs around 5 samples for end of march 2005. The TI Web site says "status PREVIEW". I am also getting in touch with various distributors of the chip to get the availability information. Has anyone heard about the current development and sampling status of that chip? Does anyone know about viable alternatives (Linear Technology for instance). Thanks.Article: 79621
I'm trying to build a simple core in which decode and register file access occurs in the same cycle on a virtex II pro board. Decode completes in the half clock cycle after the positive edge. Any ideas about how to make a dual ported RAM which operates in the half cycle after the negative edge? Thanks in advanceArticle: 79622
Hello Guys, I am interfacing the synopsys USB 1.1 core with the PHY. But the problem is the USB core side transreciever signal doesnot match the PHY signal. As any one interface USB core to PHY?. If so can you please provide more information about it. Is USB 1.1 also having UTMI interface to PHY? I searched the internet but could not get the information. Thanks and regards WilliamsArticle: 79623
On Mon, 21 Feb 2005 17:30:42 +0100, "IgI" <igorsath@hotmail.com> wrote: >> Have you re-run timing analysis on the 5.3 design, but using the latest >> timing analyser and latest speed files? > >No, because I don't think there's any timing issue here. The logic is >trivial and runs at low speed. Maybe not, unless there are hold time or skew issues, not properly covered by older speed files. I would try the newer speed files on the "suspect" design just to check. >> With 6.1, have you tried MPPR (multi-pass pacement and routing)? >> Sometimes modifying the placement (in FPGA editor) of failing paths and >> re-running "re-entrant routing" can fix problems, if there are only a >> small number of failing paths. > >Yes, I have. I tried 6.1, 6.2 and 6.3. It's always the same story. >Placer/Router does a lousy job. Either the constraints can't be met or the >router can't connect all the nets. ISE 5.2 SP3 completes without any errors >and reports 7 logic levels for the constraint. On the other hand ISE 6.x >reports 16 logic levels for the same constraint. That can be illusory, if 9+ of those 16 levels are carry logic. It may reflect relatively small differences in placement or routing getting on/off the carry chain. But I have found (a) a LUT connected to a long carry chain but placed on the other side of the chip ... and (with a heavily floorplanned design, where the placer can't do that) (b) a signal taking 3ns to get from one CLB to its immediate neighbour. The former (if an isolated incident) can be fixed in FPGA editor, the latter either reflects severe congestion (whatever happened to "view/congestion map" in the floorplanner?) or a very lazy router. >In my experience (for the Virtex-II family) if the design takes less than >~90% of chip resources then the results of ISE 6.x are similar to the ISE >5.2 SP3, sometimes even better, but as soon as design takes more than 95% of >all chip resources then ISE 6.x gives up. Similarly I still use ISE 3.3 for >SpartanXL and Spartan2 designs, because ISE 4.2 or newer don't produce the >desired results. I know a lot depends on the synthesis tool (I'm using >synplicity)... Interesting. I didn't know that about the 5.x-6.x problems, but Ray Andraka has commented on the relative performance of 3.3 vs later in the past. (Google may help a little) I'm still using 3.3 in "production"! My experience so far with 6.x (Webpack) is that it will never meet reasonable constraints, but radically overconstraining it will improve results. For example, if I want 10 ns, and ask for it, I get 10.5 ns. But if I ask for 9 ns I get 9.8, (or 10.1) and if I ask for 8 ns I get 9.5 ns... I just made up those numbers but they represent the trend I've seen. If the resulting design passes timing analysis at 10.0 ns, I can't see any reason not to use it... >Thanks for you suggestions, >Igor Bizjak Thanks. I've not pushed such high resource usages, so it's interesting to hear tales from people pushing the chips hard in other respects. - BrianArticle: 79624
Hello newsgroup people, I am facing some problems when having the following pin declarations in my VHDL top level file. (ispLEVER version 4.2) (device LFEC20E-5F672CES) ATTRIBUTE PINL : STRING; ATTRIBUTE PINL OF Rst : SIGNAL IS "V25"; ATTRIBUTE PINL OF Clk_board : SIGNAL IS "V20"; ATTRIBUTE PINL OF Sdram_clk_out_p : SIGNAL IS "A15"; ATTRIBUTE PINL OF Sdram_clk_out_n : SIGNAL IS "B15"; ATTRIBUTE PINL OF Sdram_cke : SIGNAL IS "E17, B17"; ATTRIBUTE PINL OF Sdram_csn : SIGNAL IS "A24, A23"; ATTRIBUTE PINL OF Sdram_wen : SIGNAL IS "B22"; ATTRIBUTE PINL OF Sdram_casn : SIGNAL IS "A22"; ATTRIBUTE PINL OF Sdram_rasn : SIGNAL IS "A21"; ATTRIBUTE PINL OF Sdram_addr : SIGNAL IS "D19, A18, E20, E18, B18, F18, D18, F19, C18, G18, A19, G19, B19"; ATTRIBUTE PINL OF Sdram_ba : SIGNAL IS "B20, B21"; ATTRIBUTE PINL OF Sdram_dqm : SIGNAL IS "E16, F15"; ATTRIBUTE PINL OF Sdram_dqs : SIGNAL IS "A20, G15"; ATTRIBUTE PINL OF Sdram_dq : SIGNAL IS "C17, D17, C16, D16, F17, G17, F16, G16, C15, B16, C14, E14, D15, E15, F14, G14"; When compiling I get the following warning message: >Warning, attribute PINL given large bit vector width, potentially >unacceptable by place and route tools. Consider a string attribute >instead Unfortunately I cannot find any answer in the HELP menu. Has someone of you faced a similar problem ? Thank you in advance. Rgds
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