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Messages from 79875

Article: 79875
Subject: Re: Synthesis question
From: "Vladislav Muravin" <xfilex2003@hotmail.com>
Date: Fri, 25 Feb 2005 10:38:22 -0500
Links: << >>  << T >>  << A >>
if you have a combinational process like:

always @(state or [some control inputs] )
    begin
        case (state)
            state1 : state = blablabla;
        endcase
    end

the synthesis tool will never extract a register
you should sample the state in a separate process.
post a part of your code, this would be more clear.

Vladislav

"kowari" <kellie_marks@hotmail.com> wrote in message
news:1109286743.700106.182340@l41g2000cwc.googlegroups.com...
> Hi everyone,
>
> I have a state machine which creates the following INFO when
> synthesised using Xilinx ISE6.1.
>
> INFO:Xst:1813 - Unable to extract FSM on signal <state> : outputs
> depend on both state and next state.
>
> Is this something I should be concerned about?
>
> THanks
>



Article: 79876
Subject: Re: Prescalable counter
From: "Vladislav Muravin" <xfilex2003@hotmail.com>
Date: Fri, 25 Feb 2005 10:41:21 -0500
Links: << >>  << T >>  << A >>
what is this counter for?


"Preben Holm" <64bitNOnoSPAMno@mailme.dk> wrote in message
news:421deb0f$0$29285$14726298@news.sunsite.dk...
> Hi everyone..
>
> I wonder how to build a prescaled counter! That is a counter that can be
> prescaled by fx. a factor 1.000.000 or less!
>
> Any nice ideas how to do this?
>
>
> Thanks
> Preben



Article: 79877
Subject: Re: Virtex4 : speed improvement
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 25 Feb 2005 07:46:03 -0800
Links: << >>  << T >>  << A >>
steven wrote:
> Xilinx V4 doc says one can expect 40% speed improvement over previous generation (and nearest competing FPGA as well? ;-))
> 
> Ok, but what kind of improvement may I get when upgrading from a V2Pro-7 to a V4-10? and what about -11 or latest -12 speed grades? any figure?


Steven,

Are you planning to use any of the new features, or re-targeting anything?

If so, there will be speed improvements.

If you just take the V2P design in -7 (fastest speed grade) and retarget 
for V4-10 (slowest speed grade), you may come out on par.

But, the ISE software also has improvements, so a design done a year ago 
will be able to run faster if re-run today, just from improvements in 
the tools.

Comparing the fastest speed grade of the previous product, to the 
slowest speed grade of the new product is likely to not show much of an 
improvement.  Especially since the variation in speed as we shrink gets 
wider (speed grades offer more improvement).

Austin

Article: 79878
Subject: Re: Quartus DESIGN ASSISTANT tool
From: "Vladislav Muravin" <xfilex2003@hotmail.com>
Date: Fri, 25 Feb 2005 10:46:33 -0500
Links: << >>  << T >>  << A >>
yes, this is what design assistant suggests.
but the reset doesn't necessary need to be synchronized, if it is long
enough

Vladislav


"Andrés" <nospam_nussspucke@gmx.de> wrote in message
news:385j0dF5ip30tU1@individual.net...
> Vladislav Muravin wrote:
> > Andres,
> >
> > I am not an Altera guy, but i think that the safe reset implies that the
> > very first flip-flop in a chain has to be reset
> > to a certain default value, not to the value generated by the internal
> > logic.
> >
> > Imagine that you have a state machine implemented with a certain
encoding
> > for each state.
> > If the reset is applied asynchronously, then your state register shall
be
> > resetted, but some of the flipflops can start "moving" before others are
get
> > out of reset. Consequently, your state machine could get into an
undesirable
> > state.
> >
> > So, Altera design assistant advises you to have something like this
(hope
> > the code is right, I am not VHDL guy as well):
> >
> > process (clk,Areset_n)
> > begin
> >     if (Areset_n)
> >         Areset_n_d <= "0";
> >         Areset_n_sync <= "0";
> >     elsif rising_edge(clk)
> >         Areset_n_d <= "1";
> >         Areset_n_sync <= Areset_n_d;
> >     end if
> > end
> >
> >
> > Hope this helps.
> >
> > Vladislav
> >
>
> No, sorry.
> You misunderstood my question:
> The flip flop chain I use makes sure that the reset is applied
> synchronously to my logic that is also to all state machines.
>
> The question was if the flip flops of the synchronizer chain
> should be set by the asynchronous external reset or not.
>
> Thank you.
>
> Rgds
> Andrés



Article: 79879
Subject: Re: pld macrocell usage
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 25 Feb 2005 17:07:01 +0100
Links: << >>  << T >>  << A >>

"vax, 9000" <vax9000@gmail.com> schrieb im Newsbeitrag
news:cvlkvg$64i$1@charm.magnus.acs.ohio-state.edu...

> > me.  Why does it need a macrocell for the I/O.  I put the chip in low

> I read the XC9500 user manual and I think it is designed so that you need
> one macrocell for each output pin.

Exactly. With the coolrunners, there is an option to use IO and macrocell
independend, but I wouldnt base my design too much on it. Use a bigger CPLD
or FPGA.

Regards
Falk




Article: 79880
Subject: Re: Fast 28x28 multiplier + adder in Virtex4
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 25 Feb 2005 17:08:45 +0100
Links: << >>  << T >>  << A >>

> Right now I'm not using anything fancy. I created a 28x28 multiplier

Pipelining is the magic word (Coregen calls it registered inputs and
outputs)

Regards
Falk




Article: 79881
Subject: Re: IP unnecessarily using Spartan-3 DCM?
From: "Gabor" <gabor@alacron.com>
Date: 25 Feb 2005 08:14:40 -0800
Links: << >>  << T >>  << A >>
Richard Thompson wrote:
>
> In this case, there seems to be no point in having a 0-delay buffer.
> The only place that CLK1 is used is at the DCM's CLKIN pin, so the
> whole setup seems pointless to me.
>

First of all the point of a zero-delay buffer on a global input pin
is to synchronize to a clock off-die, not inside the chip.  If you
don't use the clock for any IOB's you don't need this zero-delay
buffer.

> There's a second issue here, which is that zeroing out a delay (if
> that was the IP vendor's intent) is dangerous anyway. The only place
> at which the delay is zeroed is at the DCM's inputs; it's not going
to
> be 'zero' anywhere else on the die.

If you believe in low-skew routing resources, then the delay should
also be zero every place you use CLK3, since this is one of the DCM
inputs.  The important place for this to be zero in this case is at
your IOB flip-flops, where it can reduce the set-up time to clock.

> 
> Rick


Article: 79882
Subject: Re: EC/ECP Map Problem
From: "Gabor" <gabor@alacron.com>
Date: 25 Feb 2005 08:23:54 -0800
Links: << >>  << T >>  << A >>
Andr=E9s wrote:
> Hi FPGA people,
>
> I am trying to map my VHDL design on a Lattice-EC FPGA.
(LFEC20E-5F672CES)
>
> The following error warning occurs:
>
> *********************************
> Map checkpoint failed.
> Design's logic delay (97 percent of total delay)
> exceeds the 60 percent limit set in the map checkpoint options
> *********************************
> Process Stopped.
>
> Done: failed with exit code: 0001.
>
>
> Unfortunately there is no direct "double click" HELP  for this error
> message and I could not find any hint in the HELP menu.
>
> Has someone of you any idea what this message could mean ?
>
>
> Thank you in advance.
>
> Rgds
> Andr=E9s

This would be a lot clearer if it named a particular path.  This is
like
the old Xilinx post-translate timing, where the place and route will
not
continue if it already knows it won't meet timing.  In the Lattice case
it seems that there is also a threshold of 60% of your constraint (in
Xilinx it was 100%).  i.e. if you gave a path 10ns and with logic only
(no routing) you've already used more than 6ns it gives the error.  The
"map checkpoint options" sounds like there is a way to control this
percentage.  All of this is speculation on my part since I don't have
the Lattice tools yet, but I know that there tools were developed by
some ex-Xilinx types...


Article: 79883
Subject: Can't create Bus-Tap in Xilinx' ECS
From: "Dipl.-Ing. Hanns-Walter Schulz" <ha.schulz@tu-bs.de>
Date: Fri, 25 Feb 2005 17:34:30 +0100
Links: << >>  << T >>  << A >>
Hello all,

quite embarassing question - but can't move on without the answer ...

I'm new to FPGA-programming and encountered the following problem:

suppose we have a symbol with an output pin: A(35:0)    [Multiplier]

we have another symbol with an input pin: B(15:0)   [Latch]

if I want to connect the two, for example A(15:0) and B(15:0), I have to 
extract A(15:0) from A(35:0)

HOW DO I DO THIS??

I tried to ues a bus tap, but it never worked. got the following error 
messages:
    "Error: Destination branch of bus tap at (1616 912 1712 912) is not part 
of the source branch of the bus tap"


it does work the other way around though, when I have a bus a(3:0) and add 4 
bus taps with a(0), a(1), a(2), and a(3).


I really need help.

Thanks you in advance,

Hanns-Walter




__________________________________________
Dipl.-Ing. Hanns-Walter Schulz
TU Braunschweig
Institut fuer Luft- und Raumfahrtsysteme
Institute of Aerospace Systems
Hermann-Blenk-Str. 23  Tel.: ++49 531 391 9968
D-38108 Braunschweig   Fax:  ++49 531 391 9966



Article: 79884
Subject: Re: NiosII Vs MicroBlaze
From: jon@beniston.com (Jon Beniston)
Date: 25 Feb 2005 08:37:54 -0800
Links: << >>  << T >>  << A >>
> > NIOS II comes with eclipse (an IDE), but you can download that
> > separatly for MicroBlaze anyway,
> 
> From press release:
> --------------------------------------------------------------------------
> The Platform Studio tool suite automates a host of architecture-level design 
> steps and offers a powerful new software environment based on the 
> industry-standard Eclipse integrated design environment (IDE). The Platform 
> Studio 6.3i release supports the Xilinx processor solutions, including the 
> MicroBlaze and immersed PowerPC cores.
> --------------------------------------------------------------------------
> What does the download of eclipse buy you?

I didn't realise they had included it with the EDK now. So nothing. 

Cheers,
Jon

Article: 79885
Subject: Virtex-4 performance, where is it?
From: "Antti Lukats" <antti@openchip.org>
Date: Fri, 25 Feb 2005 17:49:16 +0100
Links: << >>  << T >>  << A >>
Hi

there are lots of PR news about how much better, etc..

but doing a very simple task with V4 I was really surprised:

to test max clock for an XC9572XL-5 (cuctomer needs 125MHz)
I used V4 development board as programambel clock source.
100Mhz comes in, goes to DCM and goes out.
nothing else

with V4LX25-10 the maximum frequency that the DCM was possible to set was
168MHz!

changing the speed grade to -11 allowed to set fout to 180MHz,
but even that seems kind low for the performance leader ???

The DCM could generate a max freq of 315MHz, but that case the input
frequency
is required to be more than 120MHz, and my development board has only 100Mhz
oscillator useable :(
hopefully I am missing something and higher frequencies are actually
possible too.

ok this time the 180MHz was sufficient for our testing -

XC9572XL-10 (max freq in datasheet 125MHz) did work very well
until input freq 150Mz, with 180MHz the first flip started to divide by 3
surprisingly deliver very clean 60MHz clock.

Another "nice" thing the first XC95 PLD we used was not supported by
Impact 6.3 !!! Xilinx has silently dropped support of some PLDs from
latest ISE/impact - the XC9536 device was recognized as
XC9536_unsupported !! by impact and it did not program it.
funny is that the development board where this PLD was also
holds a large logo of Xilinx, ah well just another thing to know...

Antti



Article: 79886
Subject: Re: IP unnecessarily using Spartan-3 DCM?
From: Richard Thompson <nospam@nospam.com>
Date: Fri, 25 Feb 2005 16:49:19 +0000
Links: << >>  << T >>  << A >>
On Fri, 25 Feb 2005 07:37:44 -0800, Austin Lesea <austin@xilinx.com>
wrote:

>Rick,
>
>Oh, but it is.  The idea behind the feedback is to cause there to be a 
>known phase realtionship so one can do system synchronous IO.
>
>The timing is within the data sheet limits for the distribution over the 
>clock tree to the IOBs.

I'm not sure that I understand this - are you replying to

>> There's a second issue here, which is that zeroing out a delay (if
>> that was the IP vendor's intent) is dangerous anyway. The only place
>> at which the delay is zeroed is at the DCM's inputs; it's not going to
>> be 'zero' anywhere else on the die.

If CLK3 is heavily loaded, and CLK1 is not, then surely they will have
a (very) significant phase difference at the end of the die opposite
the DCM?

Rick


Article: 79887
Subject: Re: IP unnecessarily using Spartan-3 DCM?
From: "Peter Alfke" <peter@xilinx.com>
Date: 25 Feb 2005 09:00:38 -0800
Links: << >>  << T >>  << A >>
The DCM works as a "zero-delay" clock buffer under the following (and
valid) assumptions:
The Global Clock buffer has a substantial (multi-ns) delay, especially
on a large chip. This delay can be "eliminated" by introducing
additional DCM-internal clock delay (that's what the DCM does), so that
the delayed output clock edge coincided with the incoming clock edge.
There is no miraculous negative delay, but it behaves as if there were,
and it therefore works only on repetitive signals like clocks.
The other correct assumption is that Xilinx designers have done a good
job in balancing the clock tree, so that it has (almost) the same delay
wherever it arrives, within a few hundred picoseconds. Good enough that
there never is a hold time issue between two flip-flops with a common
global clock, no matter how that global clock is routed.
I agree that there is no need for a DCM in the situation mentioned in
the original posting.
Peter Alfke


Article: 79888
Subject: Re: Virtex-4 performance, where is it?
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 25 Feb 2005 17:31:39 GMT
Links: << >>  << T >>  << A >>
>From p 29 of the DS302 v1.4 Virtex 4 Data Sheet: DC and Switching
Characteristics, the output clocks from the DCM in the *high frequency mode*
shows 210-280 MHz capable FX outputs (for the slower -10 device) to pick up
where the *low frequency mode* drops off.  The input for the high frequency
mode can be as low as 50 MHz if the DFS mode is all that's used.

100 MHz in, 100*M/N out up to 280 MHz in the -10 device.
Check to make sure you're 1) working in HF mode and 2) you're not using the
standard outputs - just the DFS.


"Antti Lukats" <antti@openchip.org> wrote in message
news:cvnl3m$102$01$1@news.t-online.com...
> Hi
>
> there are lots of PR news about how much better, etc..
>
> but doing a very simple task with V4 I was really surprised:
>
> to test max clock for an XC9572XL-5 (cuctomer needs 125MHz)
> I used V4 development board as programambel clock source.
> 100Mhz comes in, goes to DCM and goes out.
> nothing else
>
> with V4LX25-10 the maximum frequency that the DCM was possible to set was
> 168MHz!
>
> changing the speed grade to -11 allowed to set fout to 180MHz,
> but even that seems kind low for the performance leader ???
>
> The DCM could generate a max freq of 315MHz, but that case the input
> frequency
> is required to be more than 120MHz, and my development board has only
100Mhz
> oscillator useable :(
> hopefully I am missing something and higher frequencies are actually
> possible too.
>
> ok this time the 180MHz was sufficient for our testing -
>
> XC9572XL-10 (max freq in datasheet 125MHz) did work very well
> until input freq 150Mz, with 180MHz the first flip started to divide by 3
> surprisingly deliver very clean 60MHz clock.
>
> Another "nice" thing the first XC95 PLD we used was not supported by
> Impact 6.3 !!! Xilinx has silently dropped support of some PLDs from
> latest ISE/impact - the XC9536 device was recognized as
> XC9536_unsupported !! by impact and it did not program it.
> funny is that the development board where this PLD was also
> holds a large logo of Xilinx, ah well just another thing to know...
>
> Antti
>
>



Article: 79889
Subject: Re: Can't create Bus-Tap in Xilinx' ECS
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 25 Feb 2005 17:34:18 GMT
Links: << >>  << T >>  << A >>
You may need to specify what schematic input tool you're using since so much
of the industry is coing HDL where all you would need to do is specify the
instance port as ".B(A[15:0])" within the device instantiation.

1) Tell the folks here what schematic tool you have,
2) Consider learning Verilog or VHDL


"Dipl.-Ing. Hanns-Walter Schulz" <ha.schulz@tu-bs.de> wrote in message
news:cvnk2l$qgv$1@rzcomm2.rz.tu-bs.de...
> Hello all,
>
> quite embarassing question - but can't move on without the answer ...
>
> I'm new to FPGA-programming and encountered the following problem:
>
> suppose we have a symbol with an output pin: A(35:0)    [Multiplier]
>
> we have another symbol with an input pin: B(15:0)   [Latch]
>
> if I want to connect the two, for example A(15:0) and B(15:0), I have to
> extract A(15:0) from A(35:0)
>
> HOW DO I DO THIS??
>
> I tried to ues a bus tap, but it never worked. got the following error
> messages:
>     "Error: Destination branch of bus tap at (1616 912 1712 912) is not
part
> of the source branch of the bus tap"
>
>
> it does work the other way around though, when I have a bus a(3:0) and add
4
> bus taps with a(0), a(1), a(2), and a(3).
>
>
> I really need help.
>
> Thanks you in advance,
>
> Hanns-Walter
>
>
>
>
> __________________________________________
> Dipl.-Ing. Hanns-Walter Schulz
> TU Braunschweig
> Institut fuer Luft- und Raumfahrtsysteme
> Institute of Aerospace Systems
> Hermann-Blenk-Str. 23  Tel.: ++49 531 391 9968
> D-38108 Braunschweig   Fax:  ++49 531 391 9966
>
>



Article: 79890
Subject: Re: IP unnecessarily using Spartan-3 DCM?
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 25 Feb 2005 09:34:35 -0800
Links: << >>  << T >>  << A >>
Rick,

You have my answer associated with the right question, yes.

Further, loading does not matter as we are fully buffered everywhere. 
Load as much as you like, delay does not change (on the BUFG)by more 
than a few tens of ps.

If it did, it would make a lot of designs very hard to do, and our 
performance would vary far too much from design to design, and we would 
have to "sand-bag" our speeds files.

P&R would be more difficult, and timing analysis would take far longer. 
  This was one of the "break-throughs" with the original Virtex:  fully 
buffered interconnect (patented) led to huge reductions in time in the 
front end software tools, as well as more predictable back-end performance.

Austin

Richard Thompson wrote:
> On Fri, 25 Feb 2005 07:37:44 -0800, Austin Lesea <austin@xilinx.com>
> wrote:
> 
> 
>>Rick,
>>
>>Oh, but it is.  The idea behind the feedback is to cause there to be a 
>>known phase realtionship so one can do system synchronous IO.
>>
>>The timing is within the data sheet limits for the distribution over the 
>>clock tree to the IOBs.
> 
> 
> I'm not sure that I understand this - are you replying to
> 
> 
>>>There's a second issue here, which is that zeroing out a delay (if
>>>that was the IP vendor's intent) is dangerous anyway. The only place
>>>at which the delay is zeroed is at the DCM's inputs; it's not going to
>>>be 'zero' anywhere else on the die.
> 
> 
> If CLK3 is heavily loaded, and CLK1 is not, then surely they will have
> a (very) significant phase difference at the end of the die opposite
> the DCM?
> 
> Rick
> 

Article: 79891
Subject: Re: Synthesis question
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 25 Feb 2005 09:36:18 -0800
Links: << >>  << T >>  << A >>
kowari wrote:
> Oh ok. Next state is not a registered output. The state machine is a 2
> process state machine ie the clocked process registers state from next
> state, and the next state process is a combinatorial process.

Consider using a single process.

          -- Mike Treseler

Article: 79892
Subject: Re: Virtex-4 performance, where is it?
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 25 Feb 2005 09:58:18 -0800
Links: << >>  << T >>  << A >>
Antti,

Was this in the software tools alone?  Sounds like you tried it on a pcb?

In hardware the DCM can generate output clocks up to 450 MHz (-11) (we 
have seen it work up to 600 MHz, I think the -12 is going to get set at 
500 MHz for all corners).  All outputs.

LF mode max is 150 MHz for CLK0.

HF CLKFX max (for _MS_MAX) is set at 315 MHz primarily to meet the CLKFX 
jitter output max issue.

CLKFX actually also goes to well over 450 MHz, but the jitter at 450 MHz 
for some M and D values is more than 20%, which makes CLKFX less useful.

Basically, it is a way for us to gently suggest that CLKFX not get used 
at these high frequencies due to the increase in jitter.

This is no different that V2, or V2P, where the CLKFX output is not as 
"hot" as the DLL outputs.

We have many customers who evaluate their M, D CLKIN freq, CLKFX out 
jitter, and go beyond the datasheet limits, but I have to say that when 
they do that, they will always get the frequency (it will always 
function), but they have to accept the risk of having too much jitter 
(they need to be sure they have enough slack).

Some folks pass the output to an external PLL to clean up the CLKFX 
output before they use it (like an icst.com ics8745 PLL/quad driver -- 
output jitter is ~50 ps P-P with a CLKFX input!!!).

One last comment:  the input restriction when operating in HF mode (> 
120 MHz) is arbitrary:  it can be less.  The issue again is with jitter 
generated.  And, also with testing every single possible input frequency 
and every possible M and D.  (Would just take too long -- even though 
the device is all digital, can't sell what you don't test.)

The good news is that it is not a PLL.  With a PLL, testing takes 
forever as the PLL must lock each time (and that takes a long time, 
compared to the all digital DCM).  So the testing we do is only as 
extensive as the data sheet.

[To think about:  With an M/D of 10 bits total, and lets us say going 
from 1 MHz to 500 MHz in 1 MHz steps, that is 2E19 choices, and we have 
4 modes (another 2 bits), we get >2E31 possible tests.  We have to 
whittle that down to something that can be done in 100 ms for production 
test, and something that can be done in a week or two in the lab (also 
automated) for characterization.  Oh, and we have to do this with lots 
of CLBs toggling, and IOs switching, too.  I once figured that if it 
took 10 ms to do each test (we lock, measure frequency and jitter) it 
would take .01*2E31 = 249 days to test.]

I suggest you try it (use FPGA editor to put in the M, D and mode you 
want).  Then measure the output jitter.  If it works, and meets your 
needs, you may email me directly to get a Xilinx Official "OK to use" 
statement (i.e. we will support you forever with that combination of 
Fin, M, D, on that part).  There are just too many combinations to 
support them all!

I recognize there are 'Magic Numbers' that we all end up using, so there 
is not an infinite number of options that get used.

http://tinyurl.com/6tbnu

Have fun.

Austin

Article: 79893
Subject: Re: Virtex-4 performance, where is it?
From: "Antti Lukats" <antti@openchip.org>
Date: Fri, 25 Feb 2005 19:01:20 +0100
Links: << >>  << T >>  << A >>
Hi

I am using FX only:

 Inst_m125: m125 PORT MAP(
  CLKIN_IN => sysclk,
  CLKFX_OUT => clk,
  CLKIN_IBUFG_OUT => open,
  CLK0_OUT => open,
  LOCKED_OUT => open
 );

V4LX25-10, in Xilinx Clocking Wizard
setting "Max speed"
                fin                fout
LOW      24-120        24-160
HIGH    120-280        160-280

setting "Max Range"
                fin               fout
LOW      16-84         16-112
HIGH      84-168       112-168

as you see the maximum frequency when using
100MHz reflck in is 168MHz ! for -10 speed grade
actually its 160 as there is no M/N ratio that producdes 168

:(

Antti






"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag
news:%hJTd.23$vt.355@news-west.eli.net...
> From p 29 of the DS302 v1.4 Virtex 4 Data Sheet: DC and Switching
> Characteristics, the output clocks from the DCM in the *high frequency
mode*
> shows 210-280 MHz capable FX outputs (for the slower -10 device) to pick
up
> where the *low frequency mode* drops off.  The input for the high
frequency
> mode can be as low as 50 MHz if the DFS mode is all that's used.
>
> 100 MHz in, 100*M/N out up to 280 MHz in the -10 device.
> Check to make sure you're 1) working in HF mode and 2) you're not using
the
> standard outputs - just the DFS.
>
>
> "Antti Lukats" <antti@openchip.org> wrote in message
> news:cvnl3m$102$01$1@news.t-online.com...
> > Hi
> >
> > there are lots of PR news about how much better, etc..
> >
> > but doing a very simple task with V4 I was really surprised:
> >
> > to test max clock for an XC9572XL-5 (cuctomer needs 125MHz)
> > I used V4 development board as programambel clock source.
> > 100Mhz comes in, goes to DCM and goes out.
> > nothing else
> >
> > with V4LX25-10 the maximum frequency that the DCM was possible to set
was
> > 168MHz!
> >
> > changing the speed grade to -11 allowed to set fout to 180MHz,
> > but even that seems kind low for the performance leader ???
> >
> > The DCM could generate a max freq of 315MHz, but that case the input
> > frequency
> > is required to be more than 120MHz, and my development board has only
> 100Mhz
> > oscillator useable :(
> > hopefully I am missing something and higher frequencies are actually
> > possible too.
> >
> > ok this time the 180MHz was sufficient for our testing -
> >
> > XC9572XL-10 (max freq in datasheet 125MHz) did work very well
> > until input freq 150Mz, with 180MHz the first flip started to divide by
3
> > surprisingly deliver very clean 60MHz clock.
> >
> > Another "nice" thing the first XC95 PLD we used was not supported by
> > Impact 6.3 !!! Xilinx has silently dropped support of some PLDs from
> > latest ISE/impact - the XC9536 device was recognized as
> > XC9536_unsupported !! by impact and it did not program it.
> > funny is that the development board where this PLD was also
> > holds a large logo of Xilinx, ah well just another thing to know...
> >
> > Antti
> >
> >
>
>



Article: 79894
Subject: dealing with NGO files
From: "RobJ" <rsefton@abc.net>
Date: Fri, 25 Feb 2005 10:03:11 -0800
Links: << >>  << T >>  << A >>
I'm trying to integrate a piece of IP that was delivered in NGO format into 
a verilog design. I've scoured the ISE and XST documentation and the Xilinx 
answers database and there is really not a complete description of this 
flow. I'm assuming the IP provider sythesized the block to EDIF (with 
Synplify I think), then used edif2ngd to convert the EDIF netlist to NGO. 
This block is being provided for free by a Japanese company as part of a 
convoluted foundry relationship and I have no recourse for help from them.

I can place and route the NGO file by itself, but I can't get XST to run 
with the NGO module instantiated in the verilog. I've tried the

// synthesis attribute box_type of IP_BLOCK is "black_box";

synth directive but XST seems to ignore it. If I try to add the NGO file to 
the ISE project the file gets added as a top-level module instead of down in 
the hierarchy where it belongs, and the instantiated block remains unkown to 
ISE. When I run XST it immediately gags because it can't find the block 
(despite the black_box directive). I've also tried inluding a verilog 
description of the port list for the block in the project, which ISE 
recognizes and then the instantiated block is no longer unkown, but when I 
run XST I get some bizarre errors.

Basically I'm flailing here. Any help appreciated.

Bob S. 



Article: 79895
Subject: Re: Implementing Multi-Processor Systems in FPGAs
From: DerekSimmons@FrontierNet.net
Date: 25 Feb 2005 10:07:58 -0800
Links: << >>  << T >>  << A >>

For me to answer your question let me tell you a little bit about
myself. In the fall of 1987 I entered college at RIT. I was exposed to
a lot of new computer hardware. Growing up I was exposed to computers
designed for data processing. I bought a Commodore Amiga to do my
school work on and it turned out to be an excellent choice because it
allowed me to work files from IBM PC and Apple Macintosh environments.
Remember at this time IBM's were still primarily CGA (4 colors -
cyan, white, magenta and black) and Macintosh's were black and white.
Commodore Amiga had a quasi-12-bit color mode called HAM. For
recreation one of the first freeware applications I discovered
raytracers. The Commodore Amiga was a 16/32-bit MC68000 at about 14 Mhz
(IBMs were 16, 20, 25 and Mac was 8 Mhz). In some of my free time
between classes I spent time at the library researching different ways
to accelerate raytracing. The first and most obvious way was to buy an
accelerator or co-processor card with a faster processor and floating
point co-processor. I think it was in byte magazine I saw an article on
Transputers and I had read articles on transputer products being
developed for the Amiga. I saved my money while waited for the products
to be completed but eventually the projects were canceled. Late one
winter with the money saved I bought a CSA Education Kit. I could
compile and run transputer applications on an IBM bridge card and the
copy them to the Amiga file system and view them from the Workbench
desktop. I also made it a habit of visiting Rochester's surplus shops
and through dump luck I found a factory tray of eight T800s. The guy
who ran the shop didn't know what they were, seeing that they were
gold told me he would have to charge me a premium for them, $10. Using
a Vector prototyping board I connected the eight processors to the CSA
card. I just wired them up so that they could properly reset. I
didn't have money buy any memory so I just used the on chip ram. I
could implement a very small raytracer and when I out grew the memory
of one processor I would pair them up. Eventually I had a tightly
coupled processor made up of an arrangement of 8 transputers in a cube
topology. I think it was about a year later I was a HAM radio flea
market found my next upgrade. This guy and his son brought a real truck
load of junk. I remember him have bar code scanners, data entry pads,
and parts of old telephone system. One of things I found was a black PC
expansion case. The front was ripped off, on the back I could see the
rows of 37 pin connectors and through the vents I could see the tops of
gold chips. I asked him how much it was. He told me it was marked and
came over and found the price for me. He charged me $20 for it. The
friend with asked me what I bought and I told him I'm not sure but
I'll show you. We took it back to the car where I removed the top.
Inside where 5 CSA 4 transputer boards, a crossbar board, an INMOS B008
with the graphics TRAM and who ever had it had tucked the cable for the
graphics TRAM inside. My transputer setup had moved from the Amiga to a
dedicated Everex Step 386/33 Mhz. My raytracer evolved into a hypercube
and I was able to let the main rendering routine recurse more or I
added on more features. As time went on, the topology evolved into a
sophisticated pipe line. A few years after graduating from college I
started buying them through eBay. My system is split between an
industrial PC, the old black PC expansion case and a VME cabinet. The
last time I spent anytime doing anything with I was having problems
with the worm program that maps the network. I could determine if the
network had gotten so big it was timing out before it had finished
discover the network or if there was a hardware failure. I do follow
the other news group (comp.sys.transputer). I haven't compared it to
a modern PC, currently it I have a PIII 500 Mhz laptop and dual 733 Mhz
desktop. But it would require a rewrite to take advantage of the PC
threading architecture.

I bought the NIOS II Development kit because I liked the development
tools and I can see the potential for doing the same kind of things
that I have done with transputers. I bought the kit and a Lancelot
video adaptor. I plan on developing a 3D graphics core for it with a
similar api to OpenGL with intentions of making it into a commercial
product. With the Stratix II development board, I see the SDRAM as the
biggest bottle neck. I have sketched out an elaborate buffering system
that should alleviate this. I would also like to be able to configure
the resolution and color depth from software. When I roll it over as a
core the wizard would give the engineer the option of letting it be
programmable with default values or hard code the settings.

I have been poking around the couple of days about and have found a
couple of post about engineers implementing multi-processor systems. I
would say have of them sounded like student projects. If anybody has
implemented multi-processors systems I would like to hear about their
experiences and any after thoughts from the experience. Since a lot of
this is still new to me, I'm still at the steep part of the learning
curve, I would appreciate if anybody has any projects that they can
share with me.

Derek


Article: 79896
Subject: Re: Virtex-4 performance, where is it?
From: "Antti Lukats" <antti@openchip.org>
Date: Fri, 25 Feb 2005 19:36:44 +0100
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag
news:cvnovq$bjl4@cliff.xsj.xilinx.com...
> Antti,
>
> Was this in the software tools alone?  Sounds like you tried it on a pcb?

thanks for long answer, well I used the lazy approuch ie Xilinx Clock Wizard
and in that tool its not possible to get more than 160MHz from 100MHz input.

in order to get around it pumped up the device speed grade to higher and
selected
the maximum that was possible (that was 180MHz)

and I did measure that 180MHz as output signal and used that signal to feed
a PLD
I did not try to set the DCM params by hand.
so I dont know how much the chip actually could perform, I do belive that it
could way higher than the 160MHz (or 315)

its just that the Xilinx Clocking Wizard made me wonder big time why I cant
enter values for higher frequncies when I want too! There should be an
super-user checkbox that allows to enter out spec values as well.

Antti



Article: 79897
Subject: Re: VIE in electronic and FPGA design
From: Georgi Beloev <gbH8SPAM@beloev.net>
Date: Fri, 25 Feb 2005 10:49:30 -0800
Links: << >>  << T >>  << A >>
KCL wrote:
> Hi,
> 
> Does anyone have already heard about VIE (Volontariat International en 
> Entreprise: kind of professionnal volunteer in an other country than France, 
> little bit like trainee) in their firm?
> Because as I am looking for a (first) job as possible in FPGA design, and 
> also interested to do it abroad rather than France, I actually search 
> informations about VIE and firms that use it  because it seems to be a good 
> ways to find out an interesting position.
> 
> Regards,
> 
> Alexis 


I haven't seen the VIE term before. Maybe you want to look for "intern" 
or "internship" positions.

-- Georgi



Article: 79898
Subject: Error in ISE 6.3
From: "KCL" <kclo4_NO_SPAM_@free.fr>
Date: Fri, 25 Feb 2005 19:55:10 +0100
Links: << >>  << T >>  << A >>
I doesn't know if someone allready notice this error because is too evident 
that no one use this template, just give an eye
edit > langage templates > VHDL > commun construct > port > input > 64 bits
 Do you see the problem??
Sometime  software developper are also tired :)

Regards
Alexis



Article: 79899
Subject: Re: VIE in electronic and FPGA design
From: "KCL" <kclo4_NO_SPAM_@free.fr>
Date: Fri, 25 Feb 2005 20:44:23 +0100
Links: << >>  << T >>  << A >>
no this is different from an internship , but it's special to france before 
else to do your military service you could at the place some humanitarian 
mission in a foreign country or working abroad now that military duty have 
been removed , humanitar have been replaced bye this VIE you work a french 
or foreign firm voluntary in a foreign cuntry.



"Georgi Beloev" <gbH8SPAM@beloev.net> a écrit dans le message de news: 
p_WdnT1skevk7oLfRVn-hA@megapath.net...
> KCL wrote:
>> Hi,
>>
>> Does anyone have already heard about VIE (Volontariat International en 
>> Entreprise: kind of professionnal volunteer in an other country than 
>> France, little bit like trainee) in their firm?
>> Because as I am looking for a (first) job as possible in FPGA design, and 
>> also interested to do it abroad rather than France, I actually search 
>> informations about VIE and firms that use it  because it seems to be a 
>> good ways to find out an interesting position.
>>
>> Regards,
>>
>> Alexis
>
>
> I haven't seen the VIE term before. Maybe you want to look for "intern" or 
> "internship" positions.
>
> -- Georgi
>
> 





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