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Symon, See below, Austin Symon wrote: > Austin, > Does V4 incorporate any new packaging technology wrt SI over and above > previous packages? Yes. We call in the SparseChevron(tm) and it is superior to IBM's 'signal cross (tm?)' (the "best package in the industry") Did Dr. Johnson help Xilinx design the V4 packages? No he did not. It was all of our own hard work (with some outside SI experts called in). 'School of Hard Knocks' often leads to innovation. HJ may have an opinion on the package design, however. Since his reputation as an SI expert is important to him, his opinion will be impartial, and all his own. It wasn't that our previous packages were terrible, they just were not as good as they could be. With increased speed, and more IOs, and 10 Gbs MGTs, we just can't use "good enough" anymore. It has to be "best." > Looking at the pinout of the balls on some of the packages for V4, it > appears that Xilinx hasn't made it easy to layout the PCB. That may be true. It is also true that to get the improvements we may have made layout more of a challenge. Which would you like to have? A crummy package and terrible signal integrity and lots of jitter, or a great package, great SI, low jitter? That is just too easy. The FF668 package > for the LX parts looks good, but the FF672 for the FX parts is a real dog's > breakfast. There are Vccint, Vccaux, Vcco and GND balls all over the place. > What's going on? It is called making the signal loops as small as possible, thereby reducing inductance. The pcb routing is done automatically anyway. Is there something esthetically pleasing about patterns? You may see the beauty of the SparseChevron once you recognize its benefits! > Sometimes I wonder if the guys who design these package pinouts actually get > to use them in a real system. We do. We have to design characterization pcbs (12+ layers) for all packages. We also have to design demo pcbs with even greater number of layers. Look at the V4 netowrking and memory platforms: pretty tough stuff. But they work, at speed, with great performance. If you can;t make it work, then having an easy pattern is worthless. Making the package perform well is only half > the job. Well, see the presentation. We might just surprise you with how a bad package can screw up the SI so that no pcb can improve upon it. The performance depends on how well you can connect it to a PCB. Again, that is not all true. A bad package pinout can prevent any pcb from having a good return path for power, ground, and signals. Compettion would like you to think that there are no bad packages, just bad pcb design. Nice trick if you can get away with it. But SI Experts (like HJ), Cisco, IBM, etc. all know better. The pcb can only make it worse, not better.Article: 79751
Two clarifications; Paul H. wrote "EasyPath, which is a way of taking defective silicon which has failed final test and recycling it to see if the defects won't matter in your design. I have yet to meet a customer who thinks this sounds like a good idea. Note that this is a different approach from the properly planned use of redundancy which deliberately builds in additional resources up-front, which can be switched in if needed. " I fail to see the difference. Both approaches assume that a localized defect has no general impact if it is in an area not used by the specific design. Any different evaluation must be strictly emotional. Use engineering common sense instead! More important is the cost analysis of, 56 (or really 36) EasyPath die vs 143 Hardcopy die coming from a wafer. (Let me just use Paul's numbers) In Paul's mind this is a big advantage for Altera. In reality, it is a big burden. Altera must run and pay for an extra wafer for those 143 die, while Xilinx gets the 36 (or whatever) die "for free", since the wafer is already paid for by the normal FPGAs. Xilinx does not run extra wafers for EasyPath, until that business reaches a similar volume as the normal FPGA volume. Xilinx FPGAs are manufactured in very large volume (hundreds of thousands of devices per working day), and there should be no lack of candidates for EasyPath. It's all a matter of testing and logistics, and we are good at that... EasyPath is a win-win proposition for the customer and for Xilinx. Peter AlfkeArticle: 79752
MK, Well, Altera's claim of 39% performance speed gain is bogus. And they continue to make it (it is in all their ads). We feel compelled to set the record straight. Wouldn't you defend your performance if you can show it is better? Should we be quiet and not say anything? I thought I was being very polite, and posting a link to a technical presentation. You can ignore it if you like. There were no comments (other than the title). AustinArticle: 79753
Hi Austin, Thanks for your reply! I must say it's good to see Xilinx are taking this issue seriously. As you say, the silicon performance improvments necessitate these package improvements. I totally agree that the package can screw up the whole thing. The tales of woe on CAF from folks trying to design with PQ208s show that! My concern was that the package pinout can make it hard to design a PCB layout which has good SI. Power vias turning ground planes into Swiss cheese and all. Ah well, it's about time I did a board with an extra microvia layer.... Cheers mate, Syms.Article: 79754
Hello Rick. rickman wrote: > I have had email exchanges with a person at Xilinx about this. None of > the Spartan chips are currently supported, but I have been told that > Xilinx is "committed" to providing partial-reconfiguration for the > Spartan 3 chips (this was over a year ago, so I'm not sure what > "committed" really means ;). There are two problems with getting PR > working in the Spartan 3. Yes, I read your previous posts on the subject. > The first issue is the fact that PR has used tristate buffers to connect > to long lines to provide the intermodule connections. This has worked > in the Virtex family. However the V4 chips also have no tristate > buffers. So Xilinx is working on that problem and I expect their > solution will be portable to the S3 parts. Wow, that is something new. I didn't know they had dropped the TBUFs in Virtex-4! Does this mean that Virtex-4 is not reconfigurable by modules? > But the second problem is the lack of interest in S3 PR in the customer > base. I am surprised at this since it can make the difference between a > $10 FPGA and a $20 FPGA and/or a $5 flash memory and a $10 flash memory. Exactly. A single chip solution is worthwhile on its own sake. > I believe you are looking to use PR the same way I want to. You don't > need to do it on the fly with the rest of the chip running, you just > need to download modules in different combinations to provide the final > download that suits the current need. But I may be mistaken here. If > you don't have an external processor to load the FPGA, were you planning > to use the internal proc to do that? I have a known-good initial bitstream in a configuration Flash (the 'boot' image). After that I disable it and I read data from a memory card, including the other bitstreams. > I may be mistaken, but I think > there is a special block in the FPGA to allow internal logic to load a > new design (I forget the name, it may be IMAP). I seem to recall that > the Spartan 3 does not have this block so PR must be controlled from the > outside. That is the ICAP block I was asking about. It seems the SP-3 has an ICAP but it either doesn't work or there are no tools to use it. > There are some limitations to loading the partial configuration while > the rest of the chip is alive. It may be that you just plain can't do > it, or it may just be that the chip does not allow blocks adjacent to > the partial load to be active. There are also limitations in that an S3 > PR block must use full columns while the Virtex chips (or maybe just V4) > can load partial columns. I do recall that the S3 is much more limited > in the way it can do PR than the Virtex parts. Yes. I am assuming appnote 290 applies to Spartan-3 also, I used it to prepare my design for PR. Many Xilinx documentation refer to SP-3s partially reconfiguring, but I haven't found the definitive reference yet... Cheers. PabloBleyerKocik /"Person who say it cannot be done pbleyer / should not interrupt person doing it." @embedded.cl / -- Chinese proverbArticle: 79755
Antti Lukats wrote > pretty nice is linux inside RJ45 jack (price 99EUR) Which manufacturer?Article: 79756
Austin, The PR says the speed files have been released, but they are nowhere to be found on Xilinx's website. Do you have a URL for 6.3i speed files, or does this PR refer to ISE 7.1i? -KevinArticle: 79757
I have a generic question on how memory controllers work. A device places the address, data, and write cmd to the controller then issues a request (REQ). After the memory operation completes the device gets an ACK back from the memory controller. What's the typical way REQ and ACK work? Does REQ stay high until ACK comes back? and how long does ACK stay high? Thanks,Article: 79758
Thanks to all for your advice. Altera finally did get in touch with me today around 6 pm, and I feel the issue is close to a resolution. Also, these posts were not meant to bash Altera. I've used both Xilinx and Altera extensively, and they both have their strengths and weaknesses. Thanks again. JohnArticle: 79759
Weddick, There simple answer is it depends on the memory controller. It's totally up to the logic in the memory controller how these signals will interact. REQ could simply be a write stobe to a fifo or register, or it could act in conjucntion with the ACK as a semaphore. You definitely need to provide more info if you want a more detailed answer. JohnArticle: 79760
Pablo Bleyer Kocik wrote: > Hello Rick. > > rickman wrote: > >>I have had email exchanges with a person at Xilinx about this. None of >>the Spartan chips are currently supported, but I have been told that >>Xilinx is "committed" to providing partial-reconfiguration for the >>Spartan 3 chips (this was over a year ago, so I'm not sure what >>"committed" really means ;). There are two problems with getting PR >>working in the Spartan 3. > > > Yes, I read your previous posts on the subject. > > >>The first issue is the fact that PR has used tristate buffers to connect >>to long lines to provide the intermodule connections. This has worked >>in the Virtex family. However the V4 chips also have no tristate >>buffers. So Xilinx is working on that problem and I expect their >>solution will be portable to the S3 parts. > > > Wow, that is something new. I didn't know they had dropped the TBUFs > in Virtex-4! Does this mean that Virtex-4 is not reconfigurable by > modules? V4 still has full PR capability, but the old software does not support it. I have been told they are actively working on the software to support PR in the V4 chips. In fact, V4 has more capability I believe in that it can be configured in partial columns. >>But the second problem is the lack of interest in S3 PR in the customer >>base. I am surprised at this since it can make the difference between a >>$10 FPGA and a $20 FPGA and/or a $5 flash memory and a $10 flash memory. > > Exactly. A single chip solution is worthwhile on its own sake. > > >>I believe you are looking to use PR the same way I want to. You don't >>need to do it on the fly with the rest of the chip running, you just >>need to download modules in different combinations to provide the final >>download that suits the current need. But I may be mistaken here. If >>you don't have an external processor to load the FPGA, were you planning >>to use the internal proc to do that? > > > I have a known-good initial bitstream in a configuration Flash (the > 'boot' image). After that I disable it and I read data from a memory > card, including the other bitstreams. Do you require the FPGA to be running when you load the other bitstreams. >>I may be mistaken, but I think >>there is a special block in the FPGA to allow internal logic to load a >>new design (I forget the name, it may be IMAP). I seem to recall that >>the Spartan 3 does not have this block so PR must be controlled from the >>outside. > > > That is the ICAP block I was asking about. It seems the SP-3 has an > ICAP but it either doesn't work or there are no tools to use it. If it is there, I am pretty sure it does not support configuration. >>There are some limitations to loading the partial configuration while >>the rest of the chip is alive. It may be that you just plain can't do >>it, or it may just be that the chip does not allow blocks adjacent to > > >>the partial load to be active. There are also limitations in that an S3 >>PR block must use full columns while the Virtex chips (or maybe just V4) >>can load partial columns. I do recall that the S3 is much more limited >>in the way it can do PR than the Virtex parts. > > > Yes. I am assuming appnote 290 applies to Spartan-3 also, I used it to > prepare my design for PR. Many Xilinx documentation refer to SP-3s > partially reconfiguring, but I haven't found the definitive reference > yet... APP290 does not apply to S3 yet. What docs talk about PR in S3s?Article: 79761
Dig, I have recently evaluated EasyPath, Hardcopy II, and LSI's structured ASICs. Here are my observations: EasyPath: EasyPath did not offer a sufficient reduction in cost per piece as compared with Altera or LSI. But the real show-stopper is that EasyPath for the Virtex-4 parts will not come in the fastest speed grade. Hardcopy II: Reasonable NRE, and huge reduction in cost per piece as compared to Stratix II costs. In addition, Altera claims 50% speed-up in a typical design. I have several big gotchas though. First, Hardcopy II has no M512 RAMs, so if you proto with SII, you have to understand that any M512s will be converted to gates. Two, Hardcopy II devices have much fewer I/O than the closest comparable FPGA. Again, if you proto with SII, make sure you only use pins available on both. Lastly, according to Altera you will not get any speed up on RAM access times. The access times on these guys are quite large, so if you are shooting for 300 MHz+, you're RAM output better feed right into a register, becuase there will be almost no time for route or additional logic. LSI: Reasonable NRE and pretty low minimum volumes. Logic density is adequate, but it has very little embedded memory. I would be taking a hard look at LSI, if I didn't need so much RAM. Hope that helps. JohnArticle: 79762
mk wrote: > On Wed, 23 Feb 2005 10:51:01 -0800, Austin Lesea <austin@xilinx.com> > wrote: > >>See: >> >>http://biz.yahoo.com/prnews/050223/sfw032_1.html >> >>Austin > > Hi Austin, > I am a mainly X based consultant and I'd like to say that this is > getting ridiculous. Why don't you leave the PRs at PRNEWS and keep the > relatively high SNR of this group where it's at ? The technical tit > for tat between you and Paul@A is nice but just copying the PRs here > is not necessary IMO. MK, I am a big advocate of keeping marketing and PRs out of the news group. But I must admit, that the way Austin did it, is the way I would like for all non technical items to be posted here: short link. It is obvious from the link that it is a PR NEWS article, and you can skip it if it does not interest you. I think we are wasting more bandwidth by having this non technical "complain" thread than Austins original post. Keep it up Austin ! Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 79763
Hi,
In my project,there's a xilinx IP core. I want to use the synplify7.7 to
synthesize it, but there's a warning when synthesize .
The warning is :
@W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":29:10:29:19|Unbound
component counter_11 mapped to black box
@W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":37:10:37:18|Unbound
component counter_4 mapped to black box
my project nane is itu656_dec : a decoder for itu 656 video
The following code has been used in my project:
component counter_11
port (
Q: OUT std_logic_VECTOR(10 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
ACLR: IN std_logic);
end component;
component counter_4
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
ACLR: IN std_logic);
end component;
Can anybody help me? Give me some suggestion to deal with this kind of
warning.
You'd better send me some document of how to using xilinx ip core and hwo to
synthesize it with synplify.
Thank's a lot!!!
willie CHEN
Article: 79764Do I get a ticket for the Love Boat also? Outside cabin, next to the swimming pool, good food, babes, sunshine, booze... Man, I might not even miss this newsgroup after a while... Peter AlfkeArticle: 79765
Hallo, is there a way to get delay-info on resource-basis? I'd like having the output of "XDL -report -pips" annotated with delay(functions). The purpose is to identify fast resources to ease up the design of macros such as those, XST tries to detect when syhthesising HDL and to gain my personal learning-curve about fpga-design (I don't see HDL-compilers do this=20 for me). I'm tired of writing just-a-few-slice-designs, wait a minute or two for the toolchain to print out a result, then modify the test, and again wait for the toolchain, and all this just to find out, what=20 leaving a carry-chain or whatever might cost. Any ideas, how to get "XDL -report -pips" annotated with useful delay-estimates? Gruss Jan BrunsArticle: 79766
I have a simple binary FSK demodulator circuit based on the old 74HC297 DPLL, a divide-by-4 counter, and a flip flop. I'm interested in seeing how many such circuits I could pack into a cheap FPGA like one of these: http://www.fpga4fun.com/board_pluto.html (uses Altera EP1K10TC100) http://www.altera.com/products/devices/acex/acx-index.html but I'm not sure where to start. I'm just trying to figure out a ballpark number, i.e. "one copy will just barely fit" or "seems like you should be able to get five copies in there with room to spare". Is this a common kind of problem - translating old-school discrete chip designs into FPGA? I did a lot of googling for resources along this vein but didn't come up with much. At the low price of the fpga4fun board, it's almost an impulse buy, but I wanted to ask the newsgroup first and mull it over. RobArticle: 79767
"Tim" <tim@rockylogic.com.nooospam.com> schrieb im Newsbeitrag news:cvj7nd$533$1$8300dec7@news.demon.co.uk... > > Antti Lukats wrote > > > pretty nice is linux inside RJ45 jack (price 99EUR) > > Which manufacturer? > http://www.picotux.com/ go figure out, I am not sure 100% similar looking module was at other booth as well. AnttiArticle: 79768
Hi Willie, please refer to the "core generator guide" document. It explains how to do it. the document is located at YOUR_XILINX_ISE_INSTALLTION_FOLDER \doc\usenglish\books\docs\cgn good luck, MotiArticle: 79769
Dear Francesco Poderico, Please send me your compiler for PicoBlaze. Thansk in advance! Best regards, ZotyaArticle: 79770
"willie CHEN": > In my project,there's a xilinx IP core. I want to use the = synplify7.7 to=20 > synthesize it, but there's a warning when synthesize . > The warning is : > @W: CD280 = :"G:\project\itu656_dec\itu656_Decoder.vhd":29:10:29:19|Unbound=20 > component counter_11 mapped to black box > @W: CD280 = :"G:\project\itu656_dec\itu656_Decoder.vhd":37:10:37:18|Unbound=20 > component counter_4 mapped to black box "Xilinx-boxes" are synthesized within Xilinx-toolchain, as it seems. Xilinx: XAPP409 might solve your problem. I'm not sure if that's really important when using synplify, but reading XILINX: xst.pdf might also make sense. Gruss Jan Bruns =20 >Article: 79771
Hi! I have problem to send data from an own IP- core to the Microblaze. The IP-core is a state machine witch writes data to the FSL-bus every second clock cycle and the Microblaze receive the data with the function: “microblaze_bread_datafsl(value,0);” The problem is that the Microblaze only reads 16 times and then it stalls. The C-code is a while(1) loop and I print the data with the function: “xil_printf("value = %d\n\r ", value);” in a Hyper Terminal on a PC.
PARAMETERS for the FSL-bus: C_FSL_DEPTH = 16 C_EXT_RESET_HIGH = 1
PORT for the FSL-bus: FSL_Clk = sys_clk , External SYS_Rst = net_gnd, Internal
Software: XPS 6.2.03i Hardware: LC1000 (Virtex-II)
Could anyone please help me?
Backman
Article: 79772Probably the best way to start would be to use something like the schematic entry module in either the xilinx or altera free toolsets,you'll find that most standard logic devices are available as parts which you can pick and place. Synthesising with one copy will give you an idea of how many you might expect to fit into any device.Article: 79773
Vladislav Muravin wrote: > Andres, > > I am not an Altera guy, but i think that the safe reset implies that the > very first flip-flop in a chain has to be reset > to a certain default value, not to the value generated by the internal > logic. > > Imagine that you have a state machine implemented with a certain encoding > for each state. > If the reset is applied asynchronously, then your state register shall be > resetted, but some of the flipflops can start "moving" before others are get > out of reset. Consequently, your state machine could get into an undesirable > state. > > So, Altera design assistant advises you to have something like this (hope > the code is right, I am not VHDL guy as well): > > process (clk,Areset_n) > begin > if (Areset_n) > Areset_n_d <= "0"; > Areset_n_sync <= "0"; > elsif rising_edge(clk) > Areset_n_d <= "1"; > Areset_n_sync <= Areset_n_d; > end if > end > > > Hope this helps. > > Vladislav > No, sorry. You misunderstood my question: The flip flop chain I use makes sure that the reset is applied synchronously to my logic that is also to all state machines. The question was if the flip flops of the synchronizer chain should be set by the asynchronous external reset or not. Thank you. Rgds AndrésArticle: 79774
Hej Anders,
I might help you but I would need more information about your system.
Could you email me the .mhs and the C code?
Göran Bilski
Backman wrote:
> Hi! I have problem to send data from an own IP- core to the Microblaze. The IP-core is a state machine witch writes data to the FSL-bus every second clock cycle and the Microblaze receive the data with the function: “microblaze_bread_datafsl(value,0);” The problem is that the Microblaze only reads 16 times and then it stalls. The C-code is a while(1) loop and I print the data with the function: “xil_printf("value = %d\n\r ", value);” in a Hyper Terminal on a PC.
>
> PARAMETERS for the FSL-bus: C_FSL_DEPTH = 16 C_EXT_RESET_HIGH = 1
>
> PORT for the FSL-bus: FSL_Clk = sys_clk , External SYS_Rst = net_gnd, Internal
>
> Software: XPS 6.2.03i Hardware: LC1000 (Virtex-II)
>
> Could anyone please help me?
>
> Backman
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