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On Tue, 1 Mar 2005 23:57:21 +0100, "Falk Brunner" <Falk.Brunner@gmx.de> wrote: > >"Mike Treseler" <mike_treseler@comcast.net> schrieb im Newsbeitrag >news:38jpfiF5ou9etU1@individual.net... > >> Hazard-free as long as the set and reset pulses >> are well formed and far enough apart in time. >> It's not difficult to make an oscillation >> burst otherwise. > >After all, what is a RS-FF good for nowadays?? The same things that it has always been good for. For a cost of 2 gates, it gives you a memory. It doesn't need a clock. It remembers an event until you have time to deal with it. It's ideal for handshaking, and for communicating between different clock domains. Can you name any other digital circuit which is so versatile, at such a small cost? Even if you ignore the 'cost', as you might do in an FPGA implementation? RickArticle: 80151
On 2005-03-01, B. Joshua Rosen <bjrosen@polybus.com> wrote: > Parallel simulators are apparently a much harder problem then you might > suspect. A number of years ago I was discussing this issue with the CTO of Savant tries to do parallel VHDL simulation: http://www.ececs.uc.edu/~paw/savant/ "The SAVANT project has been integrated with UC's WARPED parallel simulation research project and provides an end-to-end VHDL-to-batch simulation capability. WARPED provides a general purpose discrete event simulation API that can be executed in parallel or sequentially. Built on top of WARPED is a VHDL simulation kernel called TyVIS that links with the C++ code generated from SAVANT for batch sequential or parallel simulation." But as it is a research project, I don't know how well it succeeds.Article: 80152
Laurent Gauch <laurent.gauch@deleteallcapsamontec.com> wrote: > Very interested for my new embedded product. > Some questions: > for when the first samples? > for when on the production market? > are the s3 and s3e FPGA pin compatible? A quick view ds099-4/p36 versus ds312-4/p 22 show that they are non pin compatible. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 80153
Just curious - not really relevant to anything, but I've just run up the ISE GUI for the first time, and it looks very familiar. I can't quite put my finger on it, but does it look like an old version of ABEL? Or an old Lattice tool? Also not really relevant to anything, but does anyone recognise the graphics toolkit it was written with? It doesn't really look like native Windows. I'm looking for a toolkit for some code that has to run on both Windows and *nix, so it would be interesting to find out. RickArticle: 80154
Hallo, it seems that XILINX ISE7.1 is out. Anybody has goy his hands on it? Does it now use QT for the GUI? Anybody using the Linux version? Is the WindU compatiblity layer gone? Any other comments? And when to expect Webpack 7.1? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 80155
I dont know what kind of simulation are you using but I suggest you to try and simulate it using the "simulate post-translate VHDL model" instead of the "simulate behavioral model" i hope that it will work for you. Moti.Article: 80156
Richard Thompson <nospam@nospam.com> wrote: > Just curious - not really relevant to anything, but I've just run up > the ISE GUI for the first time, and it looks very familiar. I can't > quite put my finger on it, but does it look like an old version of > ABEL? Or an old Lattice tool? > Also not really relevant to anything, but does anyone recognise the > graphics toolkit it was written with? It doesn't really look like > native Windows. I'm looking for a toolkit for some code that has to > run on both Windows and *nix, so it would be interesting to find out. QT is a toolkit available for many systems. Otherwise you can also use the Windows Toolkit and use Wine as a compatiblity layer, like Nike Engelhard does with Linear Technologu switchercad. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 80157
Hi, I am new to FPGA and VHDL. My job requires me to design a PCI board using Altera PCI development board Has anyone used that before and is there any method to hasten the design process??? -- Stevywww.totallychips.com - VHDL, Verilog & General Hardware Design discussion ForumArticle: 80158
Christian Schneider wrote: > > Thanks for all the benchmaks! Very interessting information! > > If I interpret the data correctly, two CPU result in the same simulation > time, so they are of no benefit? That's a pity! The 2 CPU result is 2 copies of the same simulation running at the same time. There are no multithreaded RTL simulators available commercially. That measurement shows how the memory bus and machine architeture scales. --KimArticle: 80159
On Wed, 2 Mar 2005 09:56:59 +0000 (UTC), Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >QT is a toolkit available for many systems. >Otherwise you can also use the Windows Toolkit and use Wine as a >compatiblity layer, like Nike Engelhard does with Linear Technologu >switchercad. I'm trying to choose between gtk and QT - QT does seem to be more portable. Your 7.1 posting makes me think that ISE 6.3 isn't using QT, though - any idea what it does use? RickArticle: 80160
Richard Thompson <nospam@nospam.com> wrote: > On Wed, 2 Mar 2005 09:56:59 +0000 (UTC), Uwe Bonnes > <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: > >QT is a toolkit available for many systems. > >Otherwise you can also use the Windows Toolkit and use Wine as a > >compatiblity layer, like Nike Engelhard does with Linear Technologu > >switchercad. > I'm trying to choose between gtk and QT - QT does seem to be more > portable. Your 7.1 posting makes me think that ISE 6.3 isn't using QT, > though - any idea what it does use? WindU, requiring a per seat license, reason why there is no Webpack for Linux. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 80161
B. Joshua Rosen wrote: > Parallel simulators are apparently a much harder problem then you might > suspect. A number of years ago I was discussing this issue with the CTO of > IKOS (since bought by Mentor). To me it seemed that simulation should be > a highly parallel problem but he claimed that there had be a number of > attempts at parallel software simulators (as opposed to hardware > acceleration engines) and that no one had succeeded. With the advent of I had also similiar discussion with Mentor Graphics Chief Technologist few years ago. And the story was identical. He said that there have been many different startups (and R&D project inside bigger companies) that tried to do parallel simulator, but none succeeded well enough. My imprssion was that the hard problem is how to partition the design to minimise the events needed to communicate between the threads. That communication latency was the killer for performance. --KimArticle: 80162
Hi all, I tried the solution mentioned in Answer Record 19789 to prevent XST from flooding the report with messages of the form "Set user-defined property "BEL = FFX" for instance <q_reg0> in unit <counter> (ie, setting the environment variable XIL_XST_HIDEMESSAGES to hdl_level). However, I still get the messages and a report over 3500 lines long. Can someone help? Thanks. -JimArticle: 80163
Uwe Bonnes wrote: > Hallo, > > it seems that XILINX ISE7.1 is out. Anybody has goy his hands on it? > Does it now use QT for the GUI? Anybody using the Linux version? Is the > WindU compatiblity layer gone? Any other comments? > > And when to expect Webpack 7.1? > http://www.xilinx.com/ise/ossupport/index.htm Webpack supports linux so I guess WindU is gone. SylvainArticle: 80164
Hi again, My CLOCK TO OUT timings are going off by a small amount (requested 4 ns, got 4.112 ns) on a databus going out of the chip. Will this cause problems in real life? Should I raise the drive strength? I've configured the IOBs to use FAST 12 mA LVTTL, the data is clocked at 40 MHz. I am using a Xilinx 2V1000-5 FG456. There are 32 such outputs driving a single IO Bank, I'm worried that going beyond 12 mA will cause SSO problems on that bank. -JimArticle: 80165
Uwe Bonnes wrote: > Hallo, > > it seems that XILINX ISE7.1 is out. Anybody has goy his hands on it? > Does it now use QT for the GUI? Anybody using the Linux version? Is the > WindU compatiblity layer gone? Any other comments? > > And when to expect Webpack 7.1? > Xilinx.com says Webpack 7.1 should be out by March 2005. Any time now... :-) I'm excited to see that ISE will now include a simulator. I somehow found ModelSim's interface rather clunky (I also dont make use of most of the features it offers, like Tcl scripting), and I'd like to see how ISE Simulator fares. Also, MXE's artificial speed limit makes simulations more painful. I guess the only downside to ISE 7 is that we bought ISE 6.3 just a few weeks back :-( -JimArticle: 80166
Hi, sure I mean engineers and "techies", I think this newsgroup would not be the right place for marketing people. Another general thing is, that I don't want to be mistaken. I think the support in this newsgroup is already very good, thanks to all the people who do that. regards, BenjaminArticle: 80167
digi, did you includ the xilinx libraries in modelsim? they should be listed into the library tab of modelsim workspace. andreaArticle: 80168
On Wed, 02 Mar 2005 04:13:34 -0700, Jim George <jimgeorge_@_gmail.com> wrote: > I'm excited to see that ISE will now include a simulator. I somehow >found ModelSim's interface rather clunky (I also dont make use of most >of the features it offers, like Tcl scripting), and I'd like to see how >ISE Simulator fares. Also, MXE's artificial speed limit makes >simulations more painful. The 'new ISE simulator' (no name yet?) looks like it's an option with Foundation, and there's a free kludged version with Foundation and BaseX. There's no pricing at the online store yet for the full version. The docs say that it supports VHDL93, Verilog2001, and SDF, as well as the usual GUI stuff. The screenshot looks like ISE, so they've obviously done at least some work on it, rather than buying it all in. This is *really* going to piss off the EDA vendors. XST has already screwed Mentor, Synplicity, and Synopsys, and this will eventually do more of the same. The interesting question here is whether Xilinx can co-exist with the EDA industry, and what happens when the bust-up comes. RickArticle: 80169
Michel Billaud <billaud@labri.u-bordeaux.fr> wrote: > Jeremy Stringer <jeremy@_NOSPAM_endace.com> writes: > > > One thing I guess you could consider is that the GPL can make things > > difficult for companies that want to integrate your IP block into a > > commercial product, because of the requirement to redistribute source > > code. > > Well, not a big problem. Such companies are free to contact the author > for a different licensing of the same source if they have different > needs. Only true if the gpl licenced ip comes to them unmodified. > > MB -- Sander +++ Out of cheese error +++Article: 80170
"Richard Thompson" <nospam@nospam.com> schrieb im Newsbeitrag news:rv9b211auqu58u35nq0ds2hb7iseoteu1i@4ax.com... > On Wed, 02 Mar 2005 04:13:34 -0700, Jim George <jimgeorge_@_gmail.com> > wrote: > > > I'm excited to see that ISE will now include a simulator. I somehow > >found ModelSim's interface rather clunky (I also dont make use of most > >of the features it offers, like Tcl scripting), and I'd like to see how > >ISE Simulator fares. Also, MXE's artificial speed limit makes > >simulations more painful. > > The 'new ISE simulator' (no name yet?) looks like it's an option with > Foundation, and there's a free kludged version with Foundation and > BaseX. There's no pricing at the online store yet for the full > version. > > The docs say that it supports VHDL93, Verilog2001, and SDF, as well as > the usual GUI stuff. The screenshot looks like ISE, so they've > obviously done at least some work on it, rather than buying it all in. > > This is *really* going to piss off the EDA vendors. XST has already > screwed Mentor, Synplicity, and Synopsys, and this will eventually do > more of the same. The interesting question here is whether Xilinx can > co-exist with the EDA industry, and what happens when the bust-up > comes. > > Rick Hi Rick, you are hard-mouth possible not without reason, well there are 2 sides always to the story :) I would say Xilinx does what it has todo in order to provide single and user friendly environment for its products. There are different approuches for the environment, the EDA tool integration, as far as I have seen its almost always an disaster and in many cases end of story Atmel FPGA FPSLIC stuff, that includes the vendor stuff and only a integration of those tools - its a real nightmare to use. It is also the reason why Atmels FPSLIC are not selling - the software is almost completly unuseable. Actel is the same story, a little better maybe, but again the EDA tools required in order to get the full toolchain working make the Actel software very hard to use. Xilinx and Altera both have almost all in one solutions and those are more friendly and are defenetly one key to success for the products. There are different customers and different wishes so I would say there should be 2 different options 1) ALL IN ONE VENDOR version that includes all the support for that vendor with all needed utilities 2) scripting environment for EDA tools from 3rd parties those 2 should be kept separate completly, all attempts to integrate the 3rd party EDA tools into single GUI have failed so far (IMHO) If Xilinx adds simulation support to the xilinx main GUI based environment that makes the environment better. If EDA tools from 3rd parties are still supported from scripting command line that would be sufficient and satisfy all the needs. AnttiArticle: 80171
Sander Vesik <sander@haldjas.folklore.ee> writes: > Petter Gustad <newsmailcomp6@gustad.com> wrote: >> "Michael Polovykh" <kefir@rissa.ru> writes: >> >> > So you have a fridge. Put Cyclone into it during PLL work for 30minutes :) >> > And tell us about this experiment - we are interested in it too :) >> >> I dubt his fridge will go as low as -20 ?C. > > Considering he is from .ru and its winter, he just needs to leave it outside > overnight. When I went to work this morning it was -18 °C (I live in Oslo, Norway). Russia is usually a bit colder. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 80172
No problem. I had to think a little on how to solve it. t's not a normal
system.
Yeah, in fact it seems that the microblaze architecture and the available ips aren't really well suited for this type of multiprocessing (i.e. only with pools of shared memories). Much better would be to take advantage of the local memories (maybe using a shared memory too along with the FSL connections).
I wished I had time to try it out.
It seems not so easy to manage: I think that after the initialization sequence there would be anyway problems to manage the same code for both the processors... In fact, I think that it would be rather easy to "jump" to the different code for the processor rather than "branching" on the code depending on the CPU constant signal (identification). What do you think?
My view of multiprocessing is more >of distributed processing where each
processor has it's own memory and >the communication between are done
>with message passing using FSL. Very much like to old transputer >concept.
Yep, it seems one of the model destined to become dominant in the next years (thinking about CELL Architecture)...
Article: 80173It's coming out in ISE 7.1, which is shipping this week. Speedprint won't actually print the values in the speedfile until service pack 1, which will be out around the middle of March. John McCluskey On Mon, 28 Feb 2005 08:53:06 -0800, Kevin Brown wrote: > Has anyone found the -12 Virtex4 speedfile that are mentioned in the > latest Xilinx press release? I haven't seen them anywhere on their > website. > > > -KevinArticle: 80174
On 2005-03-02, Jim George <jimgeorge_@_gmail.com> wrote: > I guess the only downside to ISE 7 is that we bought ISE 6.3 just a few > weeks back :-( Is it licensed with the time based license? My impression is that free upgrades are possible during the one-year license period. I'll soon try if it is so, as we too purchased ISE license couple of months back.
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