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I'm responding to your first question about moving graphics. What development board are you using? And how much memory is available and how is it organized? By moving graphics, do you mean 2D or 3D graphics? You have two choices: just in time rendering implementation or a double buffered display. The just in time rendering display doesn't require as much memory and it works great for text and simple 2D graphics. An example of this is the older arcade games (Pac Man, Space Invaders, Atari 2600). A double buffer display is memory hungry and it is used by the 3D cards of today. Which method are you intending on using? DerekArticle: 83226
When you say VGA what do you exactly mean? VGA was an implementation of a graphics adapter made by IBM. It became the standard for PCs because other venders picked it up and supported it on the PC. Are you trying to create an implementation of a VGA card or are you trying to create display card for displaying images from a PC using the PCI bus? DerekArticle: 83227
Hi Brendan, > In terms of "PVT" - Process, Voltage & Temperature : In the WPT currently > you can, for V4 FX devices, vary Vccint and the ambient temperature. When I enter 1.25V vs. 1.20V in WPT 4.1, I'm given 687 mW vs. 660 mW of VccInt static power for a LX80, in addition to the 234 mW of VccAux power. Similarly, for some random amount of logic utlization, I get 2727 mW vs. 2618 mW of dynamic power. It seems to me that all the tool is doing is increasing the V in P = VI. However, increasing V should (a) increase dynamic current draw roughly linearly and (b) increase sub-threshold leakage by the square of 1.25/1.2. Neither of these effects appear to be modeled. Regards, Paul Leventis Altera Corp.Article: 83228
"Paolo" <P.Prete@msn.com> wrote in message news:R9qbe.4404$TR5.302@news.edisontel.com... > Hi, > This board: > http://www.altera.com/corporate/cust_successes/customer_showcase/csh-seventech_lp.html > has similar characteristics, besides is available a Software Dev Kit to > immediately develop your program in C++. > My company, buy this board to develop gambling machine. Our company > doesn't have an inside structure to develop hardware, but only software. > Before we developed our software on PC platform. But the PC platform it's > not good for an embedded use. Now with this board we succeed in realizing > excellent products. > On the web page of Seventech, you can also see a sample C++ code to > realize a graphic animation with this board. > With this board it is possible to realize graphic animations with very > good performance and the cost, also for the companies, it is <300$, for an > only piece. > > Paolo What if we don't want to write c++ ? You don't give the price any where on your website. If a company hides the price it usually means I shouldn't bother looking as the products to expensive. Way to much marketing fluff. At least you guys got rid of the flash from your website. On the faq page why would I want to click on every little bit to expand the text ? Where are the full technical specs ? What fpga (and options), how much ram , how much fram , max vga and video output , refresh rate and number of colors , what input voltage , what power supply does it need and comes with it ? Whats in the kit, just the board or cables and power supply ? What additional software is needed ? Can you use the free version of quartus or do you need the full version ? I don't need to that it inspires inovation. I need to know the actual specs to see if it meets my needs. Most engineers I know(including me) hate marketing crap. Even more annoying is the our products better than theirs bs especially in newsgroups.(not you guys) (X vs A etc) At least add a specs page with the exact speifications so we can see what your selling without having to wade through marketing BS. AlexArticle: 83229
Hello, does anyone know the actual pin connections on a Memec JTAG cable IJC-3? The problem is that the connector has 9 pins in a row while the printing on the box shows only 8. Thanks - JanArticle: 83230
Hi Petter,
jtagd does not auto-detect ByteBlasters (of any type) as probing for
them might break other types of hardware attached to the parallel port.
You will need to add it by hand, either using the GUI or using the
command:
`jtagconfig --add byteblaster /dev/parport0`
Hope this helps,
Subroto Datta
Altera Corp.
"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message
news:87pswhj4ml.fsf@filestore.home.gustad.com...
>
> According to byteblaster/INSTALL (in linux/byteblaster.tar.gz):
>
> " If you are using Quartus II 4.0 or later then you do not need a
> kernel driver - Quartus will use the parport driver which is part of
> the 2.4.x and 2.6.x series kernels."
>
> I'm running QuartusII 4.2SP1 under RHEL-3 (2.6.x) . The permissions
> seems fine:
>
> ls -l /dev/parport0
> crwxrwxrwx 1 root lp 99, 0 Sep 7 2004 /dev/parport0
>
> I have a ByteBlasterII connected to the parport on the machine, but
> when I do:
>
> quartus_pgm --list
> Info:
> *******************************************************************
> Info: Running Quartus II Programmer
> Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full
> Version
> ...
> Info: Processing started: Tue Apr 26 10:54:37 2005
> Info: Command: quartus_pgm --list
> No JTAG hardware available
> Info: Quartus II Programmer was successful. 0 errors, 0 warnings
> Info: Processing ended: Tue Apr 26 10:54:37 2005
> Info: Elapsed time: 00:00:00
>
> Any clues?
>
> Peter
>
> --
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing on usenet and in e-mail?
Article: 83231Hi all, I am using Synplify Pro for synthesis. My target FPGA is APEX20KE. I have the following code for rom but the attribute rom_style is not working instead it gave me the following warnings. 1) CL159 Input addrs_in is unused 2) Signal sincos_rom is undriven entity Lookup is port( Addrs_In : in signed(ROM_DEPTH-3 downto 0); -- 10 bit Data_Out : out signed(ROM_WIDTH-1 downto 0) -- 16 bit ); end entity Lookup; architecture Lookup_Synth_Arch of Lookup is -- Declaration for Rom type type Sincos_Rom_Type is array (0 to 2**(ROM_DEPTH-2) -1) of WORD; signal Sincos_Rom: SinCos_Rom_Type; -- Attributes to map Rom to availbale techology library attribute syn_romstyle : string; attribute syn_romstyle of Sincos_Rom : signal is "block_rom"; begin Data_Out <= Sincos_Rom(TO_INTEGER(Addrs_In)); end architecture Lookup_Synth_Arch;Article: 83232
Calculation for synthesis process is more float type or integer type? The old AMD processors have less performance in float than Intel. Also, if cache is so important, newer Xeon have lot of cache. What do you think? "B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> wrote in message news:pan.2005.04.26.12.27.33.541031@PleaseDontSpamMEpolybus.com... > On Fri, 22 Apr 2005 18:48:29 +0200, Marco wrote: > > > I need to buy a new PC. What is the best processor for saving time during > > synthesis projects? > > > > AMD Athlon 64 > > Intel XEON > > Intel Pentium 4 > > > > ?? > > > > Thanks > > Marco > > An A64 with a 1M cache. The cache size is more important then clock speed > and memory bandwidth. I did some benchmarking of common FPGA development > task like simulation and Xilinx builds, > > http://www.polybus.com/linux_hardware/index.htmArticle: 83233
Alex, I am only a customer of that company, you not to ask to me of their web site. I have preferred not to write their web address to avoid to do publicity on the newsgroup. However (apologizing with the whole newsgroup for the publicity) you can read the board specification on: http://www.seventech.it/english/merlinoboard/2.php the Dev Kit description on: http://www.seventech.it/english/merlinosdk/5.php and the sample code: http://www.seventech.it/english/merlinosdk/2.php You can see the board price on the distributors web site http://www.comprel.it (search for "Merlino") I pay a board 260? directly buying from the manufacturing: Seventech Bye Paolo "Alex Gibson" <news@alxx.net> ha scritto nel messaggio news:3d6troF6qakp8U1@individual.net... > > "Paolo" <P.Prete@msn.com> wrote in message > news:R9qbe.4404$TR5.302@news.edisontel.com... >> Hi, >> This board: >> http://www.altera.com/corporate/cust_successes/customer_showcase/csh-seventech_lp.html >> has similar characteristics, besides is available a Software Dev Kit to >> immediately develop your program in C++. >> My company, buy this board to develop gambling machine. Our company >> doesn't have an inside structure to develop hardware, but only software. >> Before we developed our software on PC platform. But the PC platform >> it's not good for an embedded use. Now with this board we succeed in >> realizing excellent products. >> On the web page of Seventech, you can also see a sample C++ code to >> realize a graphic animation with this board. >> With this board it is possible to realize graphic animations with very >> good performance and the cost, also for the companies, it is <300$, for >> an only piece. >> >> Paolo > > What if we don't want to write c++ ? > > You don't give the price any where on your website. > If a company hides the price it usually means I shouldn't bother looking > as the products to expensive. > > Way to much marketing fluff. > At least you guys got rid of the flash from your website. > > On the faq page why would I want to click on every little bit to expand > the text ? > > Where are the full technical specs ? > What fpga (and options), how much ram , how much fram , max vga and video > output , refresh rate and number of colors , what input voltage , > what power supply does it need and comes with it ? > > Whats in the kit, just the board or cables and power supply ? > What additional software is needed ? > > Can you use the free version of quartus or do you need the full version ? > > I don't need to that it inspires inovation. > I need to know the actual specs to see if it meets my needs. > > Most engineers I know(including me) hate marketing crap. > > Even more annoying is the our products better than theirs bs > especially in newsgroups.(not you guys) (X vs A etc) > > At least add a specs page with the exact speifications > so we can see what your selling without having to wade through marketing > BS. > > Alex >Article: 83234
Is there an easy way to convert a plain ascii file of hex numbers etc. into a SOF format or similar in order to program the UFM of the MAX II? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 83235
"Subroto Datta" <sdatta@altera.com> writes: Hi Subroto, Thank you for your reply. > You will need to add it by hand, either using the GUI or using the > command: > > `jtagconfig --add byteblaster /dev/parport0` I tried this, but it resulted in an error: jtagconfig --add byteblaster /dev/parport0 Unable to add hardware (Unknown hardware) However, I took an old Windows PC and sat it up as a jtag server which seems to work fine. I can then program from the Linux machine using: quartus_pgm -m JTAG -c "ByteBlasterII on jtaghost [LPT1]" chain.cdf The odd thing is that I don't specify the password on the client side, but it works... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 83236
This is for the Xilinx guys on the newsgroup (sorry if you've heard this before): Could you make Picoblaze a standard part of ISE distribution? All it takes is to include the assembler and to make ISE recognize the .PSM files and at build time, assemble them to VHDL files and include it with the rest of the project. Maybe to also make Picoblaze into a Coregen block. Any thoughts? Thanks.Article: 83237
Duane Clark <dclark@junkmail.com> wrote in message news:<Y0Wae.193$Gd7.137@newssvr21.news.prodigy.com>... > Duane Clark wrote: > > > > Ehh... what the heck. I can't post the files directly, since the > > originals are copyrighted by Xilinx. But if you know how to use diff > > files, then here it is: > > http://www.leewardfpga.com/fpga/plb_dimm.diff > > > > Oh, and while at it, I included a simple testbench in the same > directory. The files bd_test.vhd and bd_test_siml.vhd are separate tests > that do slightly different things. You compile one or the other into the > testbench. The top level testbench file is bd_top.vhd. Hi Duane, again me here, I started working on the diff file, but I think it lacks of the dimm_controller.vhd implementation (that I think it's your revision of the ddr_controller.vhd, right? ). Or I am doing something wrong? Anyhow I'm checking if I can modify it myself. Can you confirm this? Any chance to check that file to? Thank you very much and sorry again!Article: 83238
SOF and POF are closed secret formats :( you should be able to initialize the UFM from either HEX or MIF both are simple ASCII but you need to write a small converter yourself from yourself in most cases that would be some 20 to 30 lines of PERL code antti "Petter Gustad" <newsmailcomp6@gustad.com> schrieb im Newsbeitrag news:87fyxdipdw.fsf@filestore.home.gustad.com... > > Is there an easy way to convert a plain ascii file of hex numbers etc. > into a SOF format or similar in order to program the UFM of the MAX > II? > > Petter > > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 83239
Paul, Since we power the pass gates from Vccaux through a band gap referenced supply for the entire interconnect, many simple minded formulas that you may come up with will not apply. Austin Paul Leventis (at home) wrote: > Hi Brendan, > > >>In terms of "PVT" - Process, Voltage & Temperature : In the WPT currently >>you can, for V4 FX devices, vary Vccint and the ambient temperature. > > > When I enter 1.25V vs. 1.20V in WPT 4.1, I'm given 687 mW vs. 660 mW of > VccInt static power for a LX80, in addition to the 234 mW of VccAux power. > > Similarly, for some random amount of logic utlization, I get 2727 mW vs. > 2618 mW of dynamic power. > > It seems to me that all the tool is doing is increasing the V in P = VI. > However, increasing V should (a) increase dynamic current draw roughly > linearly and (b) increase sub-threshold leakage by the square of 1.25/1.2. > Neither of these effects appear to be modeled. > > Regards, > > Paul Leventis > Altera Corp. > >Article: 83240
Ok, I will buy an Athlon 64. What model has the best price/performace ratio now? Thanks Marco <Alpharomeo2k@gmx.de> wrote in message news:1114538838.484589.181300@z14g2000cwz.googlegroups.com... > But the old AMD processors aren't sold anymore. Since 1999 the Athlon > had higher FP performance than Pentium III and although the Netburst > architecture managed to get the crown back over time in a lot of > applications, the situation changed again. Now the Opteron/Athlon 64 > achieves higher performance for most scientific calculations, 3D > calculations for games and similar stuff. For video encoders, some > audio encoders and some renderers the situation is favouring Netburst > architectures in case of single core CPUs. > > Regarding the help of big caches the same holds true, which I wrote to > Simon Peacock: > But why does an Opteron with slow registered RAM and only 2.6 GHz and 1 > MB L2 cache achieve higher SPECfp results than the fastest Xeon (3.6 > GHz) or Pentium 4 (3.8 GHz) and also higher SPECint results (using the > ICC compiler)? Because they are different architectures. The K8 has a > shorter pipeline (code with many branches doesn't hurt that much) and > higher execution bandwidth per clock and the Prescott/Nocona has a > longer pipeline with less execution bandwidth per clock, but higher > clockspeeds. > > Here is a nice article comparing the Pentium 4 with 1 MB L2 to the new > one with 2 MB L2: > http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2353&p=2 > > > Matthias >Article: 83241
Hi Jim, I have my own wishlist too, but what you suggest is not on my list, and I doubt will be implemented they way you suggested. 1) Xilinx politics: ISE is FPGA tool, EDK is embedded development tool. So picoblaze would not be integrated to ISE 2) A few releases ago it was possible to create own cores for coregen, with latest ISE releases this seems to be more hidden than it used to be. Picoblaze could be added to coregen, that would be possible - unfortunatly I can not do it (see before it was possible in ISE 5.x) 3) All the 'integration' actually isnt so necessary - all that is needed is the ability of DATA2MEM to initialize the parity bits (sorry maybe that is fixed in 7.x I havent checked). So you can just add the picoblaze with empty BRAM and run a batch/shell script that uses DATA2MEM to combine the .PSM into the ISE generated .BIT, pretty much similarly as EDK is doing it. antti PS I basically agree with you that the way PicoBlaze can be used is not very easy, a lots of looking for what to download, fill up forms, ... all pain :( "Jim George" <send_no_spam_to_jimgeorge@gmail.com> schrieb im Newsbeitrag news:oLednQC2_6Z9yPPfRVn-pA@comcast.com... > This is for the Xilinx guys on the newsgroup (sorry if you've heard this > before): > > Could you make Picoblaze a standard part of ISE distribution? All it > takes is to include the assembler and to make ISE recognize the .PSM > files and at build time, assemble them to VHDL files and include it with > the rest of the project. Maybe to also make Picoblaze into a Coregen > block. Any thoughts? > > Thanks.Article: 83242
Simon, The FX12 is shipping. The FX60 very soon now...... If you need the FX60, contact your FAE for ES material. We have either met, or exceeded every date that we agreed to for the roll out of the Virtex 4 family. Austin Simon Heinzle wrote: > Hi Austin, > > what about the FX series? When are FX60 - FX140 going to ship? > > Regards, > Simon > > > Austin Lesea wrote: > >> Simon, >> >> >> The Virtex-4 LX25, LX60, LX100, LX200, SX25, SX35, SX55, and FX12 >> FPGAs are shipping today. Xilinx now has a total of 20 FPGAs shipping >> at 90nm -- three times as many 90nm FPGAs as its nearest competitor. >> >> All there, all ready for you, >> >> AustinArticle: 83243
Hi Austin, from what you say - are ANY FX with MGT available as ES ??? We have received FX12 and FX20, but we have NO confirmed delivery of FX with MGTs :( expected in June or something like that, but not very confirmative we do have a project that depends on the early availability of FX (with MGTs!) Antti "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:d4lm1d$9iq1@cliff.xsj.xilinx.com... > Simon, > > The FX12 is shipping. > > The FX60 very soon now...... > > If you need the FX60, contact your FAE for ES material. > > We have either met, or exceeded every date that we agreed to for the > roll out of the Virtex 4 family. > > Austin > > Simon Heinzle wrote: > > > Hi Austin, > > > > what about the FX series? When are FX60 - FX140 going to ship? > > > > Regards, > > Simon > > > > > > Austin Lesea wrote: > > > >> Simon, > >> > >> > >> The Virtex-4 LX25, LX60, LX100, LX200, SX25, SX35, SX55, and FX12 > >> FPGAs are shipping today. Xilinx now has a total of 20 FPGAs shipping > >> at 90nm -- three times as many 90nm FPGAs as its nearest competitor. > >> > >> All there, all ready for you, > >> > >> AustinArticle: 83244
Antti, FX MGT ES is not released yet, as we are still performing the last of the verification and characterization tasks. Contact your FAE if you need FX MGT parts right now. Austin Antti Lukats wrote: > Hi Austin, > > from what you say - are ANY FX with MGT available as ES ??? > We have received FX12 and FX20, > but we have NO confirmed delivery of FX with MGTs :( > expected in June or something like that, but not very confirmative > we do have a project that depends on the early availability of FX (with > MGTs!) > > Antti > > "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag > news:d4lm1d$9iq1@cliff.xsj.xilinx.com... > >>Simon, >> >>The FX12 is shipping. >> >>The FX60 very soon now...... >> >>If you need the FX60, contact your FAE for ES material. >> >>We have either met, or exceeded every date that we agreed to for the >>roll out of the Virtex 4 family. >> >>Austin >> >>Simon Heinzle wrote: >> >> >>>Hi Austin, >>> >>>what about the FX series? When are FX60 - FX140 going to ship? >>> >>>Regards, >>>Simon >>> >>> >>>Austin Lesea wrote: >>> >>> >>>>Simon, >>>> >>>> >>>>The Virtex-4 LX25, LX60, LX100, LX200, SX25, SX35, SX55, and FX12 >>>>FPGAs are shipping today. Xilinx now has a total of 20 FPGAs shipping >>>>at 90nm -- three times as many 90nm FPGAs as its nearest competitor. >>>> >>>>All there, all ready for you, >>>> >>>>Austin > > >Article: 83245
TheMightyShaman wrote: > > Hi Duane, again me here, I started working on the diff file, but I > think it lacks of the dimm_controller.vhd implementation (that I think > it's your revision of the ddr_controller.vhd, right? ). Or I am doing > something wrong? Anyhow I'm checking if I can modify it myself. > Can you confirm this? Any chance to check that file to? > Oops, yep missed that one. It is there now. Have fun.Article: 83246
hi, You might want to give me a chance to look at it before you decide I don't want to learn it!! Great, so I'm doing everything wrong. Well I have something that kinda models the chip(Not what I had posted earlier) will look at yours too obviously. But I don't have much time to get it working. Everything else except the chip interfacing works so far. thanks.Article: 83247
ALuPin wrote: > Hi, > > what does have more advantages when trying to synchronize an incoming external > datastream: > > 1. Synchronize the data bus with some (two or three) register stages > and feed the sychronized data into a FIFO which is an additional > synchronization stage (write clock of FIFO has a different frequency > than the read clock) > It makes no sense to say that you are going to "synchronize the data bus with some register stages". What will invariably happen when you try to do that is that some of the portions of the data bus will occasionally exit the last stage on different clocks. Each individual bit of the bus may be synchronized correctly, but the bus as a whole will not, without taking additional measures. > 2. Feed the data bus directly into the FIFO and synchronize the data coming > out of the FIFO into some (two or three) register stages ? > Why do you need to synchronize the data coming out of the fifo? As you pointed out, the read clock is different from the write clock. So the work of synchronizing is already done for you. This is in fact a very good way of synchronizing a bus.Article: 83248
Mohammed A Khader wrote: > Hi all, > > I am using Synplify Pro for synthesis. My target FPGA is APEX20KE. I > have the following code for rom but the attribute rom_style is not > working instead it gave me the following warnings. > > 1) CL159 Input addrs_in is unused > 2) Signal sincos_rom is undriven > > > entity Lookup is > port( > Addrs_In : in signed(ROM_DEPTH-3 downto 0); -- 10 bit > Data_Out : out signed(ROM_WIDTH-1 downto 0) -- 16 bit > ); > end entity Lookup; > > architecture Lookup_Synth_Arch of Lookup is > -- Declaration for Rom type > type Sincos_Rom_Type is array (0 to 2**(ROM_DEPTH-2) -1) of > WORD; > signal Sincos_Rom: SinCos_Rom_Type; > > -- Attributes to map Rom to availbale techology library > attribute syn_romstyle : string; > attribute syn_romstyle of Sincos_Rom : signal is "block_rom"; > > begin > > Data_Out <= Sincos_Rom(TO_INTEGER(Addrs_In)); > > end architecture Lookup_Synth_Arch; > You sure you define your address as SIGNED ??? Your array is defined as natural range. It's also asynchronous. Maybe a clocked process ? did you simulate ? Where is it initialized ? Synplify does usually a good job at inferring roms. Sometimes, some synthesis tools may decide that your rom contents make it easy to implement as LUTs. I would try a synchronous Rom with initialized contents, declared as a constant (not signal) and unsigned index. I think Synplify does support ieee.math_real for constants so if you're going for a sine table, it's easy. Bert CuzeauArticle: 83249
Hi Petter, Hi Petter, I made an error in my earlier post. The command should be: jtagconfig --add ByteBlaster /dev/parport0 The "byteblaster" is case insenitive. If this does not work send me your email and I will have the person who tested this out help you. Hope this helps, Subroto Datta Altera Corp.
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