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Hi, I have a couple of questions regarding VHDL & synthesis for FPGA: 1) Are there any rule-of-thumb measurements for the max. no. of lines of code in a clocked process statement (I assume each extra code statement adds accumulated delays between successive clock edges) ? 2) Are there any good books that discuss issues relating to VHDL-FPGA synthesis i.e. exactly what code translates to & the various implications ? Many thanks DaveArticle: 83651
Neo wrote: > Info, > The code above given by you for onehot did sysnthesize differently. the > "case" version systhesized to 3 LUT's involving only OR gates and didnt > infer priority structure infact it optimized as you have mentioned to a > series of OR gates. But the "if" version systhesiszed to 6 LUT's and > inferred a priority structure. Leonardo was used for the systhesis. > Yes my point exactly. Not all tools do this correctly. Leoanrdo is right. Just try Precision Synthesis (or other tools) if you can and compare the results. The if .. elsif is a priority encoder which has a well defined behavior for the overlapping cases (more than one 1 in the vector), and this requires more logic than the "pure one hot". This edscription is more predictible acroos tools. BertArticle: 83652
backhus wrote: > Hi Symon, > for (most) of the given examples case and if-elsif will give the same > result. > Why? > Because in both cases :-) your selector is fully covered (uses all of > the bits of a vector or whatever you use as a selector). Your if-elsif > collapses into a parallel structure, because there is no priority of one > value over the other possible. > > but how about this: > > Selector <= A&B&C; -- I MUST do this for a case statement ! > case Selector is > when "001" => Output <= Input1; > when "010" => Output <= Input2; > when "100" => Output <= Input2; > when others => Output <= (others => 'Z'); > end case; > > vs. > > If C = '1' then > Output <= Input1; > elsif B= '1' then > Output <= Input2; > elsif C= '1' then > Output <= Input3; > else > Output <= (others => 'Z'); > end if; > > NOW the case produces a parallel multiplexer structure that is sensitive > for the given code of Selector. > The if-elsif does something different. Whenever C becomes '1' (No matter > how unlikely or unneccesary this might be in your particular design) it > switches Input1 to the output. Here we have the always cited priority > encoder. > > To get the same functionality with a case you have to write a different > code: > > Selector <= A&B&C; -- I MUST do this for a case statement ! > case Selector is > when "--1" => Output <= Input1; > when "-10" => Output <= Input2; > when "100" => Output <= Input2; > when others => Output <= (others => 'Z'); > end case; > > Now the first >when< hits whenever C becomes '1'. > This code might produce something more "parallel" than the if-elsif, but > who knows about the tricks of modern synthesis tools. :-) > > Have a nice synthesis > > Eilert Just a few errors : 1. you can in fact qualify the expression and not use a signal. A variable is usually preferable if you want one (otherwise, you must add Selector in your sensitivity list, and this slows down the simulation without usefulness). case SLV3'(A&B&C) is -- with subtype SLV3 is std_logic_vector (3 downto 0); 2. output <= 'Z' infers a tristate, nothing to do with a don't care! A don't care '-' does eliminate C from the result. 3. case ... is when "--1" is wrong ! Comparing anything (but a '-') to '-' produces a false. Comparing with '-' (to ignore the comparison) requires the use of std_match (not usable in case statement). VHDL is not always intuitive... Bert CuzeauArticle: 83653
Hi Peter, > Remember, any circuit that does not work close to its speed limit > represents waste. Well, I've seen a fair share of 15-25ns CPLD designs, filled 60% and running at 4 or 8MHz. Sometimes applications can simply be slow. And developed, debugged and programmed in under an hour and a half. And, especially nowadays, without a smaller or slower part that is any cheaper. But, that's good, isn't it? It would be horrible if the lower end of the market couldn't take advantage of modern technology. Best regards, BenArticle: 83654
1) If you have one clock edge driving 20,000 registers, all 20,000 registers can update at that clock edge. There is no direct penalty for having 2 registers versus 20k. The only limit on the number of lines in a clocked process statement is for your own readability, not the synthesizer's. Code statements don't add delay, complexity from register-to-register adds delay in "levels of logic" to implement the logical path. I can have one statement with enough complexity to force my maximum operating frequency into the single megahertz range and have a 1k line process that runs at 300 MHz. 2) Do you know how to design digital electronics? I'm talking registers, gates, memories, latches. Your best bet may be a text or course on basic digital electronics design to understand how logic is implemented independent of which language is used to model the logic. Once a solid understanding is had, the concept of parallelism versus the serial-native form of computer programming will become obvious. <dave_baker_100@yahoo.co.uk> wrote in message news:1115239039.839241.303280@z14g2000cwz.googlegroups.com... > > Hi, > > I have a couple of questions regarding VHDL & synthesis for FPGA: > > 1) Are there any rule-of-thumb measurements for the max. no. of lines > of code in a clocked process statement (I assume each extra code > statement adds accumulated delays between successive clock edges) ? > > 2) Are there any good books that discuss issues relating to VHDL-FPGA > synthesis i.e. exactly what code translates to & the various > implications ? > > > Many thanks > Dave >Article: 83655
Hello, first, whatever you do, avoid gated clocks at all cost, especially in cases like you have. I am not sure that i understand exactly what you would like to do, but what you should probably do is: (1) Either increase the synchronizing clock (125 MHz will run on VirtexE, but this is close to maximum (LUT-level), i.e.timing constraints must be very thorough). Personally, i would not go for this one. (2) Just create an asynchronous interface, i.e. your "write" strobe is your clock and the "read" strobe is the read clock. But this is more like spplication-specific, depends what exactly you'd like to do. if you could give more details... hope this helps. regards, Vladislav "Wenju Fu" <fwj@nmrs.ac.cn> wrote in message news:ee8dffe.-1@webx.sUN8CHnE... >I posted following message, but nobody respond(I don't know the reason, >maybe it is too naive). I I post it here again, wish someone could help me. > > I am using VirtexE to communication with an ADI's chip. The interface > include, write, read, Data, and Address. I wish FPGA communication with > the chip on FPGA main clock, which is up to 65MHz. I used a synchronized > signal gated with the Clock to generate the write, read signal. Data and > Address signal are synchronized. The problem is: 1) write/read signal > often generate one more period than what I needed. although I could > overcome it by adjust control signal's edge sensitivity, but it maybe > reappear when I resynthesize the design. The reason is time delay of 2 > inputs(one is clock, one is control signal) of the LUT4 vary greatly. Can > I limit delay difference of the 2 inputs to an acceptable level? if it is, > How could I do? 2) the timing of address, data and write/read is > inconsistent with the timing required by ADI. I could delay some signal by > add buffers or invertors. But I am afraid if it is work well if I add this > modular to the top design. Is there any better way? > > if I generate the w/r signal synchronized with the clock, the problem may > do not exist. But I should drive the clock twice high, I don't know if > VirtexE can work well on 125MHz. > > Thank you for your advice.Article: 83656
Hi dave, > 2) Are there any rule-of-thumb measurements for the max. no. of lines > of code in a clocked process statement ? My personal rule of thumb is that I should be able to cram a single process on a page of A4 paper when printed in 8-point courier. But, sometimes the algorithm just won't let you do this. In that case, put page breaks into the source code at strategic points, such as the after an end if, end case and stuff like that. Best regards, BenArticle: 83657
Ben, that's the problem with glaring generalizations: there always are exceptions. Peter AlfkeArticle: 83658
Dear Paul, I never had anything like this in my designs, but... First, you HAVE to use BUFG on the feedback clock, otherwise, the tool cannot automatically infer the deskewing function of DCM (I am not 100% sure about this, Xilinx guys are to ask), and this is what you have to do if you want to eliminate any delays in routing a clock from one edge of the FPGA to another. Second, I do not think that there is any constraint covering what you want to do here. You would probably have to do this manually. Is the clock slow enough to first multiply is and run some counter, whose bits will represent different phases? or if it is high, still can you multiply by 2/3/4 and use both some DCMs with phase outputs and less BUFGs? hope this helps. regards, Vladislav "Paul Boven" <p.boven@chello.nl> wrote in message news:1115126095.342507@blaat.sara.nl... > Hi everyone, > > On a Spartan 3, I would like a single clock-signal to drive the inputs of > all 4 DCM's. How would I get a clock-signal from the bottom to the top > edge of the die, preferably with as little extra jitter as possible? > > I would like to use all 4 DCM's to shift the input signal by a different > amount (say 45/4 = 11.25 degrees, ). But do I need to use a BUFG to > 'feedback' these signals back to the DCM? There's no real 'delay' that I > want to counter, I'm trying to (ab)use the FPGA as a phase discriminator. > > Secondly, I would like to have the four DCM outputs (0, 90, 180 and 270) > each end up on the D-input of a flip-flop. Propagation delay on these > paths should be small, but it is even more important that the signals > arrive at their flip-flops simultaneously, or as much as possible. How can > you enter that kind of constraint? > > There are not enough BUFG(MUX) resources to have all 4 I/Q-phase outputs > of all 4 DCM's run over them. So I'm thinking of not using the BUFGMUX for > that at all, but simply placing my flip-flops close to their associoated > DCMs. Is there any information available on how I can connect to the DCM > outputs (long-lines? hex-lines? neighbours?). What position relative to > the DCM should the 4 FF be at for equal delay? > > When I've synthesized a design, I can see where it has placed all the > resources. But is there any way to see how the actual routing of the > signals over the FPGA is being done, what kind of lines are being used? > > That's enough questions for one posting, I hope someone out there is kind > enough to help me along a bit. > > Regards, Paul Boven, > PE1NUT > Another FPGA-hobbyist > >Article: 83659
Limited quantities of this and other boards are available for loan or for purchase. Contact saeid@xilinx.com for details. Peter AlfkeArticle: 83660
I am a senior technical recruiter with a very reputable firm, Common Agenda. I have postitions to post in the SF Bay Area and very real. My client company is actively interviewing. Please advise if it is acceptable to post here. Eve Ellsworth Senior Recruiter Common Agenda, LLP Tel: (732) 223-7114 Ext. 108 Fax: (732) 223-7116 Email: eve@commonagenda.com Web: www.commonagenda.com ...Partnering with progressive companies in the quest for exceptional talent...Article: 83661
Hallo, where I could find a complete manual (pdf) for programming in Ansi C? I need to understand the meaning of operators like: |= ^= a & 0x07 Many Thanks MarcoArticle: 83662
Hi Paul: As you pointed out, I forgot to include style option as "MIX" in the mpd file. After updating the .mpd file, it works fine. Thanks for your help, AroulArticle: 83663
"Vladislav Muravin" <muravinv@advantech.ca> wrote in message news:8Taee.12828$3U.745079@news20.bellglobal.com... > (2) Just create an asynchronous interface, i.e. your "write" strobe is your > clock and the "read" strobe is the read clock. > But this is more like spplication-specific, depends what exactly you'd like > to do. > You bad man! ;-) Personally, I'm against adding clocks wherever possible. I'd much rather retime the data strobes into enables in a master clock domain if it's at all possible. It's more work up front, but a lot easier when you include the time taken to build your timing constraints in the UCF file and debug the unsimulatable (!) timing errors that occur one in a [m|b|tr]illion operations!. YMMV, Syms.Article: 83664
Well, this did not work. His name is Saeid. and you just have to add the usual @xilinx.com. PeterArticle: 83665
"EveEllsworth" <eellsworth@commonagenda.com> wrote in message news:1115242339.015173.259360@z14g2000cwz.googlegroups.com... > I am a senior technical recruiter with a very reputable firm, Common > Agenda. I have postitions to post in the SF Bay Area and very real. > My client company is actively interviewing. > What other kind of interviewing is there? How do you passively interview? Syms.Article: 83666
This is an unmoderated newsgroup, so there is nobody to answer your question. I would say if you keep it short and sweet, and do not double-post (as you did), the reaction will be positive. If you ramble, it will be negative. There are people who are eager to make a change, and there still is unemployment.... Peter AlfkeArticle: 83667
Hi Peter, > that's the problem with glaring generalizations: there always are > exceptions. Us in apps do tend to mostly see the corner cases - extreme speed, extreme size, trying to shoehorn that last MHz out of the silicon while trying to shoehorn a few hundred extra lines of code into the silicon etc. I'm getting the feeling that we tend to see the exceptions, more than the rule. In the last two years I have seen, with the introduction of Cyclone and (slightly less so) Spartan 3, the performance bar at the lower end of the spectrum has been raised considerably. The amount of performance and capacity that is available for under $10 nowadays is just amazing compared to three years ago. It's a fun field we're working in. Best regards, BenArticle: 83668
And only if they are FPGA related, please!! I see far more recruiters chasing me after analog, RF, power supply, but never come back with any FPGA breaks. Otherwise go ahead johnjakson at usa dot comArticle: 83669
Johnsons. Joe wrote: > Hello > > I am using a Virtex2Pro board and lately I was trying to use the PowerPC > at the highest speed (300MHz) on my board. I have a function which uses a > lot of floating point instructions The 405 used does not have floating point in hardware! (unless Xilinx 405 is something extra and does...) But the PPC instruction set always support them, in this case by taking exception (or never compile to them and use library routines instead) > for calculating the log, sine, cosine > and such stuff. When I ran this program on the PowerPC it took almost 2 > minutes to perform 1000 iterations at 100MHz. Each log, sine and cosine takes lots of floating point operations... > Then we wanted the code to > run a little more faster and so we implemented the same design at 300MHz. > Even if we didn't expect a three fold increase in speed, there was only an > improvement of a couple of seconds. Can somebody tell me the reason. Would you like to do better than that? If your input has limited range (integers) you can 1) precompute look up tables for each possible input value, next step could be to move the look up tables to the FPGA... 2) do your math in fixed point /RogerLArticle: 83670
1) Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog by Douglas J. Smith gets mentioned alotArticle: 83671
dave_baker_100@yahoo.co.uk wrote: > I have a couple of questions regarding VHDL & synthesis for FPGA: > > 1) Are there any rule-of-thumb measurements for the max. no. of lines > of code in a clocked process statement (I assume each extra code > statement adds accumulated delays between successive clock edges) ? Bad assumption - remember, VHDL is a hardware description language, not a programming language. What limits your timing is the path between flip-flops (usually through combinatorial logic). If each line defines a 'flop and a few levels of combinatorial logic feeding into another 'flop, then it doesn't really matter how many lines you have. Readability is nother question... :) > 2) Are there any good books that discuss issues relating to VHDL-FPGA > synthesis i.e. exactly what code translates to & the various > implications ? I've found some of the Xilinx techXclusives and app notes to be good in this regard - generally, coding style guidelines address this issue. I don't know of any books off hand, though no doubt other people on this NG will. JeremyArticle: 83672
<dave_baker_100@yahoo.co.uk> wrote in message news:1115234006.831800.205660@g14g2000cwa.googlegroups.com... > Symon - thanks for that little gem! > > I have a couple of off-subject questions you may be able to answer: > > 1) Are there any really good books that relate VHDL to FPGA synthesis ? Try getting on a course at Doulos. You used to get a free 'VHDL Golden Reference Guide'. V. useful. There a chap called Jonathan Bromley who posts here who's associated with them, he might be able to advise you on how to find out when the next course is, etc. Best, Syms.Article: 83673
Thanks everyone for your suggestions, I finally got it to work...Article: 83674
Correct, The 405 core we use does not have a FPU. There are FPU cores available that can be used with the new V4 APU, or with the older V2 Pro 405 PPC through the bus. The new FPU in hardware + APU in V4 offers a roughly 80X improvement over the software FPU alone. Something to seriously consider if you have FPU intensive work to do. The new APU interface allows for single cycle multiple word transfers to/from the CPU. Otherwise, you may use the soft FPU that replaces FPU instructions with subroutine calls to code. Austin roger.larsson@norran.net wrote: > Johnsons. Joe wrote: > > >>Hello >> >>I am using a Virtex2Pro board and lately I was trying to use the PowerPC >>at the highest speed (300MHz) on my board. I have a function which uses a >>lot of floating point instructions > > > The 405 used does not have floating point in hardware! (unless Xilinx 405 is > something extra and does...) > But the PPC instruction set always support them, in this case by taking > exception (or never compile to them and use library routines instead) > > >>for calculating the log, sine, cosine >>and such stuff. When I ran this program on the PowerPC it took almost 2 >>minutes to perform 1000 iterations at 100MHz. > > > Each log, sine and cosine takes lots of floating point operations... > > >>Then we wanted the code to >>run a little more faster and so we implemented the same design at 300MHz. >>Even if we didn't expect a three fold increase in speed, there was only an >>improvement of a couple of seconds. Can somebody tell me the reason. > > > Would you like to do better than that? > > If your input has limited range (integers) you can > 1) precompute look up tables for each possible input value, next step could > be to move the look up tables to the FPGA... > 2) do your math in fixed point > > /RogerL
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