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Teodor, plese check the ML403 web pages at http://www.xilinx.com/ml403, especially the "ML403 Demos and Reference Designs" section. There you will find designs for the ML403 that include software to read from and write to the UART and, thus, communicate with a PC on the other end. The CompactFlash card that ships with the ML403 has many demos and most of them use the UART at 9600 baud. The "ML403 Getting Started Tutorial" explains in detail how to set up the board and operate these demos. See http://www.xilinx.com/bvdocs/userguides/ug083.pdf for more information. - Peter teodor wrote: > Hi, I have a virtex4 development kit (ML403) and I plan to communicate with a PC via rs232. I see that you have done some work in the field and I just wanted to know if you have made any progress and if you could give me any hints where to start. > > Thanks > > ///TeodorArticle: 84076
Gavin Scott wrote: > John Savard <jsavard@excxn.anospamb.cdn.invalid> wrote: > > Are there other kinds of software-customizable chips out there that are > > very different from an FPGA? > > These guys: > > http://www.stretchinc.com/ > > appear to be building processor+programmable logic chips with the > goal of compiling C/C++ code into logic for compute intensive > applications. > > G. I looked at that and grocked as much as wanted in a few mins looking at the gif pics mostly. 1st impression you only get 1 Tensilaca cpu for your $ and its pretty humble at about 260MHz but has an embc rating of 4.6 or so right in there with most 200-400MHz embedded DSPs, cpus. How much is this $chip. 2nd the compiler flashes critical C areas into the side engine reducing maybe a few 100 instructionsinto 1 cycle. Then it jumps to the top of the list with rating of about 900 for 200x gain, right on top of TI and BOPs (RIP). 3rd they claim fpgas are pretty expensive, well a risc core with 1 BlockRam and needed LUTs seems to be in the order of $1 and falling or so depending on cpu design etc. FPGA RISC can have any co processor attached as desired with no limits on what it could do bar imagination and the FPGA limits, but you gotta design it yourself, right now, but who knows somebody might have a bright idea. Now if somebody were to do this whole compiler thing using a soft FPGA core and auto magically take chunks of C code and convert to FPGA fabric on the fly, they would likely get just as good results, although they would have to do some work in the reconfigation aspect and justify the swap costs v deliverd gain. Further you could replicate this thing as many times as the fabric allows and you could put in things which were never part of the C program in the 1st place, such as the I/O systems, memory controllers. While these other NOT AN FPGAs are very interesting, you swap 1 set of limits that we know how to deal with, for another set of limits and far smaller market presence if any at all. Anyone remember BOPs, they got borged. regards johnjakson at usa dot com transputer2 at yahoo dot comArticle: 84077
See http://www.xilinx.com/ml401 http://www.xilinx.com/ml402 http://www.xilinx.com/ml403 for currently available V4 boards. We are also working on the ML405 (4VFX20) and the ML410/411 (4VFX60/100 with PCIe). Please contact your local FAE/sales person for more information on these boards. - Peter asoc35@dsl.pipex.com wrote: > Hi, > > I am looking for a Virtex 4 based FPGA development board with ideally a > PCI Express interface and at least a FX-100 Virtex 4. If anybody knows > of any vendors who have this or are working on this, please let me > know. > > Thanks, > > Sam. >Article: 84078
Peter Alfke wrote: > Give up, this is hopeless. > The structures are so different, there is no conversion factor. > Let me give you the extremes: > > The 4-input LUT can be used as either an inverter or a 10-gate XOR > structure, or as a 64+-gate 16-bit RAM, or as a 100-gate sixteen bit > shift register. > The associated fancy flip-flop is worth 7+ gates. > And a slice is twice what I listed above, so it's anything from 2 gates > to 214 gates. > Is that enough leeway? How about a slightly different question. How many gates (NAND2 equivalent) does it take to implement a slice? Or alteranatively, what's the area of a slice? I'd be interested to know for an older device if you can't give out details of your latest devices. Cheers, JonArticle: 84079
Hi, in the Quartus Help I have found the following: #Input Delay from Pin to Input Register logic option # #A logic option that specifies the propagation delay from an input pin #to the data input of the input register implemented in the I/O cell #associated with the pin. This is an advanced option that should be #used only after you have compiled a project, checked the I/O timing, #and determined that the timing is unsatisfactory. For detailed #information on how to use this option, refer to the data sheet for #the device family. # #This option is useful for fine-tuning a design's I/O timing and meet #tSU/tH requirements. # #Legal integer values range from 0 through 63. # #This option is ignored if it is applied to anything other than an #input or bidirectional pin. This option can be set in the Assignment #Editor (Assignments menu). This option is available for CycloneT II #and Stratix=AE II devices. So it seems that this feature is not available for Cyclone devices? Is there some alternative method for Cyclone? Rgds Andr=E9Article: 84080
jgknowla1 wrote: > Greetings, > > I have one of the Digilent spartan-3 starter boards, and have been > browsing this newsgroup for a while. I think I may be ready to design > a small board of my own. I can't seem to find a minimum circuit to get > the chip running. I'm thinking really simple here...no external RAM, > etc. Just a JTAG interface, clock, and reasonable power/ground methods > (decoupling, etc). > > Has anyone seen something like this before? > > thanks, > the newcomer You would think that the simplest approach is to take the schematic that comes with the starter / eval boards and start removing the parts you don't need. That being said, I have never seen an eval board that was designed with minimizing component count or board space as a goal. Most often the design expands to fill the available PC board real-estate. So in reality a better place to start is with a design for a commercial product rather than an evaluation board. The problem is getting access to the schematic for such boards. The problem with designing a "minimum" board with a programmable component is that the design will depend on what you expect to put into the program of the component. In the case of the FPGA this means power supply current, I/O voltages, and decoupling in addition to other components. You could make some estimates for maximum requirements based on the I/O pin count, the I/O standards, and frequencies you intend to use. For Xilinx parts look at the "user guide" rather than the data sheet for useful information on board design and layout. Also look at the power estimator to get a handle on power supply requirements. Good luck, GaborArticle: 84081
Hi, I am using Oregano's mc8051 IP Core on a Altera Cyclone II FPGA (EP2C35) Board with great success. I have synthesized this core many times with Quartus (several procets). The occupied area is about 12%, fmax is about 20 MHz.Article: 84082
Try http://www.neosera.com/ They're a University campus company in Dublin, Ireland.Article: 84083
To be quite honest I wouldn't waste time or money buying IP. It's very easy to write UARTs - Go to the Xilinx website, and search... You could start this way, and use something as easy as HyperTerminal to communicate with the board. Ben "Peter Ryser" <peter.ryser@xilinx.com> wrote in message news:42830660.7090603@xilinx.com... > Teodor, > > plese check the ML403 web pages at http://www.xilinx.com/ml403, especially > the "ML403 Demos and Reference Designs" section. There you will find > designs for the ML403 that include software to read from and write to the > UART and, thus, communicate with a PC on the other end. > > The CompactFlash card that ships with the ML403 has many demos and most of > them use the UART at 9600 baud. The "ML403 Getting Started Tutorial" > explains in detail how to set up the board and operate these demos. See > http://www.xilinx.com/bvdocs/userguides/ug083.pdf for more information. > > - Peter > > > teodor wrote: >> Hi, I have a virtex4 development kit (ML403) and I plan to communicate >> with a PC via rs232. I see that you have done some work in the field and >> I just wanted to know if you have made any progress and if you could give >> me any hints where to start. >> >> Thanks >> >> ///Teodor >Article: 84084
Gabor, Thanks for the ideas... I was originally not thinking deep enough and planning on just getting the chip running, then breaking out the IOs to headers. Of course that doesn't take into account what IO type I would then want to use and any possible level converters. I guess that's why there's a market for demo boards, afterall. thanks, JoshArticle: 84085
Hi, I have constrained some pins in my top-level design as virtual pins: (Altera QuartusII v. 4.2 SP1 To Assignment Name Value Enabled Pin_name Virtual Pin On Yes .=2E. After fitting I get the following warning message for all constrained output pins: Warning : Can't fit auto-select clock for virtual pins "Pin_name1" -- setting clock to GND Warning : Can't fit auto-select clock for virtual pins "Pin_name2" -- setting clock to GND .=2E. When looking at the Quartus Help it is said under ACTION : Assign the Virtual Clock Pin logic option to an appropriate clock signal in the design. But I have not chosen a Virtual CLOCK Pin assignment but Virtual Pins !!! So why do I get these warnings ? Rgds Andr=E9Article: 84086
If you are looking for a commercial product with all the bells & whistles (built in logic analyzer, etc), you should also look at the Mentor Graphics/Ikos emulation products. Last time I worked with their products, they were much smaller, used less power, required less air conditioning than the Quickturn products. They also seemd to be less buggy. I've seen both Quickturn and Mentor/Ikos products used for ASIC emulation. They are NOT trivial to setup, but for a big chip, the cost and hasle is well worth the effort/expense. Good Luck! John ProvidenzaArticle: 84087
Hi, I am looking too for reference designs. The guy from Digilent told me on the phone, that they are waiting to receive the promised reference designs from Xilinx, to put them on their homepage. Maybe someone from Xilinx knows when they will be available. regards, BenjaminArticle: 84088
Hello everybody, I would like to implement a multiplier with word size equal to 16. However I read some book, for example "Computer Arithmetic" by Parhami, and I found only high radix multiplier radix-8 and radix-16 at maximum. Is there that can suggest me some good reference (book, articles etc) about this topic? Thanks a lot GiovanniArticle: 84089
Presumably, if you post this to the arch.Fpga group, you mean to use an FPGA of some kind. SpartanIII FPGA's (amongst others) from Xilinx provide very efficient embedded 18 X 18 multipliers.Article: 84090
Brian, All I am trying to point out is that the load is 6.25pF + 100 ohms, not 12.5pF + 100 ohms. When folks wave their arms and state 12.5pF is the LVDS load, they are miss-stating it. Simple point. And once you do the simulations, or look at the actual waveforms, you realize that it is mostly just a beauty contest. In communications theory, excess bandwidth in the channel only adds to the error rate (due to noise). Some band limiting is a good thing. Too much is a bad thing (eg using the LVDS at 1.3 Gbs where it wasn't designed to be used, that is where our MGTs are to be used). AustinArticle: 84091
"AVG" <hse00045@fh-hagenberg.at> wrote in message
news:d7206b46299a6e210db5611bcf733a3d@localhost.talkaboutelectronicequipment.com...
> Hi,
>
> I am using Oregano's mc8051 IP Core on a Altera Cyclone II FPGA (EP2C35)
> Board with great success.
> I have synthesized this core many times with Quartus (several procets).
> The occupied area is about 12%, fmax is about 20 MHz.
>
>
>
For my own interest I've tried fitting the core to a Xylinx device, an
XC3S200-PQ208 and it won't fit:
Number of Slice Flip Flops: 566 out of 3,840 14%
Number of 4 input LUTs: 4,562 out of 3,840 118% (OVERMAPPED)
Logic Distribution:
Number of occupied Slices: 2,356 out of 1,920
122%
(OVERMAPPED)
Number of Slices containing only related logic: 2,284 out of 2,356
96%
Number of Slices containing unrelated logic: 72 out of 2,356
3%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 4,669 out of 3,840 121% (OVERMAPPED)
Number used as logic: 4,562
Number used as a route-thru: 107
Number of bonded IOBs: 156 out of 141 110% (OVERMAPPED)
IOB Flip Flops: 47
Number of MULT18X18s: 1 out of 12 8%
Number of GCLKs: 1 out of 8 12%
It may be ISE but I can't seem to make a symbol either? It comes up with an
internal error!:
FATAL_ERROR:HDLParsers:vhptype.c:172:$Id: vhptype.c,v 1.6 2001/10/12
21:32:28
weilin Exp $:200 - INTERNAL ERROR... while parsing
c:/temp/8051/mc8051_core_.vhd line 222. Contact your hot line. Process
will
terminate. To resolve this error, please consult the Answers Database
and
other online resources at http://support.xilinx.com. If you need further
assistance, please open a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com
There aren't 222 lines in "mc8051_core_.vhd"!
Article: 84092Hi Folks, I am using Altera's LPM FIFOs. These are deep fifos and was wondering if there are any techniques that people follow to initialize the rd/wr pointers in the fifo so that I can quickly simulate the overflow condition. I use modelsim pe. I would appreciate any thoughts. TIA. -sanjayArticle: 84093
Brian, Sigh. See below. Austin Brian Davis wrote: > Austin, > >>Lots of scope shots are available (ask your FAE). >> > > Then why not publish them, along with a comparison of IBIS/HSPICE > simulations versus the real world measurements? All I can say, is that they are coming. Just takes awhile. Right now we have much more important things to do: tout our power advantage, our static current advantage, our speed advantage, our MGT advantage, our PPC advantage, our SI packaging breakthrough ... Showing an IBIS simulation of a five year old interface is just not high on our list -- too many customers use it, and are perfectly delighted with it. We do not want to be defocused and stop pointing out the areas where we are clearly superior. > > >>But, I am sure our Marketing Folks will be rolling our scope shots >>as part of pitch-packs, etc. for those who are unable or unwilling >>to do the SI engineering that their job requires of them. >> > > > Let's see if I've got this straight [1]: > > A) Xilinx publicly posts in FPGA and SI forums touting their > real world X vs. A package testing, and asks for feedback [2] Sure. > > B) Forum users post some suggested measurements, which a > certain Xilinx employee says they can make I did. Yes. > > C) Two months later, when asked when said measurements might > be published, the very same Xilinx employee cops an attitude OK, so I was snippy. I am told that the measurements will be done, but again, it isn't a high priority. > > >>Get the ML450 board, or ask for the documentation. >> > > > That would be the same manual (UG077 v1.2) that mentions a > HyperTransport compliant DUT interface connector, without > pointing out that the the specified V4 FPGA Cin is 5x the > allowed HyperTransport max Cin for a 1 Gbps part ??? True: we are not an ASIC/ASSP. That is the one area where they win (they can make these specs as tight as they please). But guess what? We are growing, increasing sales, and ASICs are not. Our real competition now is no longer other FPGA companies; it is the ASIC/ASSP providers. We can supply features and circuits on technologies they can't (yet). Who has 10 Gbs transceivers? Who has the lowest power 405PPC? Who has the lowest power/highest performance DSP48 blocks for DSP applications? We do, they don't. > > As to why that matters: a HyperTransport test probe attempting > to monitor the input link to the FPGA can't function properly > because Cin reflections off the FPGA would prevent the probe from > properly clocking the data at the mid T-line probe sampling point. I claim in a real system, with a compliant transmitter, there will be sufficient return loss matching to make the eye visible, and useful. But, I agree, that in some cases, what you see is not what you get. That can happen with a simple single ended input pin, and is definitely true about 1Gbs, where observing it, breaks it (often). I think that there is a whole class of people out there who have to see it to believe it. OK. But, they should get used to the fact that none of the test equipment is really fast enough to show them what they want to see. And it is only getting worse. > > There are ways around this, but life would be easier if Xilinx > actually bothered to meet the spec in the first place. Already explained why we can't do that: 35 IO standards in one pin has to make some compromises. > > Lacking that, proper documentation of your part's shortcomings, > and how and when to work around them, would be appropriate. We got all that. That is what the user's guide is for. That is what the datasheet is for. Should we place a billboard on 101 South that states the IOB pin capacitance is ~ 12pF? It is already in the datasheet. So is the MGT, PPC, DSP48, etc. What do you think we should spend time on? > > > Brian > > > [1] Speaking of those unable to perform the SI engineering that is > required of them : when might we expect publication of characterized > static DCI power and DCI impedance modulation limits for the five year > old Virtex2 FPGA family ? I think all this is now covered between data sheets, user's guides, and technical answers on our website. Let me know if there is something missing between those three resources. Generally speaking, if we don't specify it, then you are on your own to use it there. For example, if you chose to set the resistance to 100 ohms, to match a 100 ohm single ended line, we are not going to claim we meet any standard (there isn't any), and we aren't going to spend time characterizing all the silicon for it. I believe we state the range of the resistance from 40 ohms to 150 ohms, but when you use it at anything other than 50 ohms, you are required to check it out (I would run the spice simulations -- you may request impedances other than 50 ohms for the spice models of DCI, 40, 50, 68, and 75 are the ones we have if I recall correctly), as that is not any one of the 35 IO standards that we designed the IOB to support. A small change, such as using the DCI at 68 ohms instead of 50 ohms is used by quite a few (to save power). You can characterize it if you need to, and if you feel there is a benefit you can derive, but unusual usage of a feature in an area it was not intended to be used (not specified), is not guaranteed.Article: 84094
How to turn off auto bufg insertion in ISE 7.1 ??? when using *schematic* entry?? It's messing up my design. Anyone?Article: 84095
Benjamin Todd wrote: > To be quite honest I wouldn't waste time or money buying IP. > It's very easy to write UARTs - Go to the Xilinx website, and search... > > You could start this way, and use something as easy as HyperTerminal to > communicate with the board. > I'm doing a Spartan-III project with a UART connection to the PC, and I'm using Ken Chapman's UART core. It's a freebie in with the equally free Picoblaze core, and operation out to 115200 baud has been problem free and generally spiffy. I think there's a UART over at opencores.com too, but I know nothing about it. Cravat emptor*. *Let the buyer wear a silly excuse for a necktie. -- RobArticle: 84096
Fred wrote: > "AVG" <hse00045@fh-hagenberg.at> wrote in message > news:d7206b46299a6e210db5611bcf733a3d@localhost.talkaboutelectronicequipment.com... > >>Hi, >> >>I am using Oregano's mc8051 IP Core on a Altera Cyclone II FPGA (EP2C35) >>Board with great success. >>I have synthesized this core many times with Quartus (several procets). >>The occupied area is about 12%, fmax is about 20 MHz. >> > For my own interest I've tried fitting the core to a Xylinx device, an > XC3S200-PQ208 and it won't fit: > > Number of Slice Flip Flops: 566 out of 3,840 14% > Number of 4 input LUTs: 4,562 out of 3,840 118% (OVERMAPPED) > Logic Distribution: > Number of occupied Slices: 2,356 out of 1,920 > 122% > (OVERMAPPED) > Number of Slices containing only related logic: 2,284 out of 2,356 > 96% > Number of Slices containing unrelated logic: 72 out of 2,356 > 3% > *See NOTES below for an explanation of the effects of unrelated logic > Total Number 4 input LUTs: 4,669 out of 3,840 121% (OVERMAPPED) > Number used as logic: 4,562 > Number used as a route-thru: 107 > Number of bonded IOBs: 156 out of 141 110% (OVERMAPPED) > IOB Flip Flops: 47 > Number of MULT18X18s: 1 out of 12 8% > Number of GCLKs: 1 out of 8 12% > > It may be ISE but I can't seem to make a symbol either? It's not ISE, it's your selection of a Spartan-III part. You can't compare a EP2C35 device (33,216 LUTs/475 IOs) to a 3S200-PQ208 (3,840 LUTs/141 IOS). The part that you selected was 10% the size of the other part!!! The OP said the EP2C35 was about 12% used which is about 4K LUTs. This isn't too far off from your report. Select a larger Spartan-III part with more IOs (at least 156 per your report) and it should go through without a problem. EdArticle: 84097
Thanks berty, but I already did mention > Anybody having this problem, and know what I can do (appart from specifying ports by name)? That's what I'm doing now, but it's just that I'm following a tutorial and re-typing the examples, but the examples mostly use un-named parameters. I guess though that it could be a good habit to start passing parameters by name from the start of the learning process...Article: 84098
You can define a simple design, like <<press a button, turn on a LED>>. Verilog example module top(led, button); output led; input button; assign led = button; endmodule Then, you need to specify a constraint file, telling the P&R where what FPGA pins to use for 'button' and for 'led'. This is a very basic.Article: 84099
in your code, the value of synch_found is never reset after it has found the first synchronisation byte... Ben "Weddick" <weddick@comcast.net> wrote in message news:I_adnfHl47DWIR_fRVn-3A@comcast.com... >I have what I thought was a simple problem. I need to count the number of >clocks to determine when to take data out of the shift register. The data >is a continuous stream and I want to be able to count every 8 bits. I >thought I could use a 3 bit counter but can't seem to get the code correct. >I then went to a 4 bit counter, and while it works I am not sure if the >code is the best way. Any ideas? > > Thanks, > Joel > > > >
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Compare FPGA features and resources
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