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Hi Ben, Some 'real world' comments: I think it's stuck in human nature to compare, therefore 'mine is bigger than yours' has nothing to do with programmable logic at all. Have you ever seen an customer that needs 'all' the features even if this feature happens to be 'the biggest device'? Of course there will be some customers spending 1000's of dollars on research projects, but I guess your boss will like it more that you spend your time with the customers that need lot's of FPGA's! Any idea what percentage of the revenue these high gate count devices represent? I guess something like 1%. So spending lot's of R&D money on those devices isn't worth it. That's reality I'm afraid. Luc On Thu, 12 May 2005 20:53:29 GMT, Ben Twijnstra <btwijnstra@gmail.com> wrote: >Hi Peter, > >> It is so easy to ridicule this puerile bragging contest and its >> Freudian fix on one specific aspect, while ignoring far more important >> features. Unfortunately, some poor innocent person might actually get >> fooled by it. Too bad! > >Yep. In The Netherlands we call it a far-peeing contest. > >However, I have been subjected to a customer who made a vendor decision for >a low-cost device based on the fact that this vendor at the time also >happened to have the largest high-end FPGA in the market. I kid you not. >Took me two days to regain my confidence in humanity. If this happens in a >postage-size country like The Netherlands, it must happen in other places - >we're not _that_ much more unreasonable than other countries... > >> For a more entertaining story, click on >> http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm > >Wonderful! Thanks for the link! > >BenArticle: 84176
I recently wasted several hours trying to get a project from ISE 6.1i to *load* correctly in ISE 6.3.03i. I always seem to loose more time to the tools (either due to bugs or the tools being downright awfull compared to a software compilation toolflow for providing easily usefull data etc.) than I do to reaching timing requirements, or adapting a design to live with a lower clock. So yes, in my view I'm more interested in toolflows lately, although with only to fish in the pond hardware wise, and in both cases the hardware and tools being intematly linked (at lower levels, and at higher levels for those on restricted budgets), their is sadly little choice :-( An interesting asside, I've been getting involved with work in using FPGAs in high performance computing, coming from a background in both. Meeting people coming from a background that is software/HPC and no FPGAs, they tend to be appauled by the FPGA software flows. I'm reasonably convinced that a 'proper' implementation of the modular design stuff from Xilinx (i.e. not relying on using the disapearing tristate bus emulation from the Virtex architecture) would make the tools more usable, not least in reducing raw hardware and time requirements for big PARs. Mind you it could be argued that the reason I have the luxury to be pissed at the tools is because the hardware is now at a state where it does what I want most of the time :-) --- cds Nicholas Weaver (nweaver@soda.csua.berkeley.edu) wrote: : Warning: Ranty, opinionated (and quite probably wrong): : Stupid question on the X vs A urination (in a hurricane) contest: : How much does performance really matter? : First, how many FPGA tasks are not defined by an external clock or : clocks? If you are doing GigE, your clock is 125 MHz (8 bit path) or : 62.5 MHz (16 bit path). The PCI-X bus is 33/66/99/133 MHz. : Second, how many designs have single-cycle latency requirements? PCI : does, but your part either can or can't make the PCI spec with the : provided IP core (so thats a pass/fail metric, not a performance : metric). : If the task is latency bound overall, then performance matters. But : otherwise, just add more registers & pipeline more finely. : Thus I personally wonder whether the primary focus of the pissin match : should be mostly about tools (both the vendor tools and support for : third party tools, especially easy floorplanning, datapath aware : placement, & retiming), density ($/LE), and features (Brand X has a : big lead here), rather than who's lut is 10% faster on what functions, : and who's interconnect might be slightly faster on some designs and : slower on others. : -- : Nicholas C. Weaver. to reply email to "nweaver" at the domain : icsi.berkeley.eduArticle: 84177
Frank,
you have two options when you compile your application to reduce the
address range it spans ("its size"):
- write your own linker script. In that linker script map the .boot and
the .boot0 sections with the .text sections to the location of your
external memory
- use "-Wl,--section-start,.boot0=<address>" as a compiler option to map
the .boot0 section to your desired location. For example in XPS set the
start address of your application to 0x10 and use
"-Wl,--section-start,.boot0=0" if your external memory is mapped to
address zero.
- Peter
Frank van Eijkelenburg wrote:
> Hi,
>
> I have made a bootloader which runs from BRAM on a PPC. Now I want to
> download an application into external RAM and execute it. If I build my
> application and convert the .elf file into a binary file, the result is a 2
> GB binairy file. This is because my external RAM starts at 0x80000000 and
> the startup up code contains a section called boot0, which is laid at
> 0xFFFFFFDC.
>
> AFAIK, the boot0 section contains a jump to my application (0x80000000).
> But, I think, the boot0 section is not needed. At startup the boot0 section
> (in BRAM) contains a jump to my bootloader program and I don't want to
> overwrite it. How can I create a .elf file (or .bin file) without the boot0
> section (but with initialisation/startup code)? In that case I can simply
> download my application through the bootloader into external RAM and jump to
> it.
>
> TIA,
> Frank
>
>
Article: 84178
Use "-Wl,--section-start,.boot0=0x80000000" and start address 0x80000010
for your environment.
A third option: strip the .boot and .boot0 sections from the ELF file as
they provide the means to jump anywhere in the 4GB address range,
something you do not need in your case because you have your own bootloader.
Example:
$ powerpc-eabi-objcopy -R .boot -R .boot0 original.elf new.elf
- Peter
Peter Ryser wrote:
> Frank,
>
> you have two options when you compile your application to reduce the
> address range it spans ("its size"):
> - write your own linker script. In that linker script map the .boot and
> the .boot0 sections with the .text sections to the location of your
> external memory
> - use "-Wl,--section-start,.boot0=<address>" as a compiler option to map
> the .boot0 section to your desired location. For example in XPS set the
> start address of your application to 0x10 and use
> "-Wl,--section-start,.boot0=0" if your external memory is mapped to
> address zero.
>
> - Peter
>
>
> Frank van Eijkelenburg wrote:
>
>> Hi,
>>
>> I have made a bootloader which runs from BRAM on a PPC. Now I want to
>> download an application into external RAM and execute it. If I build
>> my application and convert the .elf file into a binary file, the
>> result is a 2 GB binairy file. This is because my external RAM starts
>> at 0x80000000 and the startup up code contains a section called boot0,
>> which is laid at 0xFFFFFFDC.
>>
>> AFAIK, the boot0 section contains a jump to my application
>> (0x80000000). But, I think, the boot0 section is not needed. At
>> startup the boot0 section (in BRAM) contains a jump to my bootloader
>> program and I don't want to overwrite it. How can I create a .elf file
>> (or .bin file) without the boot0 section (but with
>> initialisation/startup code)? In that case I can simply download my
>> application through the bootloader into external RAM and jump to it.
>>
>> TIA,
>> Frank
>>
>
Article: 84179Hi anyone has made it own microblaze soc (eg not using ML401 derivate) where PLB is connected to microblaze OPB over bridge and some peripherals live on the PLB bus? I am struggling with this and can find the problem, for testing I just connected PLB GPIO, it seems to be kind of visible over OPB2PLB bridge, but there is defenetly any writes working :( This can be done and is used in ML401 ref design, but there seem to be some 'special gotchas' that one has to know to make it work, so if anyone had some problem with similar design and has some hints I would be extremly thankful anttiArticle: 84180
i guess u won't be able to simulate inout signals....simulator won't give error but the signal will be missingArticle: 84181
Some of our working designs under 6.2 fail to even route under 7.1, although I guess that is preferable to having an implementation fail, perhaps in subtle ways. Our FAE advised us to wait for the next ISE 7.1 service pack which should be out in less than a month. I was hoping as the EDK tools matured, upgrades would be less painful, but apparently not.Article: 84182
"joe4702" <joe4702@hotmail.com> schrieb im Newsbeitrag news:1116013046.366443.14330@o13g2000cwo.googlegroups.com... > Some of our working designs under 6.2 fail to even route under 7.1, > although I guess that is preferable to having an implementation fail, > perhaps in subtle ways. > > Our FAE advised us to wait for the next ISE 7.1 service pack which > should be out in less than a month. > > I was hoping as the EDK tools matured, upgrades would be less painful, > but apparently not. > NO, they are not. That's pitty as it really takes a REAL LOT OF time every time wasted when something is broken after tools update. AnttiArticle: 84183
hello, there seems to be a plethora of textbooks on VHDL/Verilog available. But what about floorplanning ? Are there any resources (print/Web) available ? lukaszArticle: 84184
Eric, thanks very much for your answer. However, the problem went away when I upgraded from 6.3 to 7.1. Now the fake buffers are gone without any further action. Cheers Gunter "Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:d5r8uh$k4u3@cliff.xsj.xilinx.com... > > Hi, > > I think the way ECS works is that it writes out a netlist of your > schematic > in an HDL using instantiated primitives from the UNISIM library. Then, > the > design is actually synthesized by XST before it heads into MAP and PAR. > > By default, XST does not "optimize" instantiated primitives. You can > override this option, I think it is called "optimize_primitives" and you'd > set it to "yes". Consult the online help system to find the specific name > of the option. If you have trouble finding it, file a case with the > Xilinx > customer support team and they will help you find it. > > Eric > > "Gunter Knittel" <knittel@gris.uni-tuebingen.de> wrote in message > news:d5kgh4$m6u$1@newsserv.zdv.uni-tuebingen.de... >> Hi Folks, >> >> I'm using ECS (yes, I know...). Now, ECS forces one to insert >> a buffer whenever one wants to rename a bus. I have done so. >> I was stunned to see that buffer appear in the routed design - >> as a LUT with D=A1! >> I'm sure I can get rid of it using the proper XST or PAR options, >> but I don't know which. >> Can anybody help? >> >> Thanks a lot >> Gunter >> >> > >Article: 84185
ALuPin@web.de wrote: > ... > t_Bidir_data <= t_tx_data when t_drive_tx_data='1' else (others => > 'Z'); > t_rx_data <= t_Bidir_data when t_drive_tx_data='0' else (others => > '0'); > ... > > My question : > In the port map > Bidir_data => t_Bidir_data > > an INOUT port of the unit under test is connected to a signal within > the testbench. > > Will the Tristate Description shown work ? (Which "direction does > "t_Bidir_data" have ?) > The testbench "t_tx_data" generation takes over the tristate bus master > role. > Did you just try it? That would be the easy thing to do. Sure, it will work. There is normally no reason to tristate the receive data. Just do t_rx_data <= t_Bidir_data;Article: 84186
Hi, I'm trying hard to speed-optimize an arithmetic function on a VII 4000 - 4 device, using ISE 7.1. I have minimized the logic down to a few layers of 4-input LUTs. However, the routed design spends much more time on the wire than in the LUT. In particular, communication from one slice to the next in the same CLB through the Switch Matrix can be slow, sometimes in the order of 1ns. So my question is: is there no fast private communication between slices in the same CLB (other than shift and carry)? Is there any documentation available about the performance of the Switch Matrix, and how I should arrange the logic such that fastest interconnects can be made? Thanks a lot GunterArticle: 84187
Thanks you all. This has been very helpful.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 84188Hi, I have been using Altera Quartus II v4.2 SP1 for quite a long time. Recently, I have a problem that the fiiter change the logic equation compare to the synthesis. 1. I wonder why the fitter need to change the post-synthesis logic equation during fitter stage. More interesting is that the changes make my synchronous register behave asynchronously. Post-synthesis logic equation : ZD1_RD_PTR[1] = DFFEAS(ZD1_RD_PTR[0], H1_rd_fifo_rd_clk, !PIN_RSTN, , , , , , ); Post-fitter logic equation : ZD1_RD_PTR[1] = DFFEAS( , GLOBAL(H1L39), !PIN_RSTN, , , ZD1_RD_PTR[0], , , VCC); Obviously, the behaviour will totally different! 2. Can someone tell me how to turn off the fitter optimization? RobertArticle: 84189
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:d62vs6$5hm$03$1@news.t-online.com... > "joe4702" <joe4702@hotmail.com> schrieb im Newsbeitrag > news:1116013046.366443.14330@o13g2000cwo.googlegroups.com... > > Some of our working designs under 6.2 fail to even route under 7.1, > > although I guess that is preferable to having an implementation fail, > > perhaps in subtle ways. > > > > Our FAE advised us to wait for the next ISE 7.1 service pack which > > should be out in less than a month. > > > > I was hoping as the EDK tools matured, upgrades would be less painful, > > but apparently not. > > > NO, they are not. > That's pitty as it really takes a REAL LOT OF time every time wasted when > something is broken after tools update. OK problem, old solution. Never change a running system. Regards FalkArticle: 84190
Michael, As of ISE 7.1 Data2MEM does support 18-bit datawidths. You need to add a BMM and MEM file to the top level of your ISE project. The BMM should have syntax to describe the instantiation of the BlockRAM you instantiated. An example BMM file is: //////////////////////////////////////////////////////////////////////// ADDRESS_SPACE picoblaze1 RAMB18 INDEX_ADDRESSING [0x00000000:0x000003FF] BUS_BLOCK top/picoblaze1/myram [17:0]; END_BUS_BLOCK; END_ADDRESS_SPACE; //////////////////////////////////////////////////////////////////////// In the above BMM file example the name 'picoblaze1' could be anything. Further the label 'top/picoblaze1/myram' is the instantiation name of the blockRAM with complete hierarchy. To obtain the instantiation name of the blockRAM you could run the tools one and then open up FPGA Editor to see the complete instantiation name of the blockRAM. The second file you have to add to the Project Navigator project is a MEM file. A MEM file is essentially a HEX file (output from KCPSM assembler) with '@0' as the first line. Currently, you must create the MEM file by hand from the HEX file. Every time the time stamp of the MEM file changes then the 'Generate Bitstream' task becomes unchecked in Project Navigator. All you have to do is is Run 'Generate Bitsteam' and the a bitstream will be generated with the updated values without running through Synthesis/Translate/MAP/PAR. Cheers, Shalin- Michael Dreschmann wrote: > Hello, > > in my actual design im using a few picoblazes. Now I wonder if it is > possible to update the code in the bitstream without a new > implementation run like it is possible with the microcblaze. I checked > data2bram but it allows only an update of 16 Bit wide Brams, not the > necessary 18 Bit. > > Thanks, > Michael -- ------------------------------ Shalin Sheth Embedded Applications Engineer General Products Division Spartan-3 Generation FPGAs http://www.xilinx.com/spartan3 http://www.xilinx.com/spartan3e ------------------------------Article: 84191
Click on the Assignment Editor->Timing button which is in the upper right corner. This will show only timing related assignment names in the Assignment Name field in the table below. You will have to fill in the From and To fields and the value needed. You can also use the All button in the upper right corner of the Assignment Editor to obtain a list of every Assignment Name possible which will include these Timing Assignment names also. Hope this helps. - Subroto Datta Altera Corp. <ALuPin@web.de> wrote in message news:1115965745.611489.161920@g44g2000cwa.googlegroups.com... Where can I find this assignment type "Input max delay / input min delay" in the Assignment Editor? Rgds AndréArticle: 84192
How would I infer the fifo from the code? Do you mean I should write my own fifo or create a behavioral model of Altera's FIFO? While this may be the way to go, but last time I tried some thing like this, I noticed that the FPGA vendor had a much better implementation of the fifo. -sanjayArticle: 84193
I've had a similar experience with a V4sx55 design. Trying to
synthesize from RTL code and achieve high performance takes a lot of
"pushing on a rope", is frequently broken by gratuitous changes in the
synthesis algorithm from version to version, and then often won't meet
timing without a heroic placement effort. doing structural
instantiation gets me the performance in less overall time, but at the
price of a design that is not very portable.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84194What do you really want to simulate? Generating the FULL signal after the right amount of writes is really a trivial decoding job. Getting back out of "FULL" is tricky, and - I claim- cannot be simulated exhaustively, since there is an infinite (truly infinite) number of phase relationships between the write and the read clock ( if they are asynchronous). If write and read are synchronous, the whole FIFO design is a trivial state machine. Peter Alfke (Xilinx, but posting from home). fpgabuilder wrote: > How would I infer the fifo from the code? Do you mean I should write > my own fifo or create a behavioral model of Altera's FIFO? While this > may be the way to go, but last time I tried some thing like this, I > noticed that the FPGA vendor had a much better implementation of the > fifo. > > -sanjayArticle: 84195
Yes, with ISE 6.x one would add a BUFG(x) symbol to explicitly insert a bufg in the schematic. I want to avoid placing an attribute BUFFER_TYPE=none on a LOT of nets that XST thinks should be a clock net; If that's even possible since it's not listed as a constraint under schematic flow. Anyone know of a global way to turn off auto bufg insertion? "Gabor" <gabor@alacron.com> wrote in message news:1116005053.961418.251210@o13g2000cwo.googlegroups.com... >W A wrote: >> How to turn off auto bufg insertion in ISE 7.1 ??? when using > *schematic* >> entry?? It's messing up my design. >> >> Anyone? > > In older versions the ECS schematic would not insert these, but for > HDL you would attach a BUFFER_TYPE attribute to the net. Check out > the constraints guide to see how. >Article: 84196
ma wrote:
>Hello,
>
> I want to start learning VHDL (or VERILOG) and FPGA programming. I have
>ISE 6.1 and some FPGA board. Where is the best place to start? I am an
>experienced C/C++ programmer.
>
>
>
Start by forgetting everything you know about C. This is hardware
design. Envision the circuit you want to create, and then write the HDL
to produce that circuit. Treating it like software is bound to cause
you no end of frustration.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84197
praveen.kantharajapura@gmail.com wrote:
>Hi peter,
>
>So what you mean to say is in simple dual port memories one port is
>restricted only for write, and the other one only for read.
>
>I read in ALTERA cyclone FPGA's that there memory blocks can be used as
>
>1)Simple dual port memory.
>2)True dual port memory.
>3)FIFO buffers.
>Is it the same in XILINX.
>
>But according to your explanation Simple dual port memory is nothing
>but a FIFO, so why have they explicitly mentioned as FIFO buffers.
>
>Please clarify on the 3 types of memory usages.
>
>Thanks in advance,
>Praveen
>
>
>
simple dual port allows random access to both ports, with the
restriction that one port is read only , one is write only with
independent addresses for each port.. It has memory address inputs for
each port. A FIFO buffer typically includes read and write pointers and
flag logic so that the external interface does not include address
inputs. True dual port allows both read and write from both memory
ports. earlier Altera devices (10K and 20K) had simple dual port
memories, while Xilinx FPGAs of the same vintage had true dual port.
Altera's current devices have true dual port memories.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 84198
Uwe Bonnes wrote:
> Geogle <georgevarughese@indiatimes.com> wrote:
> > Hi,
>
> > Does this "Free ISE WebPACK 7.1i" for linux work
> > with any distribution other than Red Hat Enterprise Linux 3 ?
> > I tried to install this under Fedora Core 3 / Debian and
> > installation didn't succeed. Looks like the installer is
> > linked against libwiclient.so, libcommdlg50.so ....
> > libodbc50.so etc, which are not there on the system.
>
> > Does anyone know which package provides these ?
>
> The webpac installer is in charge to install them. They are found in
> ../bin/lin
Thanks, they are in the BIN area!
When I tried to install the software, I got the following message:
( running setup from the extracted files/
and
sh Webpack*..sh yielded the same
result. )
Wind/U X-toolkit Error: ", 24Wind/U X-toolkit Error:
wuDisplay: Can\'t open display\n", 30wuDisplay: Can't open display
Apparently:
connect(4, {sa_family=AF_INET, sin_port=htons(6000),
sin_addr=inet_addr("127.0.0.1")}, 16) = -1 ECONNREFUSED (Connection
refused)
is the message from strace on xilsetup.
I was running X from display manager.
Then I tried starting it manually and surprisingly the installation gui
did show
up.
It did proceed to almost the final step and
I got a message:
path/xilinx/installer/platform/lin/bin/lin
Wind/U Error (294): Unable to install Wind/U ini file
(/path/xilinx/installer/platform/lin/data/WindU).
See the Wind/U manual for more details on the ".WindU" file and the
"WINDU"
environment variable.
Error:cannot run process -
/path/Webpack/.xinstall/install_driver_installscript
insmod: error inserting '/lib/modules/misc/windrvr6.o': -1 Invalid
module formatinsmod: error inserting '/lib/modules/misc/windrvr6.o': -1
Invalid module format
But I succeeded in running ise, and got
one example project "implemented". Haven't gone in to details though.
I get another message too :
./ise
OLE API Function OleInitialize is not currently implemented. Further
warnings will be suppressed
Hope you have some information to share regarding this.
Thanks,
George
Article: 84199If your team is using X language and not Y, then it will be prudent to follow. The word programming can rub some HW guys off the wrong way, it can only safely be used to infer downloading the bit file to FPGA or PROM. Most HW guys design or develop or engineer HW, those that "program" are coming from the SW side with all that baggage of sequential thinking rather than parallel. Since you have a HW background, I'd suggest the Doug Smith book, which I suggested a thousand times already., google douglas smith verilog vhdl fpga asic It covers X/Y languages examples for FPGA and ASIC, it is not a HW teaching book, it assume you know basics. it gives schematics, hdl for X/Y and synthesized output. Also Palnitker is recomended, initially Verilog, I think its been VHDLed. Why didn't you ask your HW co workers, most EEs would be more than willing to help a co worker get interested in what they are doing. You may even graduate into the team after brushing up. I had the same issue, when I did the deep guts of the HW ASIC/FPGA and some interface to their SW, it took a year before I could convince the driver HW-SW guy to do his own damn HW interface that would work with his own damn SW. Eventually he did and the results were far better for all concerned. The problem I always find is not enough people who know both sides and can think laterally enough to design the right HW interface to SW. Usually if the interface between HW-SW is done by HW guy with no clue about SW stack and the SW guys don't even know how to describe FSMs then you get pretty poor results. look like you could help out on both sides good luck johnjakson at usa dot com
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