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Methi, CLKIN of the DCM is 13.5 MHz from a clock input. Do not connect anything to CLKFB, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X_b, or CLKDV. Use the CLKFX or CLKFX_b outputs with M=2, D=1. This selects only the use of the synthesizer, and the low frequency restriction becomes as low as 1 MHz for CLKIN. CLKFX must still be greater than 24 MHz, which is OK, because 13.5 X 2 = 27 MHz. Austin methi wrote: > Hi Gabor, > > Thanks fore replying. > > "For FX-only you can go down to 1.5 MHz IIRC." > > How do I do this? > > I mean, how do I make use of the DCM core in Xilinx to take an input > clk of 13.5mhz... > > Thanks, > Methi > > Gabor wrote: > >>methi wrote: >> >>>Hi, >>> >>>I need to double an input clk of 13.5mhz to 27 mhz...but the DCM core >>>in xilinx can take frequencies from 24 Mhz and up only... >> >>Only true if you use DLL outputs. For FX-only you can go down >>to 1.5 MHz IIRC. >> >> >>>On going through some of the posts, this is the idea that I have come >>>across: >>> >>>Give my input clk to one input of the XOR gate. >>> >>>Delay my input clk with a series of inverters and give it as the second >>>input of the XOR gate.. >>> >>>Would this work? >> >>Maybe. Is your input duty cycle 50%? Is it still 50% after the IBUF >>inside the part? Do you need a specific duty cycle on the doubled >>clock? Can you tolerate jitter on the doubled clock? >> >>If your input has exactly 50% duty cycle you can create a relatively >>low-jitter doubled clock and it could be squared off by adjusting the >>delay to one leg of the XOR, or if the jitter is low enough by feeding >>through the DCM. >> >> >>>Thank you, >>> >>>Methi > >Article: 85201
Hello, I am new to fpga design and am trying to use Webpack to generate a bit-file from an edif file preconverted by another synthesiser. I created a project with EDIF as the top-level module, and added the relevant .edf and .ncf files. I then highlighted the configured EDIF file in the "Sources in Project" window, and tried to run "Implement Design". I get an 'NGDBuild Failed' error: ERROR:Portability:90 - Command line error: Argument "Files\Celoxica\RC100\Examples\Menu\EDIF\Menu.edf" has an invalid extension. The valid extension is ".ngd". If your file name has more than one "." in it you must explicitly enter the full file name with its extension. But there is a .ngd file in the same directory as the .edf file. Am I missing a step somewhere? Any help would be greatly appreciated. MeesArticle: 85202
look for KICAD (totally free) Stef MientkiArticle: 85203
> > My opinion is that you ask for an awful lot for free. No just 5 years too early ;-) StefArticle: 85204
"methi" <gmethi@gmail.com> wrote in message news:1118088247.690449.312480@g43g2000cwa.googlegroups.com... > Hi Chuck, > > Thanks for replying.. > > Did I get this right: > > Take my 13.5 and give it as one input of an XOR Yes > > Take the output of the XOR1 and give it as input clk to a D-FF1 Yes > > Take the output of the D-FF1 and give it as input to an inverter. Yes > > Take the output of the inverter and give it as input clk to another > D-FF2 No, take it to the D input of the DFF1 - there is only one XOR and one DFF in design. > > and also as the second input of the XOR1 Yes > > And the output of the XOR1 gives 27mhz Yes, but it does rely on your 13.5MHz input being 50% duty cycle. The output will be a positive pulse produced on each edge of input, the pulse width being a function of the prop delays on XOR/DFF and inverter. > > Am I understanding this right? > I hope the above makes it clearer - a picture is worth a thousand words!!!! Ciao for now ChuckArticle: 85205
I'm not trying to "milk the system" I'm just trying to get list of free programs and there limitaions, so I can choose which one I should learn how to use. I'm using these programs for a hobby non-profit project. EricArticle: 85206
Eric wrote: > What is the best FREE Schematic & PCB Layout software available that > will run on Windoze XP? Maybe it is time for you to install linux. gEDA and PCB are free on linux. They are very good. vax, 9000Article: 85207
Frederic, We have plenty of XC3S200, but how can we halp you when you give neither your name nor your company affiliation. Being "pissed off" is no good when you give us no chance to help you. Peter Alfke, XilinxArticle: 85208
This thread is going around in circles. We know the average frequency is no problem. We also know that jitter is unavoidable, and tends to camouflage the resolution. We do not know why the whole effort is necessary... "Why" is a bigger question than "How" Peter AlfkeArticle: 85209
Hi Austin and Chuck, Thankyou so much for helping me out... I am goin to try using the DCM core as well the XOR circuitry( by the way, I found the diagram in one of the google posts) Thank you so much for your time.. I really appreciate all the help.. Methi Chuck Bodgers wrote: > "methi" <gmethi@gmail.com> wrote in message > news:1118088247.690449.312480@g43g2000cwa.googlegroups.com... > > Hi Chuck, > > > > Thanks for replying.. > > > > Did I get this right: > > > > Take my 13.5 and give it as one input of an XOR > > Yes > > > > > Take the output of the XOR1 and give it as input clk to a D-FF1 > > Yes > > > > > Take the output of the D-FF1 and give it as input to an inverter. > > Yes > > > > > Take the output of the inverter and give it as input clk to another > > D-FF2 > > No, take it to the D input of the DFF1 - there is only one XOR and one DFF > in design. > > > > > and also as the second input of the XOR1 > > Yes > > > > > And the output of the XOR1 gives 27mhz > > Yes, but it does rely on your 13.5MHz input being 50% duty cycle. The output > will be a positive pulse produced on each edge of input, the pulse width > being a function of the prop delays on XOR/DFF and inverter. > > > > > Am I understanding this right? > > > I hope the above makes it clearer - a picture is worth a thousand words!!!! > > Ciao for now > > ChuckArticle: 85210
sorry for the trouble. i guess its because of my options. try it now. thanksArticle: 85211
"Joe" <joe.ricky@gmail.com> wrote in message news:1118081603.893628.136300@g49g2000cwa.googlegroups.com... > What i would like to know is how to interface USB1.1 which is > having non-AHB interfacing signals, which is working at fullspeed > (12Mhz) with ARM processor which is operating at 25 MHz usign AMBA 2.0 > specification. > > --Joe > > > > Mike Lewis wrote: >> dude what information are u looking for? The AMBA spec is readily >> available >> from ARM website. Whose USB core are u trying to implement? If u are >> asking >> for doumenation for that ... would you not have received that with the IP >> .. >> even >> if it was a long time ago. >> >> Does the USB core have an AMBA interface? Or is the interface something >> else >> that >> you want to modify to connect to an AMBA bus? What is the interface? >> >> We need more detail if we are going to help you. >> >> Mike > how can I possibly answer that without knowing what interface you do have? What are the non-AHB signals? I'm a good designer but not that good! MikeArticle: 85212
Eric wrote: >What is the best FREE Schematic & PCB Layout software available that >will run on Windoze XP? > >I've looked at PCB123.com and Expresspcb.com and they have pretty good >programs available. Unfortunately if I use either one I'm stuck getting >the prototypes through them. (Because they won't output Gerbers) > >I've also looked at Eagle Layout at cadsoft.de, but the size limitation >of 100 x 80mm on the free version is a negative. It would work for my >current project. > >I'm just curious at what other people's opinions are. http://bach.ece.jhu.edu/~haceaton/pcb/ http://pcb.sourceforge.net/Article: 85213
Jedi, Sorry I did not see this sooner. I just tried a test with Nios II 5.0 of the timer peripheral -- starting with a 10ms period as you indicated, and tried an experiment to modify the timer period as well as take snap-shots based on pressing/releasing a button on my dev board. It all worked fine. Send me an email if this is still a problem and I'll send you the source code I'm using for the test! One scenario that comes to mind that may have caused this is that if your code is not setup to use I/O instructions to peripherals (recommended for all Nios II software), and you're using the data cache: there have been modifications to the Nios II data cache in 5.0 -- whether you're using the data cache or not its best to ensure that you're doing an "I/O" read/write to external peripherals rather than simple load/store (as you'd get with a regular pointer dereference). This stuff is described in the Nios II Software Developer's manual. Jesse Kempa Altera jkempa -at- altera -dot- comArticle: 85214
kempaj@yahoo.com wrote: > Jedi, > > Sorry I did not see this sooner. I just tried a test with Nios II 5.0 > of the timer peripheral -- starting with a 10ms period as you > indicated, and tried an experiment to modify the timer period as well > as take snap-shots based on pressing/releasing a button on my dev > board. It all worked fine. Send me an email if this is still a problem > and I'll send you the source code I'm using for the test! > > One scenario that comes to mind that may have caused this is that if > your code is not setup to use I/O instructions to peripherals > (recommended for all Nios II software), and you're using the data > cache: there have been modifications to the Nios II data cache in 5.0 > -- whether you're using the data cache or not its best to ensure that > you're doing an "I/O" read/write to external peripherals rather than > simple load/store (as you'd get with a regular pointer dereference). > This stuff is described in the Nios II Software Developer's manual. > Everything working fine with periphals (o; Wasn't the cores but the NIOS2 toolchain producing wrong code on AMD64 Linux platforms... Compiling everything on OSX now (o: best regards rickArticle: 85215
Hello Chuck, Gabor and Austin.. I used both the methods...and have a 27 Mhz for both of these methods.. Thankyou very much for helping me out.. I appreciate it very much, Methi methi wrote: > Hi Austin and Chuck, > > Thankyou so much for helping me out... > > I am goin to try using the DCM core > > as well the XOR circuitry( by the way, I found the diagram in one of > the google posts) > > Thank you so much for your time.. > > I really appreciate all the help.. > > Methi > > > > Chuck Bodgers wrote: > > "methi" <gmethi@gmail.com> wrote in message > > news:1118088247.690449.312480@g43g2000cwa.googlegroups.com... > > > Hi Chuck, > > > > > > Thanks for replying.. > > > > > > Did I get this right: > > > > > > Take my 13.5 and give it as one input of an XOR > > > > Yes > > > > > > > > Take the output of the XOR1 and give it as input clk to a D-FF1 > > > > Yes > > > > > > > > Take the output of the D-FF1 and give it as input to an inverter. > > > > Yes > > > > > > > > Take the output of the inverter and give it as input clk to another > > > D-FF2 > > > > No, take it to the D input of the DFF1 - there is only one XOR and one DFF > > in design. > > > > > > > > and also as the second input of the XOR1 > > > > Yes > > > > > > > > And the output of the XOR1 gives 27mhz > > > > Yes, but it does rely on your 13.5MHz input being 50% duty cycle. The output > > will be a positive pulse produced on each edge of input, the pulse width > > being a function of the prop delays on XOR/DFF and inverter. > > > > > > > > Am I understanding this right? > > > > > I hope the above makes it clearer - a picture is worth a thousand words!!!! > > > > Ciao for now > > > > ChuckArticle: 85216
Hi, In Virtex-4 silicon, the transceivers exist in pairs and they share some common circuits (such as the dynamic reconfiguration port and clocking circuits). It is perfectly legal to combine two one-lane designs (using two GT11) into a single tile as long as you follow the rules in the user guide. The architecture wizard is fairly generic, and when writing out code, will write GT11 in pairs. If you select a one-lane configuration, you will get one GT11 that is actively used, and another GT11 that is just along for the ride. The architecture wizard doesn't know enough about your specific design requirements to determine if transceivers can be shared or not. However, you can easily take the architecture wizard output and create a shared tile by copy/paste as long as you are not violating the rules in the user guide. With this approach, for example, you could creat a single tile that used two GT11 transceivers to implement two independent one-lane PCI Express interfaces. EricArticle: 85217
Have any of you tried to simulate the pre-configuration startup conditions
of an FPGA? Sometimes pins are tied high, tied-low, etc. Sometimes the
chip comes out of reset before clocks are ready, etc. Sometimes the
configuration logic is broken.
Board level bring-up with FPGAs always seems to require lab debugging of
reset issues because these things are not normally properly simulated.
It would sure be nice if tool generated back-annotated netlist included the
FPGA startup logic, or at least an approximation of it.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 85218Eric wrote: > What is the best FREE Schematic & PCB Layout software available that > will run on Windoze XP? > > I've looked at PCB123.com and Expresspcb.com and they have pretty good > programs available. Unfortunately if I use either one I'm stuck getting > the prototypes through them. (Because they won't output Gerbers) > > I've also looked at Eagle Layout at cadsoft.de, but the size limitation > of 100 x 80mm on the free version is a negative. It would work for my > current project. > > I'm just curious at what other people's opinions are. In terms of freely available downloads that are useful up to a level I would suggest you have a look at VuTrax <http://www.vutrax.co.uk/>. If the pin limit is too low for your needs the cost of upgrading to the next level is quite reasonable. It is also available for Linux too. -- ******************************************************************** Paul E. Bennett ....................<email://peb@amleth.demon.co.uk> Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/> Mob: +44 (0)7811-639972 Tel: +44 (0)1235-811095 Going Forth Safely ....EBA. http://www.electric-boat-association.org.uk/ ********************************************************************Article: 85219
Thanks for your help Eric. I think this explanation should find its way into the documentation. I am trying to create a very simple data loopback test design. The only examples that I could find require using EDK, and are written in Verilog. I would like to avoid using the former at this point as it would distract my attention from the RocketIO stuff and for a number of reasons I need to use VHDL. So far I have created a single Aurora transmitter and a basic testbench that uses a 32-bit wide counter to supply data to the transmitter. The simulation seems to show that my design is alive, but I am yet to interpret properly what I see... I am having difficulty in figuring out what to do with all the ports that the Architecture Wizard chose to expose. In my opinion there are way too many. Why, for example, the dynamic configuration bus is exposed at all? I think this should be an option... Do I really need to bother about things such as Running Disparity Control, all the CRC stuff, etc. to be able to do basic data loopback? And why do I see RX side clocks in a transmitter only component? Are they there "along for the ride" similarly to the second transceiver? Thanks, /Mikhail "Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:d82i6n$psh5@cliff.xsj.xilinx.com... > Hi, > > In Virtex-4 silicon, the transceivers exist in pairs and they share some > common circuits (such as the dynamic reconfiguration port and clocking > circuits). It is perfectly legal to combine two one-lane designs (using two > GT11) into a single tile as long as you follow the rules in the user guide. > > The architecture wizard is fairly generic, and when writing out code, will > write GT11 in pairs. If you select a one-lane configuration, you will get > one GT11 that is actively used, and another GT11 that is just along for the > ride. The architecture wizard doesn't know enough about your specific > design requirements to determine if transceivers can be shared or not. > However, you can easily take the architecture wizard output and create a > shared tile by copy/paste as long as you are not violating the rules in the > user guide. > > With this approach, for example, you could creat a single tile that used two > GT11 transceivers to implement two independent one-lane PCI Express > interfaces. > > Eric > >Article: 85220
Austin Lesea <austin@xilinx.com> wrote: > It doesn't hurt anyone to have more than one forum, It hurts... At least for all forums not liste by gmane... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 85221
Peter Alfke <peter@xilinx.com> wrote: > Frederic, > We have plenty of XC3S200, but how can we halp you when you give > neither your name nor your company affiliation. Being "pissed off" is > no good when you give us no chance to help you. Peter, go to www.nuhorizons.com , search for XC3S and let only available device get listed. You'll get horrified... Why does .www.xilinx.com only sell CPLDs? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 85222
Michel Billaud wrote: > Will Hua Zheng <Hua.Zheng@jpl.nasa.gov> writes: > > > >>And you are right, you can practice with simulation tools first (this >>lets you see the inner-workings of your design, not just the output). > > > Blinking leds and displaying stupid messages on the 7-segment things > is more fun than reading pages of $monitor() outputs ! > > MB > > Reading a waveform of 100Hz is easier on your eye than LEDs blinking 100 times a second.Article: 85223
"Peter Alfke" <peter@xilinx.com> wrote in message news:1118091416.990182.179050@g14g2000cwa.googlegroups.com... > Frederic, > We have plenty of XC3S200, but how can we halp you when you give > neither your name nor your company affiliation. Being "pissed off" is > no good when you give us no chance to help you. > > Peter Alfke, Xilinx > Perhaps by telling that to Insight Memec in the UK rather than telling them there's a 14 week lead time! Also having more than one distributor in the UK may inspire some customer appreciation.Article: 85224
PQ208 "Antti Lukats" <antti@openchip.org> wrote in message news:d820bq$nnk$00$1@news.t-online.com... > what package do you need? > > Antti > > > "Fred" <Fred@nospam.com> schrieb im Newsbeitrag > news:42a4814e$0$2594$da0feed9@news.zen.co.uk... >> 14 week lead time for samples for the XC3S200. How can you prototype >> with >> that? >> >> It makes worry even more when it comes to manufacture where I might need >> quantity. >> >> > >
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