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I am a newbie and I need rules to assign pins to FPGA. I would imagine some, 1. Group signals that are natually related, and assign them to the same I/O bank/side of the FPGA; 2. Let the software to assign pins, then fix some pins according to the automatic assignment, then let the software run again. Do this iteratively for several times. What is your experience? Suggestions are welcomed. vax, 9000Article: 82226
Then am I to assume that the capacitors on the underside of the PCB share the power and ground vias with the FPGA power and ground vias, or do the capacitors have their own power and ground vias. I always assumed that it was a "no no" to use the vias from the BGA power ground for the capacitors? I realize that my design is not really pushing the envelope, but I want good design practice from the start. Thanks once again for the tips, Jason "Symon" <symon_brewer@hotmail.com> wrote in message news:4256eb9e$3_3@x-privat.org... > Jason, > Comments inline... > "Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message > news:PDy5e.23696$Fy3.1558386@news20.bellglobal.com... > > Symon, > > > > Thanks for the response, I read the thread, very interesting, and I'll > > have > > to speak with my fab house about microvias. You mention lots of room > > underneath the BGA for the decoupling caps, but if they are connected > > (similarly to the BGA) with thru-hole vias for ground then that would > > impact > > on the space as well, unless you are using blind vias for the decoupling > > caps on the bottom of the PCB? There would be lots of vias to stuff in > > there > > with the BGA grounds (thruhole vias) and the capacitor grounds and powers > > (thruhole vias). > > > > Correct, you need to use through vias for the ground and power. But you need > those through vias to connect the BGA balls up anyway, so you're getting > double the use for each one. > > > I have thought that I might be able to go to an eight layer PCB using > > blind > > vias with the following stack up > > > > 1 - signal/component > > 2 - mixed pwr plane > > 3 - ground plane > > 4 - signal > > 5 - signal > > 6 - 3.3V power plane > > 7 - ground > > 8 - signal/component > > > > If I use blind via (layer 1 -3) for power and ground for the BGA then I > > have > > Hmmm, layer 1 to 3 blind vias = expensive. More than one drilling process or > more expensive double layer microvias. And bad SI because the return > currents can't get from one ground plane to the other near the FPGA. > > > lots of room to route signals on layers 4,5, and 8 provided I place > > decoupling caps on layer 1 around the package (FG256). However this then > > goes against the connecting ground planes theory, unless I add lots of > > ground vias to join the planes after I route the signals. I do have quite > > a > > few components for the 3.3V so I don't know if I want to give up that > > plane, > > Give it up! You'll never look back. > > > however my layer 2 is a mixed plane layer (1.8 and 2.5 volts) with more > > than > > enough room to accommodate signals or more 3.3V plane. I'm not sure on > > which > > is better since I have not ventured into this many layers (having multiple > > ground planes) before. > > > > thanks, > > > > Jason > > If I was doing 8 layers, I'd do > 1 - signal/component > 2 - signal > 3 - ground plane > 4 - mixed powers > 5 - signal > 6 - ground plane > 7 - signal > 8 - signal/component > > I'd have microvias between layers 1 and 2. You'll be able to route out every > signal ball of a BGA256 on layers 1 and 2 without a single through via. > Through via every power and ground ball, connect the bypass caps on layer 8. > Of course connect ground vias to all ground planes. > > Anyway, that's what I'd probably do. I hope it gives you some ideas. > > Cheers, Syms. > > > >Article: 82227
Benjamin, These tools are obsolete, by 3 generations (4.2i vs 7.1i). You should check with your university for the latest version of the Embedded Developer's Kit (EDK) and Foundation ISE 7.1i. Ed Benjamin Menküc wrote: > Hi, > > I have found this on the Xilinx-website: > > The Virtex-II Pro Developer’s Kit is a compilation of three CDs. The > first CD, labeled “Virtex-II Pro Developer’s Kit, March 2002” contains > reference systems, hardware/software IP, and documentation. The second > CD, labeled “GNU Software Developer’s Tools for PowerPC®, March 2002” > contains a set of tools for building software applications. The third > CD, labeled “Foundation ISE 4.2I Eval” contains the Xilinx FPGA > Implementation Tools. > > The problem is, that I don't have those 2 cds because I got the > starterkit from my university... Is there any source on the web to get > the cds? > > regards, > BenjaminArticle: 82228
"Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message news:qqD5e.26388$Fy3.1624833@news20.bellglobal.com... > Then am I to assume that the capacitors on the underside of the PCB share > the power and ground vias with the FPGA power and ground vias, or do the > capacitors have their own power and ground vias. I always assumed that it > was a "no no" to use the vias from the BGA power ground for the > capacitors? > Hi Jason, Absolutely, it's a "yes yes" to share the vias for the BGA grounds/power with the bypass caps. It works great. Another site you might be interested in is http://www.sigcon.com/pubsIndex.htm Click on 'bypass capacitors' for some interesting stuff. This article shows where to put your vias relative to the capacitors. http://www.sigcon.com/Pubs/news/6_09.htm Best, Syms.Article: 82229
Hi Jedi, > Any information regarding new Quartus 5.0 and NIOS II? If all goes according to schedule, both should be released early May. Nios II version number will be bumped up to 5.0 to align with Quartus version number. Check with your local FAE for more details. Best regards, BenArticle: 82230
Hello all,
I'm dealing with ISE 7.1sp1 and am trying to load the drivers (for
Parallel IV) needed to run Impact under the "xilinx supported" RHEL3.0.
I get the errors listed below during install, and again if I try
"install_windrvr6" in the /lib/modules/misc directory. They definitely
appear to be kernel mismatch problems. Any advice? Any idea if the new
xilinx driver source is available?
Warning: kernel-module version mismatch
/lib/modules/misc/windrvr6.o was compiled for kernel version
2.4.18-14
while this kernel is version 2.4.21-20.EL
/lib/modules/misc/windrvr6.o: unresolved symbol
pci_write_config_word_Reb06a06f
/lib/modules/misc/windrvr6.o: unresolved symbol map_user_kiobuf_R59ddbb4a
/lib/modules/misc/windrvr6.o: unresolved symbol
pci_write_config_byte_Rc8265797
/lib/modules/misc/windrvr6.o: unresolved symbol usb_set_interface_Rcb6c63b5
/lib/modules/misc/windrvr6.o: unresolved symbol add_wait_queue_R11dfb1e5
/lib/modules/misc/windrvr6.o: unresolved symbol
pci_register_driver_Racd7be09
/lib/modules/misc/windrvr6.o: unresolved symbol remove_wait_queue_Rb3afbf37
/lib/modules/misc/windrvr6.o: unresolved symbol usb_unlink_urb_Rbb64dcdc
/lib/modules/misc/windrvr6.o: unresolved symbol
pci_read_config_dword_R66468a6e
/lib/modules/misc/windrvr6.o: unresolved symbol mem_map_R12cb6230
/lib/modules/misc/windrvr6.o: unresolved symbol usb_clear_halt_R1a1bb8f1
/lib/modules/misc/windrvr6.o: unresolved symbol register_chrdev_R44b36f42
/lib/modules/misc/windrvr6.o: unresolved symbol
pci_read_config_byte_R90c21225
/lib/modules/misc/windrvr6.o: unresolved symbol usb_deregister_R0ae4ed30
/lib/modules/misc/windrvr6.o: unresolved symbol lock_kiovec_R45c6c469
/lib/modules/misc/windrvr6.o: unresolved symbol remap_page_range_R69d01e73
/lib/modules/misc/windrvr6.o: unresolved symbol pci_enable_device_Ra2411ea7
/lib/modules/misc/windrvr6.o: unresolved symbol add_timer_Ra19eacf8
/lib/modules/misc/windrvr6.o: unresolved symbol
pci_read_config_word_R4433deb0
/lib/modules/misc/windrvr6.o: unresolved symbol do_munmap_R39d002a0
/lib/modules/misc/windrvr6.o: unresolved symbol
pci_unregister_driver_R513ca96c
/lib/modules/misc/windrvr6.o: unresolved symbol usb_alloc_urb_R50bd716b
/lib/modules/misc/windrvr6.o: unresolved symbol usb_free_urb_R49f8d975
/lib/modules/misc/windrvr6.o: unresolved symbol usb_ifnum_to_if_Rb490df97
/lib/modules/misc/windrvr6.o: unresolved symbol del_timer_Rfc62f16d
/lib/modules/misc/windrvr6.o: unresolved symbol usb_submit_urb_Rf2e18c64
/lib/modules/misc/windrvr6.o: unresolved symbol free_kiovec_Rc91c8e82
/lib/modules/misc/windrvr6.o: unresolved symbol alloc_kiovec_Rb7823fc0
/lib/modules/misc/windrvr6.o: unresolved symbol pci_find_slot_R496697bb
/lib/modules/misc/windrvr6.o: unresolved symbol do_mmap_pgoff_R03a11d71
/lib/modules/misc/windrvr6.o: unresolved symbol pci_set_master_R00ba60ca
/lib/modules/misc/windrvr6.o: unresolved symbol unmap_kiobuf_R56b19ff7
/lib/modules/misc/windrvr6.o: unresolved symbol usb_register_Ree3d8a5f
/lib/modules/misc/windrvr6.o: unresolved symbol
pci_write_config_dword_R57e8add4
/lib/modules/misc/windrvr6.o:
Hint: You are trying to load a module without a GPL compatible license
and it has unresolved symbols. The module may be trying to access
GPLONLY symbols but the problem is more likely to be a coding or
user error. Contact the module supplier for assistance, only they
can help you.
Article: 82231Hi, I know thats an old version, I already have the latest ISE. But I am looking for some sample programms that use the LCD from my board or something like that (reference systems). I have this board: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&key=DS-KIT-2VP4LC At the moment I can not assign my ports to a pin, very weird. I can only choose a bank in the "loc"-field but not a specific pin. regards, BenjaminArticle: 82232
Hi, My recent experience is with Altera Cyclone I needed to lay out the PCB first, so this is how I did it : 1 - Best possible layout for power supply pins and decouplers 2 - Best layout for clock inputs 3 - Dedicated functions (config etc) 4 - Use the general I/O in a way that gives the best layout (shortest routes, fewest crossovers etc) - This will naturally tend to group stuff functionally 5 - Tell Quartus exactly what pin-out I want I have had no problems meeting my timing requirements (300MHz) and fitting my functions with this device and this approach. I remember a few years ago, old Xilinx XC5200 series devices were less forgiving about this. I'm sure this approach doesn't squeeze the last drop out of the device, but the PCB sure looks beautiful Gary "vax, 9000" <vax9000@gmail.com> wrote in message news:d36s7p$7nn$1@charm.magnus.acs.ohio-state.edu... >I am a newbie and I need rules to assign pins to FPGA. I would imagine >some, > > 1. Group signals that are natually related, and assign them to the same > I/O > bank/side of the FPGA; > 2. Let the software to assign pins, then fix some pins according to the > automatic assignment, then let the software run again. Do this iteratively > for several times. > > What is your experience? Suggestions are welcomed. > > vax, 9000 > >Article: 82233
Hi, I don't know if my experience is relevant.. I'm using a 2.6 kernel.. but here goes... Impact wouldn't find my parallel port either. I had to compile and load in a wierd driver, windrvr6, from www.jungo.com, after registering with thier website :( which apparantly provides a layer between the sw and ports, emulating a windows box. Their software creates a device windrvr6 in the /dev directory, which I gave 777 permisions to. Really wasn't happy about the whole situation at all. There's a few FAQs out there about this, I think one is at: http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm You're using ISE 7.1sp1? Does that fix the fact that JEDEC file generation for CPLDs isn't really functioning? Good luck, AlexArticle: 82234
Eric Smith wrote: > Ray Andraka wrote about reverse-engineering ASICs based on behavior vs. > analyzing the mask layout: > >>it may take a bit of work to ferret out all the operation, but it is >>likely still easier than trying to reverse engineer from masks. > > > Speaking of such things, I have a number of old chips from which I want > to extract masked ROM and PLA contents from. Since those are very > regular strutures, and they in parts with single layer metal in 5 micron > and larger geometry, it should be fairly easy. In fact, here's an > example of someone doing this: > http://www.pmonta.com/calculators/hp-35/ > > He extracted code from 10 micron PMOS masked ROMs that were packaged in > metal cans, by the simple expedient of removing the top of the can with > a dremel tool or the like. > > I want to do basically the same thing with other chips from that era, > but they're in plastic DIP packaging. I don't want to mess with > high-temperature fuming nitric acid and such things. Can anyone > recommend a lab that will do this, and take photomicrographs, at > a "reasonable" price? > > Before everyone jumps on me about piracy, I'll explain that the ROM > and PLA code in question is NOT copyrighted. > > Thanks! > Eric ...and, pray tell, how do you get to that conclusion? Every time one generates a document or a pattern (in this case the codes, masks, etc), such items *by FEDERAL law* are copyrighted! In fact, your missive to this NG, and my answer here is copyrighted! Now, if anyone wanted to make some lawyers rich and go to court over mis-use of copyrighted material, then copyright *registration* would be considered as the ultimate proof that judges cannot go against.Article: 82235
I wrote:
> Before everyone jumps on me about piracy, I'll explain that the ROM
> and PLA code in question is NOT copyrighted.
Robert Baer wrote:
> ...and, pray tell, how do you get to that conclusion?
By knowing some of the details of US Copyright Law (Title 17 of the
United States Code).
> Every time one generates a document or a pattern (in this case the
> codes, masks, etc), such items *by FEDERAL law* are copyrighted!
In the US, that wasn't the case before the Berne Copyright Convention took
effect, March 1, 1989. See 17 U.S.C. 405(a):
Sec. 405. Notice of copyright: Omission of notice on certain copies
and phonorecords
(a) Effect of Omission Copyright on With respect to copies and
phonorecords publicly distributed by authority of the copyright owner
before the effective date of the Berne Convention Implementation Act
of 1988, the omission of the copyright notice described in sections
401 through 403 from copies or phonorecords publicly distributed by
authority of the copyright owner does not invalidate the copyright in
a if work
* (1) the notice has been omitted from no more than a relatively
small number of copies or phonorecords distributed to the
public; or
* (2) registration for the work has been made before or is made
within five years after the publication without notice, and a
reasonable effort is made to add notice to all copies or
phonorecords that are distributed to the public in the United
States after the omission has been discovered; or
* (3) the notice has been omitted in violation of an express
requirement in writing that, as a condition of the copyright
owner's authorization of the public distribution of copies or
phonorecords, they bear the prescribed notice.
In the case of the ROMs and PLAs I want to extract, none of the
conditions for preservation of a copyright without notice have been
met.
Also, these parts were sold before the Semiconductor Chip Protection Act
of 1984 (17 USC 901 et seq.) was enacted, so they are not elgible for
protection as mask works.
> In fact, your missive to this NG, and my answer here is copyrighted!
True, because the Berne Convention is in effect. I'm including quotes
from your message here as a matter of fair use.
> Now, if anyone wanted to make some lawyers rich and go to court
> over mis-use of copyrighted material, then copyright *registration*
> would be considered as the ultimate proof that judges cannot go
> against.
Technically registration is still a legal requirement, even though
a copyright notice is not.
However, the main practical effect of registration is that it allows you
to collect actual damages for infringement. Without registration, you
can only collect statutory damages, though they can be fairly substantial.
Eric
Article: 82236
Hi,
You can load the DDR with whatever u want by just specifying the
address of the DDR which is nothing but 0x00000000 So u can just say
addr = 0x0000000;
*addr = 0x01;
So this loads "1" to 0x0000000 address location..But if ur Hardware
has to access the DDR then u need to be a Bus Master (so that u can
grab control of the bus and do whatever u want )...and for this u need
not go through PPC...
So I guess this answers ur question
--
Parag Beeraka
Article: 82237Hello Alex, I have, as well, been able to get the 6.3 drivers to work under the 2.6 kernel though the use of the self-compiled windrvr6. I could do that in this situation as well, however the xilinx xpc4drvr.o module also has the same kernel version dependencies, and no source is provided or locatable on ftp or Xilinx web. It is possible that the xpc4drvr with 7.1 is the same as 6.3, however there is a "roll-back patch" available from xilinx to make the 7.1 drivers compatible with certain 6.3 impact features, leading me to believe 7.1 is different. In regards to your JEDEC/CPLD question, I have only worked with the Virtex II Pro and EDK targeted for a ppc linux platform. I'd be happy to test compile a small design you may have and get back to you. Just email me. Speaking of 2.6 however, is anybody else working on getting the 2.6 kernel working on the ppc with the ML300/ML310 boards? Thanks, Anthony Alex wrote: > Hi, > > I don't know if my experience is relevant.. I'm using a 2.6 kernel.. > but here goes... > Impact wouldn't find my parallel port either. > I had to compile and load in a wierd driver, windrvr6, from > www.jungo.com, after registering with thier website :( which apparantly > provides a layer between the sw and ports, emulating a windows box. > Their software creates a device windrvr6 in the /dev directory, which I > gave 777 permisions to. Really wasn't happy about the whole situation > at all. > > There's a few FAQs out there about this, I think one is at: > http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm > > You're using ISE 7.1sp1? Does that fix the fact that JEDEC file > generation for CPLDs isn't really functioning? > > Good luck, > > Alex >Article: 82238
Just a short note of caution .... After installing sp1 for ise 7.1 (linux) mapper is crashing: map -p xc4vlx25-sf363-10 -timing -register_duplication -pr b -o usb_top_map.ncd usb_top.ngd usb_top.pcf Release 7.1.01i - Map H.39 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Using target part "4vlx25sf363-10". Mapping design into LUTs... Writing file usb_top_map.ngm... Running directed packing... Running delay-based LUT packing... Running timing-driven packing... Phase 1.1 Phase 1.1 (Checksum:9e05bf) REAL time: 8 secs <SNIP> Phase 14.5 Phase 14.5 (Checksum:8583af2) REAL time: 5 mins 23 secs Invoking physical synthesis ... Abort (core dumped) Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 82239
It's been now several weeks since the release of 7.1. However I still have not seen a "fix" that would allow us to install ISE 7.1 on 64 bit platforms: [rudi@cpu10 ISE71i_DesignEnv_lin64]$ ./setup /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/bin/lin64 /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/xilsetup: Symbol `_XtperDisplayList' causes overflow in R_X86_64_PC32 relocation /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/xilsetup: Symbol `_XtGetPerDisplayInput' causes overflow in R_X86_64_PC32 relocation Wind/U Error (294): Unable to install Wind/U ini file (/home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/data/WindU). See the Wind/U manual for more details on the ".WindU" file and the "WINDU" environment variable. /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/setup: line 163: 19510 Segmentation fault (core dumped) $setuploc/xilsetup $switch $batchfile ************ setup done! *************** Will xilinx ever release a setup program that works, or do we have to wait for 7.2 ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 82240
"Elektro" <blabla@bredband.net> schrieb im Newsbeitrag news:4256f0c0$0$43985$14726298@news.sunsite.dk... > Hello > > > > Yes, I used the "JTAG_Loader_ROM_form.vhd" file and made the changes to > include a reset signal. > > But I think I maybe know what I made wrong. > > After I ran the JTAG bat-file I pressed the reset button on the Spartan 3 > Evaluation Board, and by doing that the FLASH memory contents was again > loaded into the FPGA (fith the original PicoBlaze ROM). :-/ you must load the design with jtag_rom befroe running the .bat file and sure dont reconfig after that but be aware that the .bat file that downloads the picoblaze does not error checking at all, it reports all ok also when no FPGA is attached, so you must be sure that the xsvfplayer really can connect to the cable, etc > > I can't confirm this until Monday, but does it seem likely? > And what should I answer when the JTAG_loader.bat ask: > > "How many JTAG devices are before the PicoBlaze FPGA in your chain ? >" > > Should I answer 1 because in the iMPACT-tool the FPGA is the first device > and the second device is the FLASH-memory? 0, if FPGA is first > And when it asks: > > "How many JTAG devices are after the PicoBlaze FPGA in your chain ? >" > > Should I answer 1 because there is one devide after the FPGA in the JTAG > chain? yes, 1 > > "Antti Lukats" <antti@openchip.org> skrev i meddelandet > news:d36dnk$p2o$00$1@news.t-online.com... > > where are you stuck? > > did you rename the jtag_loader_rom_form.vhd into rom_form.vhd and copied > > into the assembler dir? > > you should then get special rom file that includes BSCAN, if you now build > > the Picoblaze system > > and download that to the FPGA then the ROM should be accessible over JTAG > > using the supplied > > tools. I think the version as shipped doesnt work on V4 but I guess you > > should have got synthesis > > error if you are targetting V4 > > > > or did you have problem converting the hex into XSVF? > > or did you have errors during XSVF file execution? > > > > Antti > > http://gforge.openchip.org > > > > > > "Elektro" <blabla@bredband.net> schrieb im Newsbeitrag > > news:4256b12d$0$43988$14726298@news.sunsite.dk... > > > Hello > > > > > > I'm trying to use the PicoBlaze JTAG Program Loader supplied with the > > > PicoBlaze package to download a new ROM contents. But I don't seem to > get > > > the new ROM down to my FPGA. > > > > > > Do any of you have some advise? > > > Thanks > > > > > > > > > > >Article: 82241
Content-Transfer-Encoding: 8Bit
Eric Smith wrote:
>the Berne Copyright Convention took effect [0n], March 1, 1989.
>See 17 U.S.C. 405(a):
>
> Sec. 405. Notice of copyright: Omission of notice on certain copies
> and phonorecords
>
> (a) Effect of Omission Copyright on With respect to copies and
> phonorecords publicly distributed by authority of the copyright owner
> before the effective date of the Berne Convention Implementation Act
> of 1988, the omission of the copyright notice described in sections
> 401 through 403 from copies or phonorecords publicly distributed by
> authority of the copyright owner does not invalidate the copyright in
> a if work
>
> * (1) the notice has been omitted from no more than a relatively
> small number of copies or phonorecords distributed to the
> public; or
>
> * (2) registration for the work has been made before or is made
> within five years after the publication without notice, and a
> reasonable effort is made to add notice to all copies or
> phonorecords that are distributed to the public in the United
> States after the omission has been discovered; or
>
> * (3) the notice has been omitted in violation of an express
> requirement in writing that, as a condition of the copyright
> owner's authorization of the public distribution of copies or
> phonorecords, they bear the prescribed notice.
>
>In the case of the ROMs and PLAs I want to extract, none of the
>conditions for preservation of a copyright without notice have been
>met.
Just for reference, here is a list of when copyrights run
out in various situations. Corrections/comments welcome.
**************************************************
DATE OF WORK: Published before 1923
PROTECTED FROM: In public domain
TERM: None
**************************************************
DATE OF WORK: Published from 1923 - 63
PROTECTED FROM: When published with notice [3]
TERM: 28 years + could be renewed for 47 years,
now extended by 20 years for a total renewal
of 67 years. If not so renewed, now in
public domain
**************************************************
DATE OF WORK: Published from 1964 - 77
PROTECTED FROM: When published with notice 28 years
for first term;
TERM: now automatic extension of 67 years for
second term
**************************************************
DATE OF WORK: Created before 1-1-78 but not published
PROTECTED FROM: 1-1-78 (Effective date of 1976
Copyright Act)
TERM: Life + 70 years or 12-31-2002, whichever is greater
**************************************************
DATE OF WORK: Created before 1-1-78 but published
between then and 12-31-2002
PROTECTED FROM: 1-1-78, (Effective date of 1976
Copyright Act)
TERM: Life + 70 years or 12-31-2047 whichever
is greater
**************************************************
DATE OF WORK: Created 1-1-78 or after
PROTECTED FROM: When work is fixed in tangible
medium of expression
TERM: Life + 70 years [1] (or if work of corporate
authorship, the shorter of 95 years from
publication, or 120 years from creation [2]
**************************************************
Notes:
[1] Term of joint works is measured by life of the
longest-lived author.
[2] Works for hire, anonymous and pseudonymous
works also have this term. 17 U.S.C. 302(c).
[3] Under the 1909 Act, works published without
notice went into the public domain upon
publication. Works published without notice
between 1-1-78 and 3-1-89, effective date of
the Berne Convention Implementation Act, retained
copyright only if, e.g., registration was made
within five years. 17 U.S.C. 405.
Source: Tom Field / Lolly Gasaway.
--
Guy Macon <http://www.guymacon.com/>
Article: 82242On 08 Apr 2005 19:16:09 -0700, Eric Smith <eric@brouhaha.com> wrote: > I wrote: >> Before everyone jumps on me about piracy, I'll explain that the ROM >> and PLA code in question is NOT copyrighted. > > Robert Baer wrote: >> ...and, pray tell, how do you get to that conclusion? > > By knowing some of the details of US Copyright Law (Title 17 of the > United States Code). > >> Every time one generates a document or a pattern (in this case the >> codes, masks, etc), such items *by FEDERAL law* are copyrighted! > > In the US, that wasn't the case before the Berne Copyright Convention took > effect, March 1, 1989. See 17 U.S.C. 405(a): > IANAL, but I believe that requirement for copyright notice applied to published works then. But I don't know whether PLA code was considered an expression that was copyrightable then or that distributing IC constituted publication even. You probably need a real IP lawyer to answer that. But since you're incurring the liablity here, it's your call. If you were considering putting this stuff under an opensource license it might be more problematic since you would not be the original author by your own admission. You'd probably want to document why you think the work is in the public domain. -- Joe SeighArticle: 82243
Brijesh <brijesh_xyz@cfrsi_xyz.com> wrote in message news:<d33k4c$sjr$1@solaris.cc.vt.edu>... > We have a board with multiple IDE interfaces implemented in Virtex2 > device. We are using UDMA 3 protocol. > One of the boards is giving a CRC error at random times, erros occurs > once in 12 hrs of continous read operations. Error occurs on the same > IDE channel. According to the ATA/ATAPI spec, you need input buffers with at least 320 mV of hysteresis. The appendix notes that double clocking of the CRC calculator while capturing the correct data or calculating the correct CRC while capturing wrong data had been observed, thus the requirement. Maybe that's your problem? BTW: The spec also notes that your inputs must be 5 V tolerant, which AFAICS can't be achieved on a pure Virtex-II while keeping the correct dimensions of the series resistors. The FPGA must even widthstand 6 V ringing voltages. I don't know if a Virtex-II can do this. > All inputs are LVTTL 3.3V, no IBUF delays used on strobe or data. On > Strobe pins I have enabled DCI with 50 Ohm resistor. But now my > understanding is that for LVTTL 3.3V input pins, DCI does no good. I don't know much about these issues (I design circuits for FPGA/ASICs and do no "real" hardware), but don't you need to take LVCMOS33 for outputs? > A separate question I was trying to look up the source impeadance/input > impeadance of V2 outputs/inputs, couldn't find the number anywhere. Are > they specified? The ATA/ATAPI specs dictate that the series termination plus input impedance is between 50 and 85 Ohms. How have you taken the values for your board without knowing those of the FPGA? Sebastian WeiserArticle: 82244
Hi, I got a little bit started now, with flashing some LEDs on my board.... However I think there is a bug in PACE when assigning pins to nets, I can only select Banks in the Loc field there. regards, BenArticle: 82245
Rudolf Usselmann wrote: > > Just a short note of caution .... > > After installing sp1 for ise 7.1 (linux) mapper is crashing: > > map -p xc4vlx25-sf363-10 -timing -register_duplication -pr b -o > usb_top_map.ncd usb_top.ngd usb_top.pcf > Release 7.1.01i - Map H.39 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > Using target part "4vlx25sf363-10". > Mapping design into LUTs... > Writing file usb_top_map.ngm... > Running directed packing... > Running delay-based LUT packing... > Running timing-driven packing... > > Phase 1.1 > Phase 1.1 (Checksum:9e05bf) REAL time: 8 secs > > <SNIP> > > Phase 14.5 > Phase 14.5 (Checksum:8583af2) REAL time: 5 mins 23 secs > > Invoking physical synthesis ... > Abort (core dumped) > > Regards, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis > > This problem can be avoided if you turn off that new "-register_duplication" feature. BretArticle: 82246
"Bret Wade" <bret.wade@xilinx.com> schrieb im Newsbeitrag news:d38nu7$6qk6@xco-news.xilinx.com... > Rudolf Usselmann wrote: > > > > Just a short note of caution .... > > > > After installing sp1 for ise 7.1 (linux) mapper is crashing: > > > > map -p xc4vlx25-sf363-10 -timing -register_duplication -pr b -o > > <SNIP> > > > > Phase 14.5 > > Phase 14.5 (Checksum:8583af2) REAL time: 5 mins 23 secs > > > > Invoking physical synthesis ... > > Abort (core dumped) > > > > Regards, > > rudi > > ============================================================= > > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > > Your Partner for IP Cores, Design, Verification and Synthesis > > > > > > This problem can be avoided if you turn off that new > "-register_duplication" feature. > > Bret a nice "feature" !! you should call thise feature "force core dump" then people would know to avoid it, and not spend hours of frustration! anttiArticle: 82247
Hello > > "How many JTAG devices are before the PicoBlaze FPGA in your chain ? > >" > > > > Should I answer 1 because in the iMPACT-tool the FPGA is the first device > > and the second device is the FLASH-memory? > > 0, if FPGA is first It should have said 0, I just thought wrong here at home :-) Thank you for your advice.Article: 82248
There is an old slide presentation of mine on the web, where slides 100 and 101 describe a simple way to cope with double-pulsing clocks .http://www.google.com/search?client=safari&rls=en-us&q=%22peter+alfke%22&ie=UTF-8&oe=UTF-8 Peter Alfke ============================ Sebastian Weiser wrote: > Brijesh <brijesh_xyz@cfrsi_xyz.com> wrote in message news:<d33k4c$sjr$1@solaris.cc.vt.edu>... > > We have a board with multiple IDE interfaces implemented in Virtex2 > > device. We are using UDMA 3 protocol. > > One of the boards is giving a CRC error at random times, erros occurs > > once in 12 hrs of continous read operations. Error occurs on the same > > IDE channel. > > According to the ATA/ATAPI spec, you need input buffers with at least > 320 mV of hysteresis. The appendix notes that double clocking of the > CRC calculator while capturing the correct data or calculating the > correct CRC while capturing wrong data had been observed, thus the > requirement. Maybe that's your problem? > BTW: The spec also notes that your inputs must be 5 V tolerant, which > AFAICS can't be achieved on a pure Virtex-II while keeping the correct > dimensions of the series resistors. The FPGA must even widthstand 6 V > ringing voltages. I don't know if a Virtex-II can do this. > > > All inputs are LVTTL 3.3V, no IBUF delays used on strobe or data. On > > Strobe pins I have enabled DCI with 50 Ohm resistor. But now my > > understanding is that for LVTTL 3.3V input pins, DCI does no good. > > I don't know much about these issues (I design circuits for FPGA/ASICs > and do no "real" hardware), but don't you need to take LVCMOS33 for > outputs? > > > A separate question I was trying to look up the source impeadance/input > > impeadance of V2 outputs/inputs, couldn't find the number anywhere. Are > > they specified? > > The ATA/ATAPI specs dictate that the series termination plus input > impedance is between 50 and 85 Ohms. How have you taken the values for > your board without knowing those of the FPGA? > > > Sebastian WeiserArticle: 82249
Hi,I am a newbie in using EDK. when I debug with XMD in a simple project whose only function is to control the LEDs through gpio,I read the bram using the order "mrd" and set bram using "mwr" in order to make the led off and on,but after I keyin the "mwr" order the value of specified address of bram did not changed at all!! why did this happened? Is this address of bram read-only?if that,how to check the attribute(read-only or read-write) of a certain segment of memory thanks a lot
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