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"Wojtek" <woytecc@poczta.fm> wrote in message news:d35u5b$3bh$1@nemesis.news.tpi.pl... > Hi, im tryin to perform a 2D DCT in VHDL with modelsim simulator but to be > honest with you i don't know how to start so if someone can help me it > will > be great. > thanks > Are you intending to use a fast DCT or a regular DCT. Fast will save you multipliers, but add considerable complexity in the transpose buffer. IIRC, Xilinx has a series of app notes that exploit symmetry once, for a total of four multiplies per output sample per direction. Check them out.Article: 82201
I use blowers from http://www.sunon.com/english.htm HTH, Syms. <junkmail@fastertechnology.com> wrote in message news:1112969312.502975.189710@o13g2000cwo.googlegroups.com... >I am looking for heat sinks with an attached fan for use on a Xilinx > FF1152 package on a PCI card.Article: 82202
Hi Jason, Have a look at this thread. http://groups-beta.google.com/groups?q=PCBs+for+modern+FPGAs Ten layers, three ground planes, route the power, microvias between layers 1 and 2. I've long since given up on power planes across the whole board. Think of all the different powers you need. 1.2, 1.5, 1.8, 2.5, 3.3 blah blah blah. Little local power copper floods are the answer. And yes, you should connect the three ground planes together with all the vias you can, especially in the FPGA area. This provides paths for the return currents of signals and power floods on layers adjacent to the ground planes. If you use microvias on the top layers, there's loads of space underneath for decoupling caps. It really works and it works really well. Really! Cheers, Syms. "Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message news:nal5e.9777$6k4.878787@news20.bellglobal.com... > Hello all, > > I have a question regarding the layout of a BGA packaged FPGA. For the > first > time I am using multiple ground planes, and I am curious if when routing > the > ground balls from the BGA package, do I need to have a via that attaches > to > both ground planes, or is having it attach to one plane directly under the > package enough, as long as there are vias elsewhere that tie the two > planes > together. I would ideally like to use blind vias for the BGA layout so I > can > get components on the underside of the PCB as well without any through > hole > vias getting in the way. My satckup is as follows: > > 1 - signal/components > 2 - ground plane > 3 - signal > 4 - signal > 5 - power plane > 6- ground plane > 7 - signal > 8 - signal > 9 - power plane > 10 -signal > > I was planning on mounting the caps underneath the BGA package on the > underside, again using blind vias so there is more room for signal > routing, > but I'm considering mounting them around the package on the top side now. > 100 MHz is the highest frequency signal anywhere on the board, and most > signals are 50 MHz speed (or there abouts). > > Any comments would be greatly appreciated. > > Thanks, > > Jason > > jberringerNOSPAMatNOSPAMsympatico.ca (remove NOSPAM) > >Article: 82203
Peter, I understand that DDR does not invalidate your response. Just mentioned it clear up things. I just wanted to know if I was heading in the right direction by suspecting that slower rise time may be causing the problem. Since I didnt know how slow is too slow, hence the question. So now I know there is no fundamental limiting factor on how slow a edge can be on V2. I will concentrate my efforts on identifying if the strobe line is being corrupted by noise or cross talk. I was hoping there was some rule of thumb from experience that edges slower than X ns/V is inviting trouble. :-) Jim Granville, Thanks for the response. Yess, I am going slow the edge on other channels and also on this channel and see if the errors occurs more frequently. Thanks Brijesh Peter Alfke wrote: > There is no fundamental limit. A flip-flop will be clocked, even if the > clock takes seconds or minutes to rise. But the longer the transition > time, the bigger the chance of picking up noise, and creating a > double-pulse. And the fact that you use DDR does not invalidate my > prvious response. Noise then has a chance to disturb either edge or > both. > Peter Alfke > ============ > Brijesh wrote: > >>Peter Alfke wrote: >> >> >>>If you use STROBE as a rising-edge clock input, then excessive > > noise > >>>might be superimposed on its falling edge, such that the falling > > edge > >>>actually contains a rising edge clock, which would give you weird >>>timing. >>>Just a wild guess... >>>Peter Alfke >>> >> >>Hello Peter, >> >>Its DDR scheme. Data is clocked in both on the rising edge and > > falling edge. > >>My main question is still how slow is too slow? >> >>Thanks >> >>Brijesh > >Article: 82204
John Mashey wrote: > Of course, lots of ISAs have borrowed > from each other, and and ADD is an ADD :-). Unless it's a TAD. Or an A. Although TAD (for Two's Complement Add) is hallowed by its appearance on the PDP-8, that isn't really a major alternative. But there are two basic schools of thought on assembler mnemonics. One is the IBM 704 school of thought, where every mnemonic is exactly three letters long. The other is the IBM 360 school of thought, where the mnemonics are as short as possible to be distinct. Of course, today's assemblers tend to draw inspiration from another computer, the PDP-11, and use various symbols preceding operands to indicate addressing modes. John SavardArticle: 82205
Hello I’m trying to use the PicoBlaze JTAG Program Loader supplied with the PicoBlaze package to download a new ROM contents. But I don’t seem to get the new ROM down to my FPGA. Do any of you have some advise? ThanksArticle: 82206
Symon, Thanks for the response, I read the thread, very interesting, and I'll have to speak with my fab house about microvias. You mention lots of room underneath the BGA for the decoupling caps, but if they are connected (similarly to the BGA) with thru-hole vias for ground then that would impact on the space as well, unless you are using blind vias for the decoupling caps on the bottom of the PCB? There would be lots of vias to stuff in there with the BGA grounds (thruhole vias) and the capacitor grounds and powers (thruhole vias). I have thought that I might be able to go to an eight layer PCB using blind vias with the following stack up 1 - signal/component 2 - mixed pwr plane 3 - ground plane 4 - signal 5 - signal 6 - 3.3V power plane 7 - ground 8 - signal/component If I use blind via (layer 1 -3) for power and ground for the BGA then I have lots of room to route signals on layers 4,5, and 8 provided I place decoupling caps on layer 1 around the package (FG256). However this then goes against the connecting ground planes theory, unless I add lots of ground vias to join the planes after I route the signals. I do have quite a few components for the 3.3V so I don't know if I want to give up that plane, however my layer 2 is a mixed plane layer (1.8 and 2.5 volts) with more than enough room to accommodate signals or more 3.3V plane. I'm not sure on which is better since I have not ventured into this many layers (having multiple ground planes) before. thanks, Jason "Symon" <symon_brewer@hotmail.com> wrote in message news:d367qh$mba$1@domitilla.aioe.org... > Hi Jason, > Have a look at this thread. > http://groups-beta.google.com/groups?q=PCBs+for+modern+FPGAs > Ten layers, three ground planes, route the power, microvias between layers 1 > and 2. I've long since given up on power planes across the whole board. > Think of all the different powers you need. 1.2, 1.5, 1.8, 2.5, 3.3 blah > blah blah. Little local power copper floods are the answer. > And yes, you should connect the three ground planes together with all the > vias you can, especially in the FPGA area. This provides paths for the > return currents of signals and power floods on layers adjacent to the ground > planes. If you use microvias on the top layers, there's loads of space > underneath for decoupling caps. > It really works and it works really well. > Really! > Cheers, Syms. > > "Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message > news:nal5e.9777$6k4.878787@news20.bellglobal.com... > > Hello all, > > > > I have a question regarding the layout of a BGA packaged FPGA. For the > > first > > time I am using multiple ground planes, and I am curious if when routing > > the > > ground balls from the BGA package, do I need to have a via that attaches > > to > > both ground planes, or is having it attach to one plane directly under the > > package enough, as long as there are vias elsewhere that tie the two > > planes > > together. I would ideally like to use blind vias for the BGA layout so I > > can > > get components on the underside of the PCB as well without any through > > hole > > vias getting in the way. My satckup is as follows: > > > > 1 - signal/components > > 2 - ground plane > > 3 - signal > > 4 - signal > > 5 - power plane > > 6- ground plane > > 7 - signal > > 8 - signal > > 9 - power plane > > 10 -signal > > > > I was planning on mounting the caps underneath the BGA package on the > > underside, again using blind vias so there is more room for signal > > routing, > > but I'm considering mounting them around the package on the top side now. > > 100 MHz is the highest frequency signal anywhere on the board, and most > > signals are 50 MHz speed (or there abouts). > > > > Any comments would be greatly appreciated. > > > > Thanks, > > > > Jason > > > > jberringerNOSPAMatNOSPAMsympatico.ca (remove NOSPAM) > > > > > >Article: 82207
Brijesh, It is possible to de-glitch your clock in the FPGA. Like this. Let's call your input clock, 'CLOCK'. OK, feed this into and back out of an unbonded IOB with the input delay turned on. This gives you 'CLOCK_DELAYED'. Add a SR latch. When CLOCK = '1' and CLOCK_DELAYED = '0', set the latch. When CLOCK = '0' and CLOCK_DELAYED = '1', reset the latch. The output of the latch is your new clock. The IOB-delay filters any glitches shorter than the delay. Cascade more unbonded IOBs for more delay. Horrible or what? Make sure you use MAXDELAY constraints in the UCF file, especially for 'CLOCK' to the latch. Manually place the latch next to the 'CLOCK''s input IOB. Cheers, Syms.Article: 82208
where are you stuck? did you rename the jtag_loader_rom_form.vhd into rom_form.vhd and copied into the assembler dir? you should then get special rom file that includes BSCAN, if you now build the Picoblaze system and download that to the FPGA then the ROM should be accessible over JTAG using the supplied tools. I think the version as shipped doesnt work on V4 but I guess you should have got synthesis error if you are targetting V4 or did you have problem converting the hex into XSVF? or did you have errors during XSVF file execution? Antti http://gforge.openchip.org "Elektro" <blabla@bredband.net> schrieb im Newsbeitrag news:4256b12d$0$43988$14726298@news.sunsite.dk... > Hello > > I'm trying to use the PicoBlaze JTAG Program Loader supplied with the > PicoBlaze package to download a new ROM contents. But I don't seem to get > the new ROM down to my FPGA. > > Do any of you have some advise? > Thanks >Article: 82209
Hi, I'm looking in to programming a Cyclone device and it's prom via an embedded processor. I've found documentation on how to load the FPGA it's self but not the prom. Has anyone dealt with this? Is there any ideal setup via the JTAG connection? -TomArticle: 82210
there is no docs about this. if you are configuring the FGPA over JTAG you may add small ipcore that 'bridges' the cyclone_scan primitive to the asmi block, then you can use the cyclone JTAG user command to send commands to the memory on the ASMI pins. If you are using some other memory then you need to add logic from scan to the user pins connected to the memory. http://gforge.openchip.org/projects/jtaghub/ there is example how to instantiate cyclone_scan in Quartus, using the ASMI prims for the acces to the spi rom is simple as well. but you need to write some software that sends the commands using the altera jtag user command antti "Thomas Karolyshyn" <karolyshyn.t@ll.mit.edu> schrieb im Newsbeitrag news:raz5e.298$cr2.100@llnews.ll.mit.edu... > Hi, > > I'm looking in to programming a Cyclone device and it's prom via an embedded > processor. I've found documentation on how to load the FPGA it's self but > not the prom. > > Has anyone dealt with this? Is there any ideal setup via the JTAG > connection? > > -Tom > >Article: 82211
Hi, Does anyone know what this switch really does? They don't explain as to what is in that directory. Does it mean that if you have an "`include" directive in your verilog code that XST will search that directory for the files? Thanks Dave ColsonArticle: 82212
<Sudhir.Singh@email.com> schrieb im Newsbeitrag news:1112937690.795304.253750@l41g2000cwc.googlegroups.com... > Hi Group, > I am using SPARTAN3 CLBs to divide a clock. I can't use the DCM because > the input clock is less than the minimum required by the DCM. Does > anybody know how to calculate/estimate the jitter on the divided clock? > > I am using the following VHDL code to divide by 2 > > div2: process > wait until Clkin'event and Clkin = '1'; > Clkdiv2 <= not Clkdiv2; > end process; > > Thanks in advance. Are you serious? This just a plain 2:1 divider, more or less jitter free (yeah yeah, something in the 50 ps range maybe due to noise on VCC and other things that disturb the clock input) . Regards FalkArticle: 82213
I wrote: > What MIPS invented and patented was the idea that instead of having the > hardware deal with unaligned bus accesses, they require software to > issue *two* instructions to do an unaligned access. One does the > "left part" and one does the "right part" of the word. Everett M. Greene writes: > This must be a misstatement or it's a ridiculous patent. > How can a patent be issued for NOT doing something? Of course you can patent something new that eliminates the need for something old! The patent is on the two instructions, and their use in eliminating the need for the usual hardware that would support unaligned access. > There's also the "obvious to anyone experienced with > the technology" thing. The use of the two instructions in question seemed like something that wasn't obvious when I first saw them. I think it passes the obviousness test. However, the patent office has a much lower bar for obviousness than you or I would have. Even though I think this patent was reasonable, they certainly grant many others that I don't think they should. EricArticle: 82214
Hi, I am trying to work with ML310 virtex II pro development board and I have pretty much stuck with the basic stuff, Can someone please tell me: 1- How many way one can load an image into the DDR DIMM? is this correct that all accesses to the external memory (the DDR DIMM) have to go through the PPC? if not, what are my options? 2- Ideally I would like to read the images from a camera and store them onto the ddr dimm, what's the best way to do that? I greatly appreciate any help, thanks, vikiArticle: 82215
Hi, I have this board. Now I want to implement my first project. Are there any sample projects that work for this board? regards, BenjaminArticle: 82216
jon@beniston.com (Jon Beniston) writes: > Embedded FLASH in 90nm is years off, Why can't one use 130nm (or even 180nm) embedded flash in a chip design that uses 90nm for everything else? (Yes, I'm largely ignorant of chip design issues at that level. I usually only do HDL design.) EricArticle: 82217
Ray Andraka wrote about reverse-engineering ASICs based on behavior vs.
analyzing the mask layout:
> it may take a bit of work to ferret out all the operation, but it is
> likely still easier than trying to reverse engineer from masks.
Speaking of such things, I have a number of old chips from which I want
to extract masked ROM and PLA contents from. Since those are very
regular strutures, and they in parts with single layer metal in 5 micron
and larger geometry, it should be fairly easy. In fact, here's an
example of someone doing this:
http://www.pmonta.com/calculators/hp-35/
He extracted code from 10 micron PMOS masked ROMs that were packaged in
metal cans, by the simple expedient of removing the top of the can with
a dremel tool or the like.
I want to do basically the same thing with other chips from that era,
but they're in plastic DIP packaging. I don't want to mess with
high-temperature fuming nitric acid and such things. Can anyone
recommend a lab that will do this, and take photomicrographs, at
a "reasonable" price?
Before everyone jumps on me about piracy, I'll explain that the ROM
and PLA code in question is NOT copyrighted.
Thanks!
Eric
Article: 82218In article <qhaco912bi.fsf@ruckus.brouhaha.com>, Eric Smith <eric@brouhaha.com> wrote: >jon@beniston.com (Jon Beniston) writes: >> Embedded FLASH in 90nm is years off, > >Why can't one use 130nm (or even 180nm) embedded flash in a chip design >that uses 90nm for everything else? (Yes, I'm largely ignorant of chip >design issues at that level. I usually only do HDL design.) Requires significant additional process steps, which may be incompatable with the 90nm process. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 82219
Hi, I have found this on the Xilinx-website: The Virtex-II Pro Developer’s Kit is a compilation of three CDs. The first CD, labeled “Virtex-II Pro Developer’s Kit, March 2002” contains reference systems, hardware/software IP, and documentation. The second CD, labeled “GNU Software Developer’s Tools for PowerPC®, March 2002” contains a set of tools for building software applications. The third CD, labeled “Foundation ISE 4.2I Eval” contains the Xilinx FPGA Implementation Tools. The problem is, that I don't have those 2 cds because I got the starterkit from my university... Is there any source on the web to get the cds? regards, BenjaminArticle: 82220
<Sudhir.Singh@email.com> wrote in message news:1112939292.255805.314940@l41g2000cwc.googlegroups.com... > Hi Antti, > My clock frequency is 10.84MHz. I tried to use the CoreGen on Xilinx > ISE to create the DCM component but it didn't let me. It gave a error > message that the minimum clock frequency was something like 25MHz. > Have you used the CoreGen or manually done DCM settings? > > Thanks At 184.5 ns per Unit Interval, what additive jitter do you consider "large" or "small?" If you are using the 5.42 MHz generated clock to produce a spectrally pure clock for an external device, just what *is* your sensitivity? Keep in mind that FPGAs are not precision analog components. The effect of nearby signals on the same I/O bank will be felt on the jitter of any clock that goes through that I/O bank. These effects are either insignificant or deadly depending on what you're doing with the "jitter."Article: 82221
Consider sticking with normal vias in your BGA. If you have a full matrix of balls for the part, you can route the pin escapes away from the center providing a crosshair of board are where decoupling can be added. Microvias seem a bit extreme for your first journey into multiple ground planes. If you use tiny 0402 caps with pick & place machines, you can stuff a bunch of caps underneath. It may seem like 0402s are a mess to get involved with but I would think this is a better ($$) route than microvias. You can have connections to both ground planes with all ground vias. For EMI and signal integrity, the multiple connections are necessary to keep the return current paths on one plane from having to find a return path to the other plane. "Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message news:nal5e.9777$6k4.878787@news20.bellglobal.com... > Hello all, > > I have a question regarding the layout of a BGA packaged FPGA. For the first > time I am using multiple ground planes, and I am curious if when routing the > ground balls from the BGA package, do I need to have a via that attaches to > both ground planes, or is having it attach to one plane directly under the > package enough, as long as there are vias elsewhere that tie the two planes > together. I would ideally like to use blind vias for the BGA layout so I can > get components on the underside of the PCB as well without any through hole > vias getting in the way. My satckup is as follows: > > 1 - signal/components > 2 - ground plane > 3 - signal > 4 - signal > 5 - power plane > 6- ground plane > 7 - signal > 8 - signal > 9 - power plane > 10 -signal > > I was planning on mounting the caps underneath the BGA package on the > underside, again using blind vias so there is more room for signal routing, > but I'm considering mounting them around the package on the top side now. > 100 MHz is the highest frequency signal anywhere on the board, and most > signals are 50 MHz speed (or there abouts). > > Any comments would be greatly appreciated. > > Thanks, > > Jason > > jberringerNOSPAMatNOSPAMsympatico.ca (remove NOSPAM) > >Article: 82222
Jason, Comments inline... "Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message news:PDy5e.23696$Fy3.1558386@news20.bellglobal.com... > Symon, > > Thanks for the response, I read the thread, very interesting, and I'll > have > to speak with my fab house about microvias. You mention lots of room > underneath the BGA for the decoupling caps, but if they are connected > (similarly to the BGA) with thru-hole vias for ground then that would > impact > on the space as well, unless you are using blind vias for the decoupling > caps on the bottom of the PCB? There would be lots of vias to stuff in > there > with the BGA grounds (thruhole vias) and the capacitor grounds and powers > (thruhole vias). > Correct, you need to use through vias for the ground and power. But you need those through vias to connect the BGA balls up anyway, so you're getting double the use for each one. > I have thought that I might be able to go to an eight layer PCB using > blind > vias with the following stack up > > 1 - signal/component > 2 - mixed pwr plane > 3 - ground plane > 4 - signal > 5 - signal > 6 - 3.3V power plane > 7 - ground > 8 - signal/component > > If I use blind via (layer 1 -3) for power and ground for the BGA then I > have Hmmm, layer 1 to 3 blind vias = expensive. More than one drilling process or more expensive double layer microvias. And bad SI because the return currents can't get from one ground plane to the other near the FPGA. > lots of room to route signals on layers 4,5, and 8 provided I place > decoupling caps on layer 1 around the package (FG256). However this then > goes against the connecting ground planes theory, unless I add lots of > ground vias to join the planes after I route the signals. I do have quite > a > few components for the 3.3V so I don't know if I want to give up that > plane, Give it up! You'll never look back. > however my layer 2 is a mixed plane layer (1.8 and 2.5 volts) with more > than > enough room to accommodate signals or more 3.3V plane. I'm not sure on > which > is better since I have not ventured into this many layers (having multiple > ground planes) before. > > thanks, > > Jason If I was doing 8 layers, I'd do 1 - signal/component 2 - signal 3 - ground plane 4 - mixed powers 5 - signal 6 - ground plane 7 - signal 8 - signal/component I'd have microvias between layers 1 and 2. You'll be able to route out every signal ball of a BGA256 on layers 1 and 2 without a single through via. Through via every power and ground ball, connect the bypass caps on layer 8. Of course connect ground vias to all ground planes. Anyway, that's what I'd probably do. I hope it gives you some ideas. Cheers, Syms.Article: 82223
"John_H" <johnhandwork@mail.com> wrote in message news:KEB5e.33$NY6.188@news-west.eli.net... > Consider sticking with normal vias in your BGA. If you have a full matrix > of balls for the part, you can route the pin escapes away from the center > providing a crosshair of board are where decoupling can be added. > Microvias > seem a bit extreme for your first journey into multiple ground planes. If Extreme? Naahh. In at the deep end! ;-) You'll never go back! > you use tiny 0402 caps with pick & place machines, you can stuff a bunch > of > caps underneath. No, the through vias for all the signals have used up all the space. > It may seem like 0402s are a mess to get involved with but > I would think this is a better ($$) route than microvias. You can have Of course, 0402s are a given! 1uF ones. I mix them with 0805 22uF. Don't fall for all that different value bypass caps in the same size package crap. Also, the microvias save $$, they're cheaper than you think, and you need fewer layers remember. Talk to your pcb fab house. > connections to both ground planes with all ground vias. For EMI and > signal > integrity, the multiple connections are necessary to keep the return > current > paths on one plane from having to find a return path to the other plane. > Yep, spot on.Article: 82224
Hello
Yes, I used the "JTAG_Loader_ROM_form.vhd" file and made the changes to
include a reset signal.
But I think I maybe know what I made wrong.
After I ran the JTAG bat-file I pressed the reset button on the Spartan 3
Evaluation Board, and by doing that the FLASH memory contents was again
loaded into the FPGA (fith the original PicoBlaze ROM). :-/
I can't confirm this until Monday, but does it seem likely?
And what should I answer when the JTAG_loader.bat ask:
"How many JTAG devices are before the PicoBlaze FPGA in your chain ? >"
Should I answer 1 because in the iMPACT-tool the FPGA is the first device
and the second device is the FLASH-memory?
And when it asks:
"How many JTAG devices are after the PicoBlaze FPGA in your chain ? >"
Should I answer 1 because there is one devide after the FPGA in the JTAG
chain?
"Antti Lukats" <antti@openchip.org> skrev i meddelandet
news:d36dnk$p2o$00$1@news.t-online.com...
> where are you stuck?
> did you rename the jtag_loader_rom_form.vhd into rom_form.vhd and copied
> into the assembler dir?
> you should then get special rom file that includes BSCAN, if you now build
> the Picoblaze system
> and download that to the FPGA then the ROM should be accessible over JTAG
> using the supplied
> tools. I think the version as shipped doesnt work on V4 but I guess you
> should have got synthesis
> error if you are targetting V4
>
> or did you have problem converting the hex into XSVF?
> or did you have errors during XSVF file execution?
>
> Antti
> http://gforge.openchip.org
>
>
> "Elektro" <blabla@bredband.net> schrieb im Newsbeitrag
> news:4256b12d$0$43988$14726298@news.sunsite.dk...
> > Hello
> >
> > I'm trying to use the PicoBlaze JTAG Program Loader supplied with the
> > PicoBlaze package to download a new ROM contents. But I don't seem to
get
> > the new ROM down to my FPGA.
> >
> > Do any of you have some advise?
> > Thanks
> >
>
>
>
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