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On Sat, 19 Mar 2005 23:44:24 +1100, "Alex Gibson" <news@alxx.net> wrote: >Another option would be to buy a textbook with or by itself >the student version of 6.3 which is same as full ise but without >any support. >http://www.amazon.com/exec/obidos/tg/detail/-/0131858394/qid=1111234703/sr=2-1/104-7812736-3159945?v=glance&s=books > >Alex > I have bought the Xilinx FPGA S3 Starterkit , and have a ISE Webpack , and a time limited ISE 6.2i Am i understanding thic correct , that the above is a full ISE6.3i with no timelimit ??? , and i guess the "No support" means no upgrade path possible or ???? Regards CarstenArticle: 81251
"Preben Holm" <64bitNOnoNOSPAM@mailme.dk> schrieb im Newsbeitrag news:423d4aae$0$252$14726298@news.sunsite.dk... > Hi everyone... > > Why is my statemachine not functioning the first many clock-cycles of > the post-map simulation? Because global reset is active. Regards FalkArticle: 81252
Thank you for your reply. My data is plain text .txt files, so there are something amiss from converting my text file into ELF, and when I?generate?RAM from coregen, writing BMM?file?also?becomes?a?problem.? "Nju Njoroge" <njoroge@stanford.edu> wrote in message news:1111288045.147300.233670@l41g2000cwc.googlegroups.com... > > Lin MuIin wrote: >> My scheme is like this, I generated a 32Bit*1024word DPRAM with > Coregen >> and inserted that into my design to store some initialization data. > After I >> generated >> bitstreams of the entire design, I will use DATA2MEM to generate > bitstreams >> according to each different initialization. The initializationdata > are >> stored in hex >> format, 4bytes/1024rows in text files. >> >> I failed to find any information on how to generate ELF/DRF/MEM > files, and >> I have difficulty coding BMM file. Where can I find such reference >> materials? > Try this link: > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&key=dr_dt_data2mem > > Or a direct link to the PDF is: > > http://www.xilinx.com/ise/embedded/data2bram.pdf > > This is a reference that details what you are trying to do. > Good luck, > > NN >Article: 81253
Preben Holm wrote:
>
> Yeah, but I'm not able to break a state machine into smaller pieces, and
> this is even though quite simple!
There, I agree with you entirely !
Making many separate synchronous blocks "talk" to each other is
not a good idea (it does waste usually precious clock cycles).
I've seen people write a counter outside the one-process FSM
which used and controlled it : a mess !
My recommendation = if you do it in one-process : don't split it.
> How do you like my new design (single-process)
> ----------------------------------------------
Much better !
Just a few comments
> entity holdoffcontroller is
> Port ( clk : in std_logic;
> reset : in std_logic;
> save : in std_logic;
> trig : in std_logic;
> read : in std_logic;
> holdoff : in std_logic;
> hold : out std_logic := '0';
-- I wouldn't initialize the output in the port.
-- nice trick for optional inputs though.
> state : out std_logic_vector(4 downto 0));
> end holdoffcontroller;
>
> architecture Behavioral of holdoffcontroller is
-- I would rather use RTL rather than "behavioral" (cosmetic)
> type states is (stateStart, stateWait, stateTrigger, stateHold,
> stateRead);
> begin
>
> STATEMACHINE: block
> signal current_state : states := stateStart;
No. It's "bad" enough this initialization does exist in VHDL
without you writing it....
The issue of integer range & enums is that they are "automatically"
initialized (at simulation) with the leftmost value, so you won't
notice they may not be in hardware (synthesis).
But since you've coded the async reset (almost) correctly,
it's not an issue.
Just don't initialize signals at declaration in RTL code.
> begin
> stateRegister : process(clk, reset)
> begin
> if reset = '1' then
> current_state <= stateStart;
Bad bad !
you forgot to reset all the FlipFlops you've created below !
(hold in this case, but any other signal on left side of an
assignment should be reset also).
This is bad because reset will show up in the datapath as an enable :-(
> elsif rising_edge(clk) then
> current_state <= current_state;
Don't write this line (assign to self). It's useless.
The 2-process version "next_state <= current_state" was necessary
to code the "implied else" and avoid latches, but you don't need
this in the one-process style.
>
> case current_state is
btw, you don't need the "current_" prefix anymore, used when you have two
different signals, currunt_state (FF otput) and next_state (FF input).
That's just cosmetic.
> when stateStart =>
> --holdoff_counter_enable <= '0';
> --holdoff_counter_reset <= '1';
> etc...
.../...
>
> process(current_state)
> begin
state <= (others=>'-'); -- play it safe !!!
> case current_state is
> when stateStart => state <= "00001";
> when stateWait => state <= "00010";
> when stateTrigger => state <= "00100";
> when stateHold => state <= "01000";
> when stateRead => state <= "10000";
> end case;
> end process;
> end block;
I would at least make a default assignment on top to (others=>'-')
as shown above, in the hope that the synthesis tool will create
an optimized one-hot decoder in any (encoding method) case and
will never create latches.
It's still a VERY good idea to check what synthesis will do (should
be just wires here).
Last comment : I would use block / endblock only to restrict
the scope of some signals. Since the state information is global
(it even goes up in the hierarchy), then the block section
(imho) is not useful here.
Hope this help,
Bert Cuzeau
Article: 81254zalzon wrote: > Hello all. > > I am interested in learning about FPGAs but don't know much about > where to start. Should I get Xilinx FPGA starter kit? Would that be > helpful for taking me by the hand and going through the basics? > > Are there any other things a beginner should be aware of? > > Please advise. > > Thanks We have -I think- a very nice and complete Kit to start with, and we have designed also a set of practical and progressive exercises. I don't think other Kits do this today. We start easy (BCD counter), and end up with a nice design including the design of an UART and a RS232 D.E.S. crypting engine. Initially, I thought the teaching material would be reserved to schools and our Educational Kits, but we may make it availaible to individuals. When you'll have exhausted all Tornado features, you'll be likely very familiar with HDL design :-) See : http://www.alse-fr.com/Tornado/torn_educ_us.pdf We sell it for 295 €uros (the board) The design software is free and we deliver ready-to-use scripts and examples so you can design & downnload your first application in just a few minutes after unpacking the Kit, without launching any tool other than a text editor (there is even one in the kit). You can then focus on learning VHDL (or Verilog) first and learn tools and detailed methodology after, progressively. HDLs are not like "ordinary" programming languages at all, the concepts behind them are not intuitive, and they are difficult to learn by try and guess. You can also find some simple and free HDL code at http://www.alse-fr.com/English/ips.html This code will indeed work on Tornado, but also on all other boards and FPGAs available. If you look for even cheaper board with some interesting features, you may consider the LiveDesign Evaluation boards, but indeed many others are available. But my suggestion is to find a _good_ learning source for VHDL or Verilog and start coding and testing on a bord all along the way. And make sure you always simulate your HDL code ! There are things and concepts which can only be explained or verified by simulation. HDL coding is a incredible source of enjoyment and creativity, and the learning curve _can_ be smooth and easy. Good luck, Bert CuzeauArticle: 81255
I am trying to capture RS232 data on the xilinx spartan 3 fpga on the spartan 3 development board..I have had no luck yet..For some reason, i am not able to sample the incoming data.I am using a clock that is 16X data rate of incoming rate which is 9600 Hz. I have a 16 wide shift register set to X"FFFF" and i sample the input until my shift reg is x"00FF" so i know for sure that i am at the center of my start bit or somewhere close to it.then i have a state machine that goes and counts every 16 cycles and gets one bit of information. any ideas or literature that i can use here would be helpful..thanks.Article: 81256
We generally avoid doing a true RPM and just use RLOC attributes directly in vhdl. Often if you are doing an RPM you are instantiating primitives anyway so you can easily add the rlocs to the generate loops. The logic still appears as an RPM in floorplanner if you want to place the blocks of rloc'ed logic. Also you can apply LOC attributes to RLOC'ed logic. This way there are no special steps in the flow. You just pour your vhdl into the synthesis tool like always. Pete "Tim Good" <elp04trg@sheffield.ac.uk> wrote in message news:d168dv$lr2$1@hermes.shef.ac.uk... > Hi, > > I am trying to create my own reusable Relationally Placed Macro (RPM) > using ISE 6.3.03i without much success. I have followed the procedure > defined in the "Creating a reusable RPM core" manual page without much > luck. > > I am using the "Write RPM to UCF" command in the floorplanner to create > the UCF (RLOC'ed) and NGC file. This works fine for a single > instantiation connected to the package pins but not for the desired > general case of a macro used several times internally to a larger design. > > I appear to be getting IIOB & OIOB objects in the NGC netlist for the RPM > and cannot get NGDbuild to recognise when it has already used slices in > the case where more than one instance is created (suspect not recognising > boundary area for RPM?). > > If any one has any ideas or a simple example (VHDL preferred)...... > > Many thanks, > > TimArticle: 81257
The CIC core is often used after a DDC. It gives large decimations at low cost but does usually require a cleanup FIR filter following the CIC. "Nemesis" <nemesis@nowhere.invalid> wrote in message news:20050319162156.1706.10636.XPN@orion.homeinvalid... > Hi all, > I'm implementing a Digital Down Converter for Virtex II pro device. > > I think I'll not use the builtin DDC IP core because I'm using this > project to learn something about FPGAs and VHDL. > > Essentially I have samples coming from an A/D at 64MHz. The signal is > bandpass, centered at 112 MHz and it can have to different bandwidth > 5MHz and 25MHz. > > I've already implemented in VHDL the I and Q components splitting, now I > have to filter these signals with low pass filter and decimate the > sequence. I'm going to use the "MAC FIR Filter" IP core (shipped with > Xilinx ISE). > > I have some questions, I'm a newbie digital designer so please consider > this :-) > > 1) using a polyphase decimator is exactly the same of using a > single rate filter and then downsampling the output? > > 2) I need the same filter on both I and Q channels, so I think I could > set the core to use 2 channels, but I'm not sure how it works, is it > realized with time sharing? I'd need the two samples I(k) Q(k) at the > same time. > > Thank you all, and > -- > I tried switching to gum but I couldn't keep it lit. > > |\ | |HomePage : http://nem01.altervista.org > | \|emesis |XPN (my nr): http://xpn.altervista.org >Article: 81258
"fpgawizz" <bhaskarstays@yahoo.com> schrieb im Newsbeitrag news:af5db4b897d6982d4886d010d81b0b01@localhost.talkaboutelectronicequipment .com... > I am trying to capture RS232 data on the xilinx spartan 3 fpga on the > spartan 3 development board..I have had no luck yet..For some reason, i am > any ideas or literature that i can use here would be helpful..thanks. Have a look at xapp 223. Have a look at www.opencores.org Regards FalkArticle: 81259
Mentre io pensavo ad una intro simpatica "pedro uno" scriveva: > The CIC core is often used after a DDC. It gives large decimations at low > cost but does usually require a cleanup FIR filter following the CIC. Yes, I read this, but I don't need a large downsampling. Probably I'll need a 10 factor for the 5MHz signal. But I still have doubts on the two topics I wrote in the previous article. -- Ambition is a poor excuse for not having enough sense to be lazy. |\ | |HomePage : http://nem01.altervista.org | \|emesis |XPN (my nr): http://xpn.altervista.orgArticle: 81260
Thomas, The maximum speed of the LVDS buffers is a good question for me to try to shed some light on in this forum. The LVDS buffers (both input, and output) are built from the 0.25 micron gate oxide transistors we use for IO in all devices since Virtex II Pro. These same devices are used for the 3.125 Gbs MGT front ends, so the transistors themselves are extremely quick. But, it is all in the sizing, and a regular IO is burdened by having to support 34 other IO standards. These LVDS IOs were not designed to work beyond 1 Gbs. Not that we did anything intentional to make them slow, we just didn't model them at all corners above 1 Gbs because is was not a requirement. As such, the interconnect and logic is not sized for Gbs speeds, either into, or out of, the IOB. Why isn't it a requirement? Well, the fabric can't handle it anyway. By that, I mean it is not the IO that is the limiting factor for any given standard. Take Aurora, or SPI POS 4.X, or some other IO protocol and signalling 'standard' for example. You must have a clock synchronization system, data multiplexing/demultiplexing that meets the standard. And also a core with the state maqchines, CRC, BRAM FIFO's, etc. In Virtex 4 (my favorite subject) we have the Source Synchronous IO blocks for every I/O pin which is a serdes for each pin: this easily matches Gbs speeds on DDR IO pins to the fabric at 1/2, 1/4, 1/8 (etc) speeds along with allowing for fixed or dyanamic bit eye slicing to get the best possible link. That hardware is definitely limited by the LVDS. The LVDS in V4 is running at 1.4 to 1.5 Gbs (spec'd at 1 Gbs), but we haven't characterized it over all corners, voltage and temperatures. We just may, but only after we have the entire interface designed to support it. No reason to have fast IO if there is nothing to support it. The opposite is also true, a fast core is useless without the fast IO. Basically, if you want Gbs performance, we have a cost effective part for that, the Virtex 4. Spartan 3 and 3E (identical 90nm technologies) are intended for large volume low cost applications below ~300 MHz global clock speeds. The triple oxide technology in V4 provices us with a substantial increase in interconnect performance required for 500 MHz clocked logic. Spartan 3 and 3E don't have that Ace up their sleeves. Spartan 3, and 3E are intended to address the best IO/$, and the best logic/$ sockets. I would not distinguish between them on the basis of performance or speed: they represent vitually identical devices cost optimized for the two different application spaces (logic vs. IO). Austin Thomas Entner wrote: > When we are talking about IO: Does anybody (i.e. Austin ;-) know the max. > LVDS-transmit-rate of Spartan 3E, slowest speed-grade? > > Regards, > > Thomas > > www.entner-electronics.com > > "Luc" <lb.edc@pandora.be> schrieb im Newsbeitrag > news:lmmm31lrm84tielfem34qtqdmfj9eu8gpg@4ax.com... > >>Ben & Paul, >> >>Thanks for the feedback. >>I wonder what X & L could add to their defence. >> >>What about DDR or DDR2 support? >>This is certainly somthing I'm looking for. Multipliers are benificial >>but not a necessity. >> >>Regards, >> >>Luc >>On 18 Mar 2005 13:55:56 -0800, "Paul Leventis" >><paul.leventis@utoronto.ca> wrote: >> >> >>>Hi Luc, >>> >>>I don't have much to add -- Ben has covered most of the high points. >>> >>> >>>>Has someone seen samples yet, knows something more how they compare >>>>(performance, pricewise). >>> >>>On a performance front, you will find that Cyclone and Cyclone II have >>>a significant performance advantage over Spartan-3. We're talking >>>50-60% (core performance on 100+ designs, comparing fastest speed grade >>>to fastest speed grade using best-possible software settings). >>> >>>But don't take my word on it. Download our freely available Quartus II >>>Web Edition and give your design a whirl in Cyclone/Cyclone II. Do the >>>same for Spartan-3. >>> >>>Regards, >>> >>>Paul Leventis >>>Altera Corp. >> > >Article: 81261
Really off-topic, Since we are on the rovers, (the Virtex 1000's, 12 on each rover), I watched the JPL website every day in the early days after landing. One day, I missed looking at the downloads. The next day, one of the pictures had a set of Mickey Mouse Ears on it! Wow! Was I impressed? Do they watch the Disney Channel up there? Turns out the grinding tool had ground out three circles the day before, creating the classic set of 'ears.' AustinArticle: 81262
>>I am not sure but is this got something to do with the DONE pin not >>going high. I dont know abt platform studio but then with Project >>navigator there is a setting which drives the done pin high that is if >>the done pin in the circuit is not connected to a pullup resistor. >[...] > >Yeah, but I can't seen to find any settings that does this. I am >pretty new to this. :) >Anyways, I powered off the board and soldered a 10kOhm resistor from >the DONE-pin to Vcc. And it actually worked after I powered it on >again and programmed it. > >>Hope this helps. >[...] > >I hope so too. Only time will show if the pull-up resistor did the >trick. ;-) [...] Damn, it did not work. After some hours it went mad at me again. Does anyone have any ideas on what to try out? -- HenrikArticle: 81263
Paul Leventis (at home) wrote: > Hi Vax, > > You will need three voltages for your S3 (1.2, 2.5, and 3.3V), while for > Max > II you'll need just the one (3.3V). And you won't need a seperate > configuration RAM. Also, I'd look into those costs again. The EPM1270 > will be in production shortly and should be cheaper longer term than > low-end FPGAs such as S-3 since Max II has a smaller die. Thanks. I decide to go with EPM1270 because of its single power supply and on chip configuration flash. vax, 900 > > Regards, > > Paul Leventis > Altera Corp.Article: 81264
On Sun, 20 Mar 2005 11:00:27 -0500, fpgawizz wrote: > I am trying to capture RS232 data on the xilinx spartan 3 fpga on the > spartan 3 development board..I have had no luck yet..For some reason, i am > not able to sample the incoming data. What does it mean in this case to not be able to sample the incoming data? That statement is not clear at all. > I am using a clock that is 16X data > rate of incoming rate which is 9600 Hz. > I have a 16 wide shift register set to X"FFFF" and i sample the input > until my shift reg is x"00FF" so i know for sure that i am at the center > of my start bit or somewhere close to it.then i have a state machine that > goes and counts every 16 cycles and gets one bit of information. > > any ideas or literature that i can use here would be helpful..thanks. Have you tried simulating the circuit? Have you tried looking with an oscilloscope at the signal you are feeding to the FPGA? --MacArticle: 81265
The USB ports on the ML310 board are enabled when running the Linux demo on the CompactFlash card. You can find information on how to build your own Linux system by visiting the ML310 web page at http://www.xilinx.com/ml310 and http://www.xilinx.com/products/boards/ml310/current/index.html. XAPP765 is also a good starting point for Embedded Linux on Virtex-II Pro (and Virtex-4 FX), see http://www.xilinx.com/bvdocs/appnotes/xapp765.pdf Using the USB ports from standalone software is much more challenging as you would have to write device drivers for the ALi south bridge as well as code for the USB stack. - Peter more wrote: > Hello, > > I am doing my thesis on Xilinx ML310 board. My target is to > realise the real-time image processing. First I have to find the port > where I can input the captured data. I am going to use the usb port on > MD1535D+ south bridge. To access this south bridge I need to access > the PCI bus since it is connected to the PCI. I have installed the > PCI v3.0 logicore but when I create a project, I can't find this PCI > v3.0 logicore to add into my project. Does anyone know how to access > this PCI v3.0 logicore? > > Much appreciate for your kindly help! >Article: 81266
fpgawizz wrote: > I am trying to capture RS232 data on the xilinx spartan 3 fpga on the > spartan 3 development board..I have had no luck yet..For some reason, i am > not able to sample the incoming data.I am using a clock that is 16X data > rate of incoming rate which is 9600 Hz. > I have a 16 wide shift register set to X"FFFF" and i sample the input > until my shift reg is x"00FF" so i know for sure that i am at the center > of my start bit or somewhere close to it.then i have a state machine that > goes and counts every 16 cycles and gets one bit of information. > > any ideas or literature that i can use here would be helpful..thanks. > Your data is probably bouncing a little bit on the input -- UARTs usually have some sort of a majority vote system to detect a bit, like best two out of three. You're probably much better off just looking for three consecutive high bits, or two out of three, and start your clock at 8. With your method you'll reject 0x01ff, 0x007ff, etc., which would still indicate the onset of good data. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 81267
It looks like the closest alternative for the EP2C35 is the XC3S1500 or the EC33 (I don't need the multipliers). The first two, real 90nm parts, the last a 130nm devices at 90nm price. I was looking at implementing a DDR400 or DDR333 interface, and according to the different datasheets and the posting, only the ECP33 will be able to support this. This makes the choise not so obvious. But probably I can live with DDR266. I guess, some discussions with my local distis and a short evaluation will bring the solution. Thanks for your posts, Luc On Fri, 18 Mar 2005 15:14:06 -0800, Austin Lesea <austin@xilinx.com> wrote: >Well, > >Suffice it to say, I don't agree with Paul, but that should come as no >surprise. > >Spartan 3S100E was just announced, so to ask if a 3S1500E is sampling is >a bit like asking if we are ready to go visit Mars. > >Seriously, announcement of the first available part usually means that >the rest of the family is three to six months from even being taped out >(for us, or Paul). > >Announcement of the first part into production also means that the time >till all parts are in production is out from three to six months (again, >for us, or Paul). > >Sometimes we do better than that. Sometimes they do better than that. >Sometimes we both do worse. And suffer for it. > >Depends on a lot of factors: are they any errata to fix? how many >layer changes need to be made? is the process yielding? have we passed >the process qualification? have we passed the product qualification? >do we have parts ready to ship? so on and so forth. > >For example: the 2S60 was announced as having received wafers on June >2, 2004. > >http://www.altera.com/corporate/news_room/releases/releases_archive/2004/products/nr-stratix2_sampling.html > >Then, they just recently admitted they will ship the final production >version of that 2S60 part with the Iccint surge current fixed by the end >of this month (3/31/2005). I am likely to believe this, as we just >tested the 2S90, and the Iccint surge is all gone. > >We announced the 4VLX25 on 6/28/2004 (lagging Altera, but we actually >shipped five parts on boards on this date and the customer was USING them!). > >http://www.xilinx.com/prs_rls/silicon_vir/0480v4shipment.htm > >Then, we just recently announced we are shipping production on this part >1/31/2005: > >http://www.xilinx.com/prs_rls/silicon_vir/0517v4prodqual.htm > >So, 9 months for a 2S60 from announcement of first wafer to production >(unconfirmed, as it isn't 3/31 yet), and 7 months for the Xilinx 4VLX25 >(confirmed). > >Not much of a difference there. > >If you go back and track every product announced, to every ES, to every >product released to production, you will find a remarkably similar time >line. After all, both Xilinx and Altera use world class fabs (UMC and >TSMC), and both use a leading edge process, and the differences will be >mostly related to factors that are totally random in nature (if we are >going to be honest about it). > >Go talk to your Xilinx FAE, and get the timeline for what you need. > >Oh, and take the performance boasts (for these low cost parts) from >everyone with a grain of salt. Until you see what your needs are, you >are unlikely to be able to evaluate if there is even a difference in >performance, and if that performance difference even matters for your >application. > >Sure, Spartan 3 (and 3E) have the 18X18 multipliers. And Altera has >elements they are proud of in Cyclone 2. > >But just like Virtex 4 vs Stratix 2, you are going to have to wade >through a lot of very technical information if you are trying to compare >benchmarks. Best you test your application, regardless. > >AustinArticle: 81268
Mac I am sending data through RS232 from visual basic to Com5. When i send chr(5) I see "11111001". now I am not sure if i am actually sending that data or if the data i recived in my FPGA is wrong because my sampling logic is wrong. I just dont have an application i can use where i can just send binary data from my PC to the serial port.Article: 81269
fpgawizz wrote: > I am trying to capture RS232 data on the xilinx spartan 3 fpga on the > spartan 3 development board..I have had no luck yet..For some reason, i am > not able to sample the incoming data.I am using a clock that is 16X data > rate of incoming rate which is 9600 Hz. > I have a 16 wide shift register set to X"FFFF" and i sample the input > until my shift reg is x"00FF" so i know for sure that i am at the center > of my start bit or somewhere close to it.then i have a state machine that > goes and counts every 16 cycles and gets one bit of information. > > any ideas or literature that i can use here would be helpful..thanks. > If it's for education or hobbyist use, you can try our UART IP which is free (under these conditions). All users have been extremely happy with it. It works in a few minutes, with all source code (portable), testbenches, behavioral model etc... Tested up to nearly one megabaud (reported by a Swiss user who was using a USB serial adapter w/o level translation). We don't have this 16x constraint so this IP is really optimized for high speeds and just any Xtal frequency. See http://www.alse-fr.com/English/ips.html Let me know. Bert CuzeauArticle: 81270
On Sun, 20 Mar 2005 16:23:24 -0500, fpgawizz wrote: > Mac > I am sending data through RS232 from visual basic to Com5. When i send > chr(5) I see "11111001". now I am not sure if i am actually sending that > data or if the data i recived in my FPGA is wrong because my sampling > logic is wrong. I just dont have an application i can use where i can just > send binary data from my PC to the serial port. This doesn't answer any of my questions. Did you simulate the design or not? If the design doesn't behave as expected in a behavioral simulation, then there is little hope it will work when downloaded into the FPGA. Personally, I would never forgo simulating an FPGA design. Did you use an oscilloscope to look at the data coming out of the RS-232 transceiver or not? You have an idea in your head of what the waveform coming out of the transceiver should look like, right? How does the waveform in your head compare to the oscilloscope trace? You do have an RS-232 transceiver in the design, right? You wouldn't just hook up a serial line to the FPGA, would you? --MacArticle: 81271
Alex Gibson wrote: > http://www.xilinx.com/products/spartan3e/s3eboards.htm Looks interesting. > webpack is free > edk is not, supposedly you get an eval copy when you buy > an S3 starter kit from Xilinx > They charge for it US$450 ? > The eval version is 30 days only I think ? I'm grateful to Xilinx and Altera for making their design entry and synthesis tools available for free. I wish they'd do the same for their EDK (but then, if they did, I'm sure I'd also want a free MAC, or PCI core). Thanks for all the links Alex. I'll most likely get the larger Digilent board, and forget about microblaze. A shame though. Thanks for taking the time to reply. Regards, Paul.Article: 81272
Cyclone2 will be good Paul Leventis (at home) wrote: > >> On a performance front, you will find that Cyclone and Cyclone II have > >> a significant performance advantage over Spartan-3. We're talking > >> 50-60% (core performance on 100+ designs, comparing fastest speed grade > >> to fastest speed grade using best-possible software settings). > > > > BTW, the Cyclone manual says that the highest speed of > > an M4K RAM bank is 200MHz, but Quartus estimates it to > > about 250MHz (Cyclone 1C6, speed grade 6). So, which > > information is right? > > Always trust the latest version of Quartus -- the datasheet is supposed to > follow whatever we put in the software, not vice versa. I will check into > this and get the datasheet corrected if neccessary. > > Regards, > > Paul Leventis > Altera Corp.Article: 81273
Has anyone checked out the new TI power supply for FPGAs, the TPS75003: http://focus.ti.com/docs/prod/folders/print/tps75003.html I was considering it for a potential Spartan-3E design and was looking for feedback from anyone who has sampled it or knows more about it. In particular, I was wondering if the reference design on page 7 of the datasheet was well suited for the -3E, or if anyone recommended other parts or modifications. Thanks :)Article: 81274
Paul Marciano wrote: > I'm grateful to Xilinx and Altera for making their design entry and > synthesis tools available for free. I wish they'd do the same for > their EDK (but then, if they did, I'm sure I'd also want a free MAC, or > PCI core). Just as a random interjection, you can actually get a free pci core.. At opencores.org :) 32/33MHz only though... Jeremy
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