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You don't say what target technology you are using--if Xilinx then Chapter 3: LibXil Standard C Libraries of the EDK OS and Libraries Reference Manual (http://www.xilinx.com/ise/embedded/oslibs_rm.pdf) will help you. Paul Lina wrote: > > I want to add libc.a and libm.a into my project and use the the standand C functions such as doing float computing, malloc spaces, to deal with string, and so on. > > But there are some problems: > > 1. how to add the libs into my projects. 2. how to use the libm.a and libc.a. what fuctions do the two libs provide? what's the grammar to use the libs? > > Please help me. Thank you very much!Article: 84026
Benjamin Menküc wrote: > Hi, > > simulating behavior doesnt work. Modelsim gives me this: > > # ** Error: (vsim-3170) Could not find 'work.uut'. > # Error loading design > # Error: Error loading design > > with exactly the same configuration, simulating Post-Translate, Post-Map > and Post-Place all work. My testbench is instantiated as uut. You are going way off track in your approach. Modelsim has really bad error messages. The error message you got is a catch all error message :-). In all probability there is small mistake in syntax or settings. 1) One does not instantiate a test bench. Test bench is a place holder for your enitity under test and logic required to test the entity. "My testbench is instantiated as uut." did you mean that you have named your testbench as "uut"? 2) Did your test bench compile without any errors? > > regards, > BenjaminArticle: 84027
How big is your elf (Tools-->Get Program Size)--the stack and heap are not listed in this total so factor in those sizes? How big is the Microblaze LMB memory? How did you increase the LMB memory size, perhaps you didn't add enough. Is this design straight out of BSB or have you modified it? Paul Patrick wrote: > > Hi, > > I get the following error, I am not sure how to fix that. I have tried > increasing the memory size, but that doesnt help. > > mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section > .sdata2) > mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section > .sdata2) > mb-ld: section .data [00000000 -> 0000005f] overlaps section .text > [00000000 -> 0000109f] > make: *** [TestApp/executable.elf] Error 1 > > Any suggestions? > > CheersArticle: 84028
Hi, I have a virtex4 development kit (ML403) and I plan to communicate with a PC via rs232. I see that you have done some work in the field and I just wanted to know if you have made any progress and if you could give me any hints where to start. Thanks ///TeodorArticle: 84029
Brian, Get the ML450 board, or ask for the documentation. http://tinyurl.com/b2dmo Lots of scope shots are available (ask your FAE). or, http://www.xilinx.com/publications/prod_mktg/pn0010778.pdf (page 2) Or, go to one of our RocketLabs and measure it for yourself. As for the reflection, the LVDS transmitter is also a 100 ohm termination, so reflections are absorbed at the transmitter (when the LVDS is properly done and meets the specifications, which ours do). Anyone with an IBIS simulator can see all of the above happening, so I really don't want to take this any further - demanding to see scope shots of things is pretty pointless when the simulations are perfectly good (when they are done correctly). But, I am sure our Marketing Folks will be rolling our scope shots as part of pitch-packs, etc. for those who are unable or unwilling to do the SI engineering that their job requires of them. AustinArticle: 84030
Symon wrote: > "Symon" <symon_brewer@hotmail.com> wrote in message > news:4281198e$1_2@x-privat.org... > >>>- And how do you make the enable signal go on the global clock net? >>> >> >>You ask someone from Xilinx! I've not yet started my V4 design. I just >>remembered that from the marketing spiel we had. >>Cheers, Syms. >> > > Hmmm, I might have given you a bum steer there. I just looked at the FPGA > editor view of V4 and it seems there's NOT a path from the GBUFs to the CLB > CE. You can control a CE pin on the GBUF, but that's about as useful as a > chocolate teapot in this case. > Sorry about that, Syms. No you didn't bum steer... you were right initially. CE nets can be put onto a global clock network. Look at the CLB switch box in FPGA Editor again... each CE pin can be driven by a bounce pip (4 stubs in the middle right edge of the switch box), and these 4 bounces can all be driven by the GLK pips on the lower left edge of the switch box. There's your path. Cheers, Ajay Roopchansingh Xilinx IncArticle: 84031
Hi Brijesh,
Post-Translate Simulation works. However Behavioral Model simulation
still doesn't.
> 1) One does not instantiate a test bench. Test bench is a place holder
> for your enitity under test and logic required to test the entity.
> "My testbench is instantiated as uut." did you mean that you have named
> your testbench as "uut"?
my testbench is instantiated like this:
...
-- Instantiate the Unit Under Test (UUT)
uut: led_test PORT MAP(
...
Under properties in the Project Navigator I have entered UUT as instance
name. (it works for the other types of simulation).
>
> 2) Did your test bench compile without any errors?
since I have inserted a SRL16, it hangs now
SRL16_inst : SRL16
generic map (
INIT => X"0000")
port map (
Q => dcm3_rst, -- SRL data output
A0 => '1', -- Select[0] input
A1 => '1', -- Select[1] input
A2 => '0', -- Select[2] input
A3 => '0', -- Select[3] input
CLK => clk_ibufg, -- Clock input
D => not lvds_locked -- SRL data input
); <-- in this line
the error message is
# -- Compiling architecture behavioral of led_test
# ** Error: led_test.vhd(475): The actual for formal 'd' is not a
globally static expression.
regards,
Benjamin
Article: 84032Anyone?Article: 84033
Greetings, I am looking at an application that will provide an analog input signal in the 125 to 500 KHz frequency range, and wanted to convert it to a digital signal that would be processed by a Spartan 3 FPGA. I found two xilinx app notes that address issues related these areas (but based on Virtex FPGA): http://www.xilinx.com/bvdocs/appnotes/xapp155.pdf (Virtex ADC) http://www.xilinx.com/bvdocs/appnotes/xapp154.pdf (Virtex Delta-Sigma DAC) My other hardware requirements are low power (nanoWatt). I am wondering if you can help me in the following areas: 1. Is it possible to achieve these goals given the requirements (125-500 KHz input signal, low power consumption, Spartan 3)? Note: The input frequency cycles at 125 KHz. Thus my thought is if I can devise a circuit that perhaps operates at 500 KHz, that is sufficient tolerance to assume that within the 500 KHz range the 125 KHz can be assumed to be slowly changing or linear. 2. My thought is that it is possible to implement these using Spartan 3, but the cited links were to Virtex architecture. What concerns come to mind for the transition? 3. Reasonable expectations about the resolution/accuracy of such sampled analog signals? (a) For example, I am only able to discretize the analog input signal into an 8 or 10 bit resolution (meaning that 2^8 is 256 output values for the vertical axis, thus it is an expectation for the measure of round-off errors). (b) Eventhough the Spartan 3 can run at 50 MHz, the ADC would only be able to sample slowly changing signals (<20 KHz). 4. Reference to understanding basics about ADC (e.g books, web sites, etc)? Thanks, -HerbieArticle: 84034
The app notes are not limited to Virtex. You can use the same ideas on Spartan-3. What do you mean by nano-watt? The Spartan-3 consumes many milliwatts... Peter Alfke, Xilinx ApplicationsArticle: 84035
nanoWatt is a term that was used by microchip, and has the following specification: Low-Power Features: =B7 Standby Current: - 1 nA @ 2.0V, typical =B7 Operating Current: - 8.5=B5A @ 32 kHz, 2.0V, typical - 100=B5A @ 1 MHz, 2.0V, typical =B7 Watchdog Timer Current: - 1=B5A @ 2.0V, typical See also http://ww1.microchip.com/downloads/en/DeviceDoc/41200B.pdf Thanks, -HerbieArticle: 84036
Try to contact www.amirix.com They will have a new product based on Virtex4 (> FX40) Their boards cost a bit but are very good products Regards Uxe asoc35@dsl.pipex.com wrote: > Hi, > > I am looking for a Virtex 4 based FPGA development board with ideally a > PCI Express interface and at least a FX-100 Virtex 4. If anybody knows > of any vendors who have this or are working on this, please let me > know. > > Thanks, > > Sam. >Article: 84037
> I am looking at an application that will provide an analog input signal > in the 125 to 500 KHz frequency range, and wanted to convert it to a > digital signal that would be processed by a Spartan 3 FPGA. You're probably much better off just buying an ADC capable of sampling at whatever frequency you want, and connecting it to your FPGA through the converter's interface. You'll get much better performance and you won't have to do tricks to make the FPGA do something a standalone part will do much better and for less money. -aArticle: 84038
> The Spartan-3 consumes many milliwatts... As far as the Spartan-3 power requirements, that is fine as I am designing with this part already. The part cited in the xilinx tech notes suggested 24 mA LVTTL output buffer and a comparator. I was hoping to devise the external circuitry that had requirements in the nanoWatt range. (See also other post for description of nanoWatt). Thanks, -HerbieArticle: 84039
"Austin Lesea" <austin@xilinx.com> wrote in message news:d5t993$3041@cliff.xsj.xilinx.com... > > As for the reflection, the LVDS transmitter is also a 100 ohm > termination, so reflections are absorbed at the transmitter (when the > LVDS is properly done and meets the specifications, which ours do). > No. Not if this transmitter is a Xilinx FPGA with 12.5pF of parasitic capacitance. The high frequencies see a lower impedance, and so stuff relects back out of the transmitter, exactly the same as at the receiver. This is the point I'm trying to get you to understand. I tell you what, why don't you call that nice Dr. Howard Johnson and ask him? Here's a quote from National's LVDS manual. "In a good design the connector contributes 2 pF to 3 pF, the trace contributes 2 pF to 3 pF, and the device contributes 4 pF to 5 pF.The total load in such a design is around 10 pF. The flexibility of programmable devices comes at the cost of capacitance. National Bus LVDS products have an I/O capacitance of 5 pF. The I/O capacitance of a programmable device is approximately double or 10 pF. This increase in capacitance will lower the loaded bus impedance, thereby reducing the available noise margin and lowering the reliability of operation in the design." http://www.national.com/appinfo/lvds/files/ownersmanual.pdf > > Anyone with an IBIS simulator can see all of the above happening, so I > really don't want to take this any further - demanding to see scope > shots of things is pretty pointless when the simulations are perfectly > good (when they are done correctly). > I don't want to see scope shots, I agree I want to see a simulation 'done correctly'. I think I already have on Altera's website. Best regards, Syms.Article: 84040
Instead of instantiating using location use a direct connecting meaning instead of let say andgate andgate (o,a,b); use andgate anggate (.o(o), .a(a), .b(b)); This way the order is not important any more. The risk of using location is even higher as it can give misleading result. Assume for example that two input got swaped ... Have funArticle: 84041
On Tue, 10 May 2005 19:02:19 -0700, austin <austin@xilinx.com> wrote: >The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but >can it be used in a real application on a real board? Make up your mind Austin. On numerous occasions you have recommended that people run simulation of I/O systems to see what should happen, and you have recommened the IBIS models. To suggest that Altera does not know how to run simulations is insulting. Enough! Philip Freidin =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 84042
"Ajay Roopchansingh" <ajaytr@donotspam_xilinx.com> wrote in message news:d5t9ck$30d1@cliff.xsj.xilinx.com... > > No you didn't bum steer... you were right initially. CE nets can be put > onto a global clock network. Look at the CLB switch box in FPGA Editor > again... each CE pin can be driven by a bounce pip (4 stubs in the > middle right edge of the switch box), and these 4 bounces can all be > driven by the GLK pips on the lower left edge of the switch box. > There's your path. > Doh, Thanks Ajay. I see it now. Sneaky! Cheers, Syms.Article: 84043
Good practice if you don't have timing is to assume each part should not use more than half of the period. Obviously this is not full proof but if you don't have any info this almost always will be ok for normal TTL/LVTTL signals. As for reading yourself there are some application (e.g. more than one driver) so be careful one example is the clock signal of I2C where you need to "listen" to the bus while driving it As it is a line with Possible multidriver. Have funArticle: 84044
Symon, What is 12.5pF in series with 12.5pF? Yes, that is right, 6.25pF differential load, not 12.5pF. Falling for the A FUD is especially embarrassing when you just repeat things which are factually incorrect. All these things are taken into account from the simulation. AustinArticle: 84045
On Mon, 9 May 2005 12:15:12 +0100, "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote: >Given your are using the Platform Flash you are probably using slave serial >mode programming. CCLK will be driven by the V2-Pro so what you need to be >careful of is the data input voltage levels. Usually I wire the relevant >bank voltage Vcco to the Platform Flash to solve this issue. Usually the DIN >goes in on bank4 or 5 but check that for your given device. Actually, the FPGA outputs the CCLK in Master Serial mode, which is what the OP is using (M2=M1=M0=GND) (FYI in slave serial, the CCLK comes from a source external to the FPGA) =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 84046
"ARRON" <mlpei279@gmail.com> wrote in message news:ee8e1d0.3@webx.sUN8CHnE... > Can UART16550 receive only 16bytes a time, if so, how long should the next receive wait after the first receive? how can i receive the data without losting? I think the FIFO will never be full,when you receive the data from FIFO, it is right? If you are responsible for wrapping sandwiches prepared by a cook and handing them off to the person who packs bagged lunches... You wrap each sandwich and put it on the table in front of you but your table space is limited. The bag packer takes the sandwiches from the table one at a time but can take several within the time it takes you to wrap one sandwich depending on what else they're doing. If the bag packer is on a break, you can only wrap so many sandwiches before you run out of table space and have to stop wrapping or start eating the sandwiches. UARTs are meant to have the characters removed before the FIFO is full (before the table runs out of space). You should have another process which handles your messages to move them out of the UART's FIFO and into local storage or to process them on the fly. You should not expect the simple UART core to give you unlimited buffer size.Article: 84047
Philip, 1. They ignored the top comment lines of the IBIS model which instructs them how to model the package (since package modeling is incorrect and wrong in IBIS 3.2). 2. They used an external resistor instead of the internal termination. Run it right, or not at all. AustinArticle: 84048
Hi,
I'm interested in knowing how many equivalent gates are included in
a VirteX II slice for ASIC development. Thanks.
Article: 84049John Savard <jsavard@excxn.anospamb.cdn.invalid> wrote: > Are there other kinds of software-customizable chips out there that are > very different from an FPGA? These guys: http://www.stretchinc.com/ appear to be building processor+programmable logic chips with the goal of compiling C/C++ code into logic for compute intensive applications. G.
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