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Messages from 82875

Article: 82875
Subject: Celoxica RC1000: problems accessing fpga control registers
From: andrej.wunrau@gmail.com (Andrej)
Date: 19 Apr 2005 03:18:44 -0700
Links: << >>  << T >>  << A >>
hi,

i'm writing a linux device driver for the celoxica rc1000 board.
Seems that i can't write to any of the fpga control registers on BAR3
(of PCI9080 config space). Reading access seems to be alright because
the returned values match those mentioned in the hardware reference
manual (in state after power-up).

Reading AND writing to the plx-control-registers (BAR0) and to FPGA
RAM (BAR2) is also no problem.

Any suggestions?

thanks,
Andrej

Article: 82876
Subject: Strange FPGA problem
From: stud_lang_jap@yahoo.com (williams)
Date: 19 Apr 2005 03:26:44 -0700
Links: << >>  << T >>  << A >>
Hello,

I am integrating an IP core and i am facing a strange problem.
One of the register of the IP core which is R/W register is not
writable ..in simulation I am able to write but when ported to FPGA I
am not able to write…its default value is also wrong and when I write
to one fixed register in that core...  its value gets reflects on that
register. Reset value of all the register is ok and I am able to read
and write all R/W registers except one. What may be the
problem…..since simulation results shows that the IP is ok…so I cannot
pin point that tell the IP vendor that there is a bug in ur IP…..

Any feedback???
Thanks and Regards
Williams

Article: 82877
Subject: Re: salary ballpark please guys
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Tue, 19 Apr 2005 12:32:03 +0200
Links: << >>  << T >>  << A >>
buchty@atbode100.lrr.in.tum.de (Rainer Buchty) writes:

> In article <877jiztd2b.fsf@filestore.home.gustad.com>,
>  Petter Gustad <newsmailcomp6@gustad.com> writes:
> |> Here in Oslo, Norway a newspaper delevery person working 29-39 hours a
> |> week can make $126K/yr (NOK 800K). No PhD required :-)
>
> Does that give any idea about the rent for a single one-room apartment and
> the average costs for food?

A 16 sq.meter apartment (180 sq.ft or the size of a typical American
clothing cabinet) in Oslo costs up to 1.2MNOK or close to $200K.
Gasoline in northern Norway was $8.60/gallon a couple weeks ago. 

> Or is that newspaper delivery just an alibi job for some other,
> lesser legal delivery going on below the surface? :)

No :-) There was an article about the paper delivery workers in the
Norwegian Financial Times (www.dn.no) a few weeks ago. Some of them
makes more (> 1M NOK) but they work more than 40 hours a week.


Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 82878
Subject: What is the cause of a "can not see clock" problem in logic analyser?
From: "Acceed See" <invalicd@hotmail.com>
Date: Tue, 19 Apr 2005 18:51:13 +0800
Links: << >>  << T >>  << A >>
My LA is agilent 16702. When I use the 400MHz internal clock to sample
the clock pin and the data pin with probes, I can see them nicely on the LA,
and positive edge of the clock is right in the middle of the data. When I
change
to sampling data with my external clock pin, LA told me the clock is too
weak
and can not see a clock in the top-right banner. Of course, I don't see any
data.

What is the cause of that? How can I correct this?




Article: 82879
Subject: Re: What is the cause of a "can not see clock" problem in logic analyser?
From: "Acceed See" <invalicd@hotmail.com>
Date: Tue, 19 Apr 2005 18:58:56 +0800
Links: << >>  << T >>  << A >>

"Acceed See" <invalicd@hotmail.com> wrote in message
news:4264e0ae$1@news.starhub.net.sg...
> My LA is agilent 16702. When I use the 400MHz internal clock to sample
> the clock pin and the data pin with probes, I can see them nicely on the
LA,
> and positive edge of the clock is right in the middle of the data. When I
> change
> to sampling data with my external clock pin, LA told me the clock is too
> weak
> and can not see a clock in the top-right banner. Of course, I don't see
any
> data.
>
> What is the cause of that? How can I correct this?
>


Any quick fix for those "It worked in simulation, but not in FPGA"
nightmares?
My design is 200K ASIC gates burned in an FPGA, it's so tiring to debug
that.





Article: 82880
Subject: Re: Soft CPU vs Hard CPU's
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 19 Apr 2005 22:59:19 +1200
Links: << >>  << T >>  << A >>
Benjamin J. Stassart wrote:

> Spartan 3E should help with this.  The smallest Spartan 3E starts at 
> under $2 in quantity (and fits a small MicroBlaze system) for an 
> effective MicroBlaze cost of $.48 [1].  You may need a larger device to 
> get everything you want, but I did want to point out that the $10 is a 
> little high if one is going primarily for cost.  It is not fair to 
> compare the entire cost of the FPGA to just a hard processor and then 
> use the rest of the FPGA for other stuff.  In this case the FPGA is 
> doing a lot more than the hard processor.
> 
> As far as the benefits of a soft processor.  MicroBlaze is highly 
> configurable.  You can turn on the features you need: instruction cache, 
> data cache, FSL, XCL, FPU.  See
> 
> http://www.xilinx.com/ise/embedded/mb_ref_guide.pdf
> 
> for more information on MicroBlaze v4.00.a.
> 
> The other huge advantage of soft processors is the FPGA architecture 
> itself.  EDK has an FSL wizard to allow easy creation of accelerators. 
> With careful acceleration of one's application, one can obtain 
> performance that no hard processor can touch.
> 
> EDK also includes a lot of other IP allowing one to build a System On a 
> Chip (SoC) out of the box.  It is a great deal for the price.
> 
> Personally, I also find debugging on an FPGA a lot easier.  One can 
> simulate the EDK system and get a ton of information.  I find ChipScope 
> a lot more convenient than a logic analyzer and one can dig a lot 
> deeper.  Tracking down a bus issue on a hard processor can be a pain. On 
> both sides there are lots of good tools if you want to spend the money, 
> but I think the costs may be more reasonable on the FPGA side.
> 
> If you have the need, Xilinx will sell the MicroBlaze source code for 
> you to customize as you see fit.  Try doing that at a reasonable price 
> on a hard processor.
> 
> I am not in marketing or sales, but I have no problem listing some of 
> the advantages of soft processors.
<snip>

... and neatly avoided ANY mention of the memories needed to actually 
RUN the '48c core'.

  Soft CPUs are great for consuming LUTs, and FPGA vendors love them, but
they are very much 'stone soup'.

  Key deployment 'reality check' questions are :

** Is there a key operational plus, to having the CPU on the FPGA ?

** Can I use a smaller FPGA, if I jettison the Soft CPU ?
    [Suddenly that claimed 48c CPU can get very expensive ! ]

** Will I get less EMC, if I chose a uC with on-chip, secure FLASH code, 
vs a FPGA ? [ that also needs short lifetime, off chip SDRAM, that must 
be loaded from another NV memory -> you have to pay twice to store your 
less secure code !]

** Can I afford the IDLE power budget to run the soft CPU ?

  eg take a hard look at the new widely sourced Flash ARMs (for 
example), that include Large Secure FLASH, AND Analog peripherals, AND 
Oscillators, AND save a LOT of power (wrt Spartan 3E et al). All for 
less than the cost of the dual-CODE memory the Soft-CPU needed....

  -jg



Article: 82881
Subject: Re: Strange FPGA problem
From: "Egbert Molenkamp" <molenkam_no_spam@cs.utwente.nl>
Date: Tue, 19 Apr 2005 13:39:51 +0200
Links: << >>  << T >>  << A >>
Sometimes a register in a register file has a constant value. E.g. R0 in the 
MIPS is always 0.
http://www.web-ee.com/primers/files/MIPS/MIPS.htm

Maybe you have a similar problem
(hence your IP model is incorrect)

Egbert Molenkamp


"williams" <stud_lang_jap@yahoo.com> schreef in bericht 
news:d02ff4ca.0504190226.51d4a56@posting.google.com...
> Hello,
>
> I am integrating an IP core and i am facing a strange problem.
> One of the register of the IP core which is R/W register is not
> writable ..in simulation I am able to write but when ported to FPGA I
> am not able to write.its default value is also wrong and when I write
> to one fixed register in that core...  its value gets reflects on that
> register. Reset value of all the register is ok and I am able to read
> and write all R/W registers except one. What may be the
> problem...since simulation results shows that the IP is ok.so I cannot
> pin point that tell the IP vendor that there is a bug in ur IP...
>
> Any feedback???
> Thanks and Regards
> Williams 



Article: 82882
Subject: Re: re:Spartan 3 to tempsensor interface
From: "Gabor" <gabor@alacron.com>
Date: 19 Apr 2005 06:15:04 -0700
Links: << >>  << T >>  << A >>
rgebru wrote:
> I started using the Analog devices AD7814 and I'm having trouble
> understanding how to interface it to the Spartan 3 board. :(  Does
> anyone have any suggestions to get me started? I could REALLY use the
> help!! Thanks!!

I'm not sure if you mean the electrical interface, the programming,
or both.  Anyway here's my thoughts:

If you don't need to power down the sensor, you can ground the DIN
pin as shown in figure 4 of the datasheet.  For a power supply use
the same voltage as the VCCo of the FPGA I/O to avoid interface
problems with Vih.  It looks like 3.3V and LVTTL or LVCMOS should
work.

For the programming, you need a state machine that generates the
SCLK and CS timing just as shown in figure 2.  The best approach
is to leave CS high between reads to ensure the AD7814 bits match
up with the bit positions shown in the timing diagram.  Then all
you need is a shift register to pick up the bits at the falling edge
of SCLK (to avoid hold time issues).  Depending on how you use the
temperature, you may also need another parallel register loaded
from the shift register when you return CS high.  This register
would then only change at the end of the reading period and always
contain the most recently read temperature.

Good luck,
Gabor


Article: 82883
Subject: Re: DSP-PC architectural advice needed.
From: "Ron Huizen" <rhuizen@bittware.com>
Date: Tue, 19 Apr 2005 09:20:37 -0400
Links: << >>  << T >>  << A >>
"soos" <marcsok@yahoo.com> wrote in message 
news:1113842799.301948.54440@l41g2000cwc.googlegroups.com...
> Hello,
>
> I have an idea for a design of a data aquisition system and i am
> willing to verify the possibility to implement it.
>
> Basically it's an ADC connected to the TS201 that sends the entire
> information sampled to a PC through one of it's LVDS connectors. On

The TS201 has no LVDS connectors as it's a BGA.  Do you mean the TS201 
EzKit?

> the PC there is a PCI Card that knows how to do LVDS for example the

LVDS is simply an electrical signalling standard (Low Voltage Differential 
Signalling) that defines voltage levels, so there is no real "knowing how to 
do LVDS".  The TS201 uses LVDS on its link ports, which have a very specific 
communications protocol they adhere to, so there is definitely a requirement 
to know how to run this protocol.  While you may find lots of PCI boards 
that can support LVDS, you're unlikely to find many that implement the TS201 
link protocol.  What you will find are lots of FPGA based boards where you 
could implement this protocol.  We have such boards, and we've implemented 
this protocol, but if its for a PC, we tend to use PCI as we have TS201s on 
PCI boards.  And if this is a school or hobby project with limited  budget, 
you probably don't want to pay for our boards, which tend to be high end 
(performance and cost).

> PCI GP-ECL/SSD16. of the EDT group. Before checking all the cards
> availbe i would like to ask:
>
> 1.Did someone do the LVDS  connection betwenn the TS201 and PC?

See note above.  It's more a matter of implementing TS201 link port protocol 
than just receiving LVDS signals.

> 2.Do i need to do something special when connecteing the TS to the PC
> board? (someone told   me that there are special cables for it and the
> connection is not Trivial).

Well, anything is going to need special cables.  I think the TS201 EzKit 
used standard RJ45s but only put 1 bit wide link ports on there.  With some 
care, you might get 250 Mbits/second over that.  But you will definitely 
have some custom cabling to do.

There are lots of ways to do what you want (acquire data on a PC)  but it 
all depends on why you're doing this.  A school or hobby project or  a work 
related thing?  If you want to learn FPGAs, you could probably get some 
cheap PCI based FPGA board, rig up a cable, and start hacking away.

------
Ron Huizen
BittWare 



Article: 82884
Subject: Re: EDK:input to microblaze
From: Dan Henry <usenet@danlhenry.com>
Date: Tue, 19 Apr 2005 07:26:56 -0600
Links: << >>  << T >>  << A >>
Herb T wrote:
>>kittyawake@gmail.com wrote:
> 
> Hi Dan,
> Can you give us some more specific details how to do it (or anyone that
> knows ;-)? It would be a great help.

Instantiate a uartns550 or uartlite.  Build with a software library at a 
level appropriate for your needs.  EDK will populate your project 
directory with (for example) ../libsrc/uartlite_v1_00_b/src/.. 
containing library source code to perform UART transmit and receive.

The drivers are documented by the source code and in xilinx_drivers.pdf 
in the EDK's doc directory.

-- 
Dan Henry

Article: 82885
Subject: Re: EDK:input to microblaze
From: Dan Henry <usenet@danlhenry.com>
Date: Tue, 19 Apr 2005 07:28:27 -0600
Links: << >>  << T >>  << A >>
kittyawake@gmail.com wrote:

> Hi,
>   Yeah if any body has any idea of how this thing can be done please
> share your views.I am stuck at this point and cannot proceed till i
> solve this problem of getting data into microblaze from outside(say
> using UART).
> Thanx.
> 
> Herb T wrote:
> 
>>Dan Henry wrote:
>>
>>>kittyawake@gmail.com wrote:
>>
>>Hi Dan,
>>Can you give us some more specific details how to do it (or anyone
> 
> that
> 
>>knows ;-)? It would be a great help.
>>Thanks,
>>-HT
> 
> 

Please don't top-post.

I have posted ideas in reply to Herb T.'s post.

-- 
Dan Henry

Article: 82886
Subject: Re: source control and Xilinx ISE 6 and 7
From: Phil Hays <Spampostmaster@comcast.net>
Date: Tue, 19 Apr 2005 06:28:53 -0700
Links: << >>  << T >>  << A >>
"John Retta" wrote:

>[4] Archiving a design is now simply archiving .v/.vhdl files,
>.ucf file, and script.  As a habit. I also archive .bit files so I
>can backup to a checkpoint without rebuilding.  Files needed
>to recreate .bit file are pretty minimal.

I also like to archive the placed and routed .ncd file as well, mostly
to make generation of a probed bit file faster.  With a small design,
this isn't useful as build time is short enough not to matter as much.
With a large design it is more useful.


--
Phil Hays
Phil-hays at posting domain (- .net + .com) should work for email


Article: 82887
Subject: Re: Declining a job offer
From: "Kryten" <kryten_droid_obfusticator@ntlworld.com>
Date: Tue, 19 Apr 2005 13:56:22 GMT
Links: << >>  << T >>  << A >>
<shuss3@yahoo.com> wrote in message 
news:1113845249.689554.28780@g14g2000cwa.googlegroups.com...
>I just got my first job offer with a semiconductor company. I am yet to
> sign the paperwork. I am hoping to get more offers in the forthcoming
> month. I am wondering if the paperwork that I sign for this company can
> be used against me if I turn down the position for a different one, say
> in a month? Is the paperwork legal and binding? My start date is not
> until July 1st. Thanks in advance for your inputs.


As ever, it is not wise to screw people around.

A comedian once made up an old Sicilian Mafia saying:

"He who sits on the fence gets splinters up his ass!"


In your position I would tell them that you provisionally accept their 
offer, and intend to start work unless you get a _very_significantly_ better 
job offer that you'd be an idiot to refuse.

I've said that on one occasion, and it showed I was sufficiently serious but 
not mad enough to bin any other work offers.

If I were an employer and someone offered you a much better deal (e.g. 50% 
more for oiling up supermodels) I'd find that reasonable.

If you cop out for a few percent, it suggests money is all you care about 
and you can be poached for little more than your real value.


Equally, the employer could in return ask that the job offer is subject to 
them not finding anyone better or cheaper in the meantime.


A good option might be that you both accept the deal as is, and that you 
spend the time till then shared between having a holiday and swotting up 
like mad on whatever it is they do. Thus when you start, you'll be 
refreshed, ready, confident and ready to bust ass!

May the force be with you, young padawan...



Article: 82888
Subject: GPD+APD=FPG? TLA's run amok.....
From: austin <austin@xilinx.com>
Date: Tue, 19 Apr 2005 07:21:35 -0700
Links: << >>  << T >>  << A >>
General Products Division

As opposed to what I am in, APD, Advanced Products Division (we think 
very highly of ourselves.....)

Both groups report to FPG, or the Field programmable gate array Products 
Group (I just love how we make up obscure acronyms).

Of course, next week, it may all change again (structure is a fluid 
thing, and even when the structure isn't changing, the names might be).

Yet another reason to always talk to the GSD (Global Services Division) 
or as it has always been called, the Hotline.  They get a new roadmap 
everytime things change, and they have direct access to the 'fire 
chiefs' who handle escalated cases (cases involving "lines down" issues).

Austin

Article: 82889
Subject: Re: Odd Oversampling
From: ALuPin@web.de (ALuPin)
Date: 19 Apr 2005 07:28:46 -0700
Links: << >>  << T >>  << A >>
One more question:

The quasi "oversample" solution in XAPP224 does imply that the sample
clock is the same as the clock from the incoming data stream.

But in my situation I have a clock that is 7-8 times faster.

Please clarify ...

Thank you.

Rgds
André

Article: 82890
Subject: Re: EDK:input to microblaze
From: "Herb T" <oth3ll0@hotmail.com>
Date: 19 Apr 2005 07:43:00 -0700
Links: << >>  << T >>  << A >>
Dan,
Thanks for responding and for your help.
-HT


Article: 82891
Subject: Re: Xilinx XPower - Accuracy Information
From: Brendan Cullen <bcullen@xilinx.com>
Date: Tue, 19 Apr 2005 15:43:28 +0100
Links: << >>  << T >>  << A >>

--------------F77453B674D6E88FE93ECC9C
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi,

parity wrote:

> Hello,
>
> thanks for the answers. I am sorry, that i didn't give you enough
> information. I am using the Xilinx XCV 800bg432-4 and i am also using
> VCD and sdf files. I know the FPGA is a really small one, but i need
> it for researching purposes only. Yesterday I found some information
> in the Xilinx Answer Database. The accuracy seems to be in the range
> of 10 % (PRODUCTION/FINAL).
>
> Here is the link to the Article:
>
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14285
>
>

That is correct.  XPower's accuracy improves with maturation of silicon.

Brendan

--------------F77453B674D6E88FE93ECC9C
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hi,
<p>parity wrote:
<blockquote TYPE=CITE>Hello,
<p>thanks for the answers. I am sorry, that i didn't give you enough
<br>information. I am using the Xilinx XCV 800bg432-4 and i am also using
<br>VCD and sdf files. I know the FPGA is a really small one, but i need
<br>it for researching purposes only. Yesterday I found some information
<br>in the Xilinx Answer Database. The accuracy seems to be in the range
<br>of 10 % (PRODUCTION/FINAL).
<p>Here is the link to the Article:
<p><a href="http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14285">http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&amp;iCountryID=1&amp;getPagePath=14285</a>
<br>&nbsp;
<br>&nbsp;</blockquote>
That is correct.&nbsp; XPower's accuracy improves with maturation of silicon.
<p>Brendan</html>

--------------F77453B674D6E88FE93ECC9C--


Article: 82892
Subject: Re: Xilinx tools on Linux
From: Martin Ellis <me_ncl@hotmail.com>
Date: Tue, 19 Apr 2005 15:55:23 +0100
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> Note that Qt still would have per-seat license fees, so I don't think
> it's even in the running.

Huh?  Qt is licensed per developer seat, not per user seat.
See: http://www.trolltech.com/products/qt/migrate/motif.html

"No per-copy fees" - can't get more explicit than that.
What's the problem?

Martin

Article: 82893
Subject: Re: source control and Xilinx ISE 6 and 7
From: Petrov_101@hotmail.com
Date: 19 Apr 2005 08:00:11 -0700
Links: << >>  << T >>  << A >>

Guy.Eschemann@gmail.com wrote:
> Andy,
>
> I suggest you drop the GUI and start working with the command line
> tools. The GUI is OK for getting started and playing around a bit,
but
> it has many limitations that make me feel very unproductive when I
> happen to use it.
>
> All of the command line tools have options for specifying the
location
> of input and output file, so they need not be in the same directory.
> Some also provide a -dd option for intermediate files (the
development
> system reference guide is your friend here).

I've recently started using 'make' with Revision Control System (RCS)
for my script files.  Has anyone used 'make' to manage the command line
tools for fpga simulation and synthesis?


Article: 82894
Subject: Re: XC3000 non-recoverable lockup problem
From: "lecroy7200@chek.com" <lecroy7200@chek.com>
Date: 19 Apr 2005 08:09:17 -0700
Links: << >>  << T >>  << A >>
I have come to the conclusion that it is possible that the actual core
design can effect the internal charge pump circuits.  After weeks of
testing a core that was  auto generated, I have been unable to
reproduce the problem.  Setting the outputs to FAST or slow appears to
have no effect on the failure.  Talking with Philip, it does not appear
that the device had any capabilities to turn off the charge pumps.

I did go back to the original core and made sure I could reproduce the
failure once more.

I also came across this old note from Xilinx:

"Note that XC3100L and XC5200L use a continuously running
internal oscillator to generate an elevated voltage for driving
the pass-transistor gates , This is called "pumped gates" and
gives better speed, but results in significantly elevated idle
( quiescent ) current consumption, bad for battery-operated
systems. XC3100 devices have always used this technique, while
the original XC5200 devices did not, but the coming releases
will."

It appears some of the newer parts also used internal charge pumps.
Would be interesting to know if they would be prone to the same
problem.


Article: 82895
Subject: Re: source control and Xilinx ISE 6 and 7
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Tue, 19 Apr 2005 17:15:53 +0200
Links: << >>  << T >>  << A >>
Petrov_101@hotmail.com writes:

> I've recently started using 'make' with Revision Control System
> (RCS) for my script files. Has anyone used 'make' to manage the
> command line tools for fpga simulation and synthesis?

Yes, for many years. I usually do "cvs co; configure; make" to build a
design from scratch.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 82896
Subject: Re: Strange FPGA problem
From: Navneet Rao <navneetr@xilinx.com>
Date: Tue, 19 Apr 2005 08:24:00 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Hi Williams:

If you are using Verilog: Check your port-width mismatches in the
instantiation(s)/wire(s)/reg(s) definitions. Even if verilog, does not
report above errors,
go through the synthesis report warnings in detail.

-Navneet

williams wrote:

> Hello,
>
> I am integrating an IP core and i am facing a strange problem.
> One of the register of the IP core which is R/W register is not
> writable ..in simulation I am able to write but when ported to FPGA I
> am not able to write…its default value is also wrong and when I write
> to one fixed register in that core...  its value gets reflects on that
> register. Reset value of all the register is ok and I am able to read
> and write all R/W registers except one. What may be the
> problem…..since simulation results shows that the IP is ok…so I cannot
> pin point that tell the IP vendor that there is a bug in ur IP…..
>
> Any feedback???
> Thanks and Regards
> Williams

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Article: 82897
Subject: Re: Odd Oversampling
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 19 Apr 2005 08:35:40 -0700
Links: << >>  << T >>  << A >>
Hi André,
I'd probably  do it like this.
Have a 7 bit counter that counts modulo 125 on your 125MHz clock. Call it
'counter'. If you get a transition on the data (which you've already sampled
into the 125MHz clock domain, right?), reset it to 0. When the counter says
4 | 12 | 19 | 27 | 35 | 43 | 51 | 58 | 66 | 74| 82 | 90 | 97 | 105 | 113 |
121 sample the data. (I'd check those numbers for yourself, my arithmetic
isn't what it used to be..) Of course with half the bits there will be a
transition so you'll only be sampling at big counts if you get a lot of
consecutive equal bits. Remember if the count gets to 124 the next count
should be 0, i.e. modulo 125.
Have fun, Syms.

"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0504180203.226a3d5b@posting.google.com...
> Hi newsgroup,
>
> maybe someone of you out there has faced some similar problem:
>
> I want to sample 16MHz data with a 125MHz clock.
>
> But 125/16 = 7.8125
>
> Is there some tricky method to perform this kind of oversampling ?
>
> The only thing I know is the Bresenham algorithm, but could that
> be the solution ?
>
> Thank you in advance.
>
> Rgds



Article: 82898
Subject: Re: Odd Oversampling
From: "Peter Alfke" <peter@xilinx.com>
Date: 19 Apr 2005 08:48:30 -0700
Links: << >>  << T >>  << A >>
Here is a circuit that generates 16 MHz from a 125 MHz clock:
Use a Xilinx DCM with simultaneous multiply by 16 and division by 25.
That gives you 80 MHz, which might be convenient for 5x oversampling.
Peter Alfke, Xilinx Applications


Article: 82899
Subject: Re: [Info]Platform USB.
From: Rudolf Usselmann <russelmann@hotmail.com>
Date: Tue, 19 Apr 2005 23:14:20 +0700
Links: << >>  << T >>  << A >>
Symon wrote:

> Just got my new Xilinx platform usb download cable. $149. Works great,
> even with 6.3.03, very fast. No longer will I need to position my laptop
> near a desktop to get PS2 power for my parallel download cable! Inside,
> there's a Cypress EZ-USB CY7C68013 and a Coolrunner XC2C256, with a
> unfitted 14 way connector probably to download to it!
> Best, Syms.

Does it work with Linux ?  And I mean with Linux, not just RHEL3 ....

Thanks,
rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis



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