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Hello! I am using Synopsys fc2_shell and the Xilinx ISE 6.1 Tools to create my FPGA-Design. When I define a clock frequency (like 20 MHz), Synopsys generates a edif-netlist. After using ngdbuild i get an UCF-File which contains a constraint like "max. PAD TO PAD Delay=50ns" (Syntax is quite different). My Question is: If I use registered Multipliers, Adders, etc. I want to have a Register to Register constraint defined because the Design itself is allowed to take more than one clock cycle for calculation. How can I do this? Does anybody know how to define this? Thank you. parityArticle: 82901
Duane Clark wrote: > Rudolf Usselmann wrote: >> >> yes, it is possible to replace the GUI with a script. At least >> for ISE. I have not been able to figure out hot to do the same >> for EDK (yet). >> > > Assuming you are on Linux... (though presumably this should also work on > Windows) > > The EDK project is run by a makefile, named system.make. So you can can > build the project by typing commands like: > make -f system.make netlist > which builds the bitfile from HDL code, and > make -f system.make program > which compiles C code and inserts it into the bitfile. Those are about > the only two EDK commands I use. I never use the EDK GUI. A list of > commands is available with: > make -f system.make > Actually, I create a symbolic link > ln -s system.make makefile > which means I don't need to type out the "-f system.make" stuff. > > Of course, that doesn't get you the project in the first place. In > general, I take an existing project that is similar to what I want, copy > it over, and start modifying. Exactly ! Thats is what I do. And as you point out the tricky part is to get the project created. For that I still start up xps, and ask it to "Save Makefile". After that I just run gmake ... rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 82902
ok, ok we've beaten this subject to death already .... I just had this really radical and crazy idea: XILINX, how about a BETA program ? I mean one before you burn the CDs and make a product announcement and we are stuck with a useless plastic disc. If I look at all the issues that people are having with 7.1, they are all so trivial and easy to to solve (include a few libs, distribute a statically linked setup program, etc.). I'm sure a few of us with subscription would volunteer to test drive a pre-release version of your s/w. - I know I would. Wouldn't that be much nicer than shipping Beta software and having everybody whine and complain ??? Wouldn't it be nicer if people would post messages expressing their joy how easy and functional the s/w upgrade was ? All you need is a dozen or so beta testers. Don't tell me thats more work than to creating all the work around and answer records and all the support calls .... As I said, a very radical idea ! rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 82903
Gee I almost forgot, this actually happened to me. I had a great offer from 1 of top 20 semi companies (DSP..) with big increase over what I was getting already so of course I was excited and accepted, but days before the move was set to happen.. Worst thing happened, somebody else came along that was desperate, really desparate, they doubled that offer and made it impossible for me to refuse both in stock, salary etc, I switched, the other company understood, they knew it was an exceptional counter offer so they let it go as one of those wierd things. 2x was not something they could do anything about. Do I regret doing this, yes & no, 1st company is a rock solid company I would have done well at and they are still here and stronger. The company I went with had alot of potential upside (and it was way before the bubble started). The gig lasted along time, was an interesting ride and I learnt as much as I would have at the 1st company, maybe more. Well the bubble did eventually burst and they barely exist now, lots of stuff outside my control, but I can now do my own gig. Would I recomend doing that again, in a booming economy that can be okay for seniors, but today I wouldn't do it and also youngen's shouldn't do it either as it really messes up your future options. Once you get into the mile high club, you won't be so welcome if everybody thinks you want 2x. If you want a long company career you will be in a salary tunnel that is fairly limited anyway. 20yrs exp is only worth 2x recent graduate unlike in other professions. Do your homework on the company, did you like the people you met, if so it will probably work out, if not don't go there. If you get other offers, they will likely be very close in salary anyways. regards JJArticle: 82904
All of The more recent FPGAs use the Vccaux supply through a regulator to supply Vgg, or the pass gate voltage supply. There are no charge pumps in FPGAs now since Virtex (roughly 7.5 years). AustinArticle: 82905
Rudi, Only in ISE 7.1 I think.(see link below) I use Windows for all my Xilinx stuff; my opinion is that the software has enough 'features' without trying a less used OS. I hope to be able to change that opinion in the not-to-distant future! Cheers, Syms. http://www.xilinx.com/bvdocs/ipcenter/product_brief/usb_cable_overview.pdf "Rudolf Usselmann" <russelmann@hotmail.com> wrote in message news:d43aos$v29$1@nobel.pacific.net.sg... > Does it work with Linux ? And I mean with Linux, not just RHEL3 .... > > Thanks, > rudiArticle: 82906
"Brad" <brad1@tinyboot.com> wrote in message news:1113861401.050628.69820@l41g2000cwc.googlegroups.com... > Hi all, > > Have people had reasonable success getting samples of Spartan3E parts? > The XS3S100E, for example. I ask this because I got burned by the slow > rollout of Spartan XC3S400s. > > Brad > The early XC3S100E FPGA samples are generally available at select accounts now. General sampling begins starting May with wide availability starting July. Please contact your local Xilinx distributor or representative if you have immediate needs. Production is planned for 3rd quarter 2005. Just FYI, two of our distribution partners already have XC3S100E-based evaluation boards. In alphabetical order by distributor name ... Avnet Spartan-3E Evaluation Kit http://www.em.avnet.com/s3e100eval Memec Spartan-3E LC http://www.memec.com/?cmd=detail&articleid=2056 --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e Tel: (408) 626-7447 E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 82907
Personally I probably wouldn't do this, depending on the situation. I find that having as few clocks as possible is the best strategy for FPGAs. I use enables instead. So, if Andre already has a 125MHz system clock in his device that he's using, he should stick with it rather than generating a new clock domain. If, however, the 125MHz is only used in this circuit, I guess making it into 80MHz might work. YMMV, Syms. p.s. I think all my numbers in that previous post were 1 too big for a proper sync design. "Peter Alfke" <peter@xilinx.com> wrote in message news:1113925710.027051.206960@f14g2000cwb.googlegroups.com... > Here is a circuit that generates 16 MHz from a 125 MHz clock: > Use a Xilinx DCM with simultaneous multiply by 16 and division by 25. > That gives you 80 MHz, which might be convenient for 5x oversampling. > Peter Alfke, Xilinx Applications >Article: 82908
Eric Smith wrote: > I wrote: > > What source control system are you using for which that causes > > problems? I use CVS and Subversion, and neither has any trouble with > > generated files (intermediate or final) being put in the same > > directory as the sources. > > "Andy Peters" <Bassman59a@yahoo.com> writes: > > Subversion and Visual Source (Un)Safe. It's not that the revision > > control systems have any problem dealing with the generated files -- > > it's just that there's no reason for that cruft to be in the repository > > at all. > > As I said, I'm using Subversion. And none of that cruft makes it into > my repository. The repository only gets the files on which you do a > "svn add". I think you misunderstand my question, which is: what files are necessary and what files are cruft? > My sympathies on having to use SourceSafe. At least I assume you're > forced to do so; no sane person would use it otherwise. Indeed, that's the case. > I once worked for a company at which some of the developers were unhappy > that CVS didn't have a GUI. I tried to explain that there were multiple > GUIs available for them to choose from, but apparently they didn't like > that and wanted there to be one "official" GUI. (Kinda like management > wanting to buy commercial software so that there is "someone to sue".) > > Anyhow, they prevailed and we switched to SourceSafe. What a disaster! The SourceSafe GUI isn't all that great. > Before we made the switch, I read up on it a bit on Microsoft's web > site. They were bragging about the features of the latest version, and > one of those features was a tool to repair corrupted repositories. Huh? > I've never *had* a corrupted repository with CVS. But they were common > with SourceSafe. > > The details on that recovery tool pointed out that sometimes it couldn't > completely repair the repository in one run, and you had to run it > again. What, can't the tool tell when it's done? Typical MS brain > damage. And of course there's the very fact that Microsoft doesn't eat their own dog food w.r.t. SourceSafe. > I'm *very* happen with Subversion. As am I. We had a decent Subversion set-up at my previous job, and I run svnserve on one of my Macs at home. TortoiseSVN works very well on the Windows boxen and the command-line is always available on both platforms. -aArticle: 82909
ALuPin wrote:
> But in my situation I have a clock that is 7-8 times faster.
> Please clarify ...
Please reread my posting.
The idea is as clear as I have time to make it.
-- Mike Treseler
Article: 82910I just reread your post. Where does the 16 MHz clock come from? Rereading Andre's original post, he only has 16 MHz (sic) data. ;-) Cheers, Syms. "Mike Treseler" <mike_treseler@comcast.net> wrote in message news:3cl11lF6kuiooU1@individual.net... > ALuPin wrote: > > > But in my situation I have a clock that is 7-8 times faster. > > Please clarify ... > > Please reread my posting. > The idea is as clear as I have time to make it. > > -- Mike TreselerArticle: 82911
Is there an easy to use Actel's internal ram without going to coregen? I'm concerned about compatibility issues if I have to use coregen. thanks in advance.Article: 82912
VhdlArch-0.1.1 is now available. Still only handles syntax checking, but includes several bug fixes (thanks for the feedback!). http://www.confluent.org/wiki/doku.php?id=vhdlarch -TomArticle: 82913
Hello, Just a follow up. Iam right now waiting for a better oscilloscope to see the ringing and crosstalk if any, hence the delay in response. > How do you know when new values are available to take them into your > core clock domain? Can double clocking occure at this point? I sample the strobe signal at 133MHz and detect the edge. That way I kno w when new data is present on the IOB's. Rest of the stuff guess has been answered by Peter :-) Brijesh Sebastian Weiser wrote: > Hello, > > Brijesh <brijesh_xyz@cfrsi_xyz.com> wrote in message news:<d3e426$rbl$1@solaris.cc.vt.edu>... > >>The double clocking of the CRC generator mentioned was when strobe was >>directly used to clock the CRC generator. In my design I am using >>internal clocl for CRC generator. Although I am still using the strobe >>to clock in the data at the IOB's. So right now I suspect thats where >>the problem is. > > > How do you know when new values are available to take them into your > core clock domain? Can double clocking occure at this point? > > >>So currently Iam trying to identify the cause, >>Is it really the double clocking that is causing the trouble? > > > You could put the captured data on a debug output, capture it with an > logic analyzer and compare it with your reference. High effort, > though. > > >> > I don't know much about these issues (I design circuits for FPGA/ASICs >> > and do no "real" hardware), but don't you need to take LVCMOS33 for >> > outputs? >> >>The Voh and Vol for LVCMOS33 and LVTTL33 on V2 device are identical and >>match that of the IDE spec. > > > Really? I read in the ds031.pdf (v3.4) on page 4 in module 3, that Voh > is 2.4 V for LVTTL and Vcco-0.4 for LVCMOS33. But anyway, the > requirement is 2.4 V for UDMA3. I had the more restrictant > Voh2=VDD3-0.51V in mind, which is required for UDMA5 and greater. > > >>Also just read that the LVTTL and LVCMOS >>inputs have approximately 100mV of hysteresis. > > > Again for UDMA5 and greater, there are additional requirements for the > input thresholds to keep the average of the two close to 1.5 V. I > think this is to ensure that a rising STROBE and a falling DATA edge > will switch at the same time. > Hmm - I see that the requirement for the 320 mV hysteresis is for > UDMA5 and greater only, too. > > > Sebastian WeiserArticle: 82914
Just a hunch, but this smells like a bitstream loading problem. Perhaps your connection while loading the bitstream was not OK. Try reloading the bitstream and check after that. - Swapnajit. -- SystemVerilog, DPI, Verilog PLI and all other good stuffs. Project VeriPage: http://www.project-veripage.com For subscribing to the mailing list: <URL: http://www.project-veripage.com/list/?p=subscribe&id=1>Article: 82915
Because of the deficiencies in Verilog or the tools, I often have to
write Perl to generate Verilog. Examples of these deficiencies include:
- Port list is not parameterizable without use of `defines
- Many synthesizers don't understand preprocessing constant functions
- Generate function in Verilog has limitations
Rather than write Perl to generate Verilog modules, which is a
cumbersome flow, it would be nice to have a Perl preprocessor. What I
am thinking of is something that would look through your HDL, find
formatted comments, parse parameters and `ifdefs, and then execute Perl
and insert the results there. It would see something like this:
.
.
.
parameter NUM_UNITS=2;
`define PARAM2 2
// Perl Start
// for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
// print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
// }
// Perl End
.
.
Then it would execute the Perl in the comments and append the output to
the commented section, like this:
.
.
.
parameter NUM_UNITS=2;
`define PARAM2 2
// Perl Start
// for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
// print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
// }
// Perl End
// Generated Perl Code Start
adder adder0 (.I(i[0],.O(o[0]);
adder adder1 (.I(i[1],.O(o[1]);
adder adder2 (.I(i[2],.O(o[2]);
adder adder3 (.I(i[3],.O(o[3]);.
// Generated Perl Code End
.
.
Of course this is a simple example that can be accomlished with a
'generate', but you get my point. Note that the Verilog parameters have
been parsed and can be used as Perl variables. With this preprocessor
you could also do a lot of floating-point preprocessing that uses
functions like "sine" that don't exist in Verilog. Does anything like
this exist? Or do I have to write my own?
-Kevin
Article: 82916Rudolf Usselmann wrote: > Duane Clark wrote: >>Of course, that doesn't get you the project in the first place. In >>general, I take an existing project that is similar to what I want, copy >>it over, and start modifying. > > > Exactly ! Thats is what I do. And as you point out the tricky > part is to get the project created. For that I still start up > xps, and ask it to "Save Makefile". After that I just run gmake ... A trick to save waiting for the GUI: $ xps -nw system.xmp % save make % exit JohnArticle: 82917
Kevin,
It'd be less than an hour to write a Perl pre-processor to run the inline
stuff. You know about Perl's 'eval' function I assume? Read the file in,
write it back out, execute the stuff between the //Perl Start End thingies.
Cheers, Syms.
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:d43ttt$a13@xco-news.xilinx.com...
> Because of the deficiencies in Verilog or the tools, I often have to
> write Perl to generate Verilog. Examples of these deficiencies include:
>
> - Port list is not parameterizable without use of `defines
> - Many synthesizers don't understand preprocessing constant functions
> - Generate function in Verilog has limitations
>
> Rather than write Perl to generate Verilog modules, which is a
> cumbersome flow, it would be nice to have a Perl preprocessor. What I
> am thinking of is something that would look through your HDL, find
> formatted comments, parse parameters and `ifdefs, and then execute Perl
> and insert the results there. It would see something like this:
> .
> .
> .
> parameter NUM_UNITS=2;
> `define PARAM2 2
> // Perl Start
> // for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
> // print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
> // }
> // Perl End
> .
> .
>
> Then it would execute the Perl in the comments and append the output to
> the commented section, like this:
> .
> .
> .
> parameter NUM_UNITS=2;
> `define PARAM2 2
> // Perl Start
> // for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
> // print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
> // }
> // Perl End
> // Generated Perl Code Start
> adder adder0 (.I(i[0],.O(o[0]);
> adder adder1 (.I(i[1],.O(o[1]);
> adder adder2 (.I(i[2],.O(o[2]);
> adder adder3 (.I(i[3],.O(o[3]);.
> // Generated Perl Code End
> .
> .
>
> Of course this is a simple example that can be accomlished with a
> 'generate', but you get my point. Note that the Verilog parameters have
> been parsed and can be used as Perl variables. With this preprocessor
> you could also do a lot of floating-point preprocessing that uses
> functions like "sine" that don't exist in Verilog. Does anything like
> this exist? Or do I have to write my own?
> -Kevin
Article: 82918Kevin Neilson wrote: > Because of the deficiencies in Verilog or the tools, I often have to > write Perl to generate Verilog. Examples of these deficiencies include: > > - Port list is not parameterizable without use of `defines Parameters work quite well for this, now that Verilog-2001 allows you to set up Verilog module port definitions much like VHDL's entities: parameters can be defined before the port list, and those parameters can be used in the port declarations. -aArticle: 82919
Hi, I am using OV6620 Omnivision CMOS Image sensor. My module has CLK fosc: 17.734MHz PCLK: 112ns = 8.92MHz Does any body know how this is acheieved (mathematically ?) Thanks, ArchillesArticle: 82920
I wrote: > Note that Qt still would have per-seat license fees, so I don't think > it's even in the running. Martin Ellis: > Huh? Qt is licensed per developer seat, not per user seat. > See: http://www.trolltech.com/products/qt/migrate/motif.html Thanks for the correction. I knew that there was commercial licensing involved, but had no idea that there weren't per-copy fees.Article: 82921
"Andy Peters" <Bassman59a@yahoo.com> writes: > I think you misunderstand my question, which is: what files are > necessary and what files are cruft? Your Verilog and/or VHDL files, and your UCF files are necessary. Anything else that you create yourself is necessary. All those things should be checked into your repository. Everything that is generated by the tools should not be checked into the repository.Article: 82922
Rudolf Usselmann <russelmann@hotmail.com> wrote: > ok, ok we've beaten this subject to death already .... > I just had this really radical and crazy idea: > XILINX, how about a BETA program ? I mean one before you burn > the CDs and make a product announcement and we are stuck with > a useless plastic disc. > If I look at all the issues that people are having with 7.1, > they are all so trivial and easy to to solve (include a few > libs, distribute a statically linked setup program, etc.). > I'm sure a few of us with subscription would volunteer to test > drive a pre-release version of your s/w. - I know I would. > Wouldn't that be much nicer than shipping Beta software and > having everybody whine and complain ??? > Wouldn't it be nicer if people would post messages expressing > their joy how easy and functional the s/w upgrade was ? > All you need is a dozen or so beta testers. Don't tell me thats > more work than to creating all the work around and answer records > and all the support calls .... > As I said, a very radical idea ! And a good one. But I fear that nobody from the ISE programming department reads here :-( -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 82923
Andy Peters wrote: > Kevin Neilson wrote: > >>Because of the deficiencies in Verilog or the tools, I often have to >>write Perl to generate Verilog. Examples of these deficiencies > > include: > >>- Port list is not parameterizable without use of `defines > > > Parameters work quite well for this, now that Verilog-2001 allows you > to set up Verilog module port definitions much like VHDL's entities: > parameters can be defined before the port list, and those parameters > can be used in the port declarations. > > -a > You can use parameters to define the width of the port, but you can't actually change the number of ports. For example, say I want a 4-port memory interface, I would want part of the port list to read: module memory( input [7:0] din0, input [7:0] din1, input [7:0] din2, input [7:0] din3, ... Whereas for an 8-port interface, I want four more of these ports. Parameters can't be used to increase the number of ports. What I can do is concatenate all the ports into a single port with parameterizable width, but that's not a very friendly interface. -KevinArticle: 82924
That part isn't too bad, but I think the difficult part is to be able to
use the Verilog parameters in the Perl code. For that to work, I have
to be able to parse through all the files to find the values of all the
parameters in that scope.
-Kevin
Symon wrote:
> Kevin,
> It'd be less than an hour to write a Perl pre-processor to run the inline
> stuff. You know about Perl's 'eval' function I assume? Read the file in,
> write it back out, execute the stuff between the //Perl Start End thingies.
> Cheers, Syms.
>
> "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
> news:d43ttt$a13@xco-news.xilinx.com...
>
>>Because of the deficiencies in Verilog or the tools, I often have to
>>write Perl to generate Verilog. Examples of these deficiencies include:
>>
>>- Port list is not parameterizable without use of `defines
>>- Many synthesizers don't understand preprocessing constant functions
>>- Generate function in Verilog has limitations
>>
>>Rather than write Perl to generate Verilog modules, which is a
>>cumbersome flow, it would be nice to have a Perl preprocessor. What I
>>am thinking of is something that would look through your HDL, find
>>formatted comments, parse parameters and `ifdefs, and then execute Perl
>>and insert the results there. It would see something like this:
>>.
>>.
>>.
>>parameter NUM_UNITS=2;
>>`define PARAM2 2
>>// Perl Start
>>// for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
>>// print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
>>// }
>>// Perl End
>>.
>>.
>>
>>Then it would execute the Perl in the comments and append the output to
>>the commented section, like this:
>>.
>>.
>>.
>>parameter NUM_UNITS=2;
>>`define PARAM2 2
>>// Perl Start
>>// for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
>>// print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
>>// }
>>// Perl End
>>// Generated Perl Code Start
>>adder adder0 (.I(i[0],.O(o[0]);
>>adder adder1 (.I(i[1],.O(o[1]);
>>adder adder2 (.I(i[2],.O(o[2]);
>>adder adder3 (.I(i[3],.O(o[3]);.
>>// Generated Perl Code End
>>.
>>.
>>
>>Of course this is a simple example that can be accomlished with a
>>'generate', but you get my point. Note that the Verilog parameters have
>>been parsed and can be used as Perl variables. With this preprocessor
>>you could also do a lot of floating-point preprocessing that uses
>>functions like "sine" that don't exist in Verilog. Does anything like
>>this exist? Or do I have to write my own?
>>-Kevin
>
>
>
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