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Hi Sunny, some links: http://www.niosforum.com/forum/index.php?act=ST&f=2&t=1848 http://www.niosforum.com/forum/index.php?act=ST&f=2&t=1596 (this is the thread I mentioned) Beside these (and the SDRAM) issues I see no reason why the Nios-core should not work even when the clock pauses for a long time. Of course you should take great care that the clock-gating does not introduce short glitches as these would cause troubles. Also peripherals like UARTs, etc. will behave incorrectly when the clock is stopped during operation. Regards, Thomas www.entner-electronics.com "Sunny" <shiladitya.biswas@gmail.com> schrieb im Newsbeitrag news:1119517731.171087.128290@g43g2000cwa.googlegroups.com... > Hi Thomas, > Thanks for your reply. The reason I want to slow processor clock > frequency is that I basically want to stop the processor from executing > when I want, and give it clocks only when needed (through some clock > gating mechanism). It is a multiprocessor system where one processor > will run at high speeds (~50 Mhz) and the other processor will run only > when needed. > So I wanted to know if can the processor retain its state for an > indefinite time? I will take care of SDRAM clocks separately. > Some processors like Pentium have a specification for the lowest clock > frequency because they cannot retain the state for long enough (due to > capacitors getting discharged). Is there any such limitation for Nios 2 > ( essentially the FPGA fabric) ? > So what I am looking for is that clock period should be theoretically > infinite. > > For JTAG - UART can you direct me to some place where I can read > exactly how it works and why debugging fails below 10Mhz. > > Thanks > Sunny >Article: 86226
Hi, How would you do this in terms of analog electronics? To separate the DC part from the mixed signal you have to generate an average of the AC/DC signal. This can be done with a low pass filter. Low pass filters can also be implemented digitally. Depending on the required accuracy of your application the algorithm can be more or less complex/accurate. Maybe your FPGA vendor offers some free macro blocks for IIR or FIR filters, where you only have to feed the coefficients for the desired filter characteristics. (e.g. Xilinx Coregen modules) so you don't have to reinvent it. What you described (Subtractor and MAC) sounds more like an moving average algorithm. Maybe this will work for your application, but if you need higher accuracy and a defined frequency curve you need a real low pass filter. Of course, the DC elimination can be done without the DAC, directly on the digital side of your design, (simply delay your input signal(e.g. shift register), and subtract the calculated DC value. If you try to increase the dynamic resulution of your system (measuring a small ac signal with high resolution on top of a larger DC signal) you may need your approach, but please consider if the system may become cheaper or easyer to manufacture if you just use a ADC with some more bits of resolution and do the digital subtraction method? have a nice synthesis eilert backhus(ät)isms_punkt_hs-bremen_punkt_de "punkt" is german for dot shridhar@mistralsoftware.com schrieb: > Hi, > > we are reading an ADC o/p through FPGA. To remove the DC Offset present > in the ADC input we have a DAC which can remove this DC offset using a > subtractor before the actual analog input (with added DC offset) goes > to ADC. > > Now I want my FPGA to calculate the DC offset from ADC outputs and then > feed this value to DAC input which in turn cancel the DC offset using > subtrator. > > can anybody suggest me how can i implement this in FPGA? I just gone > through net and realized that i can use a subtractor and a MAC. The ADC > output will go to this Subtractor which has the final output of MAC as > other input. the subtractor output will be multiplied with some small > value K (??) and then an accumulator. The final output of accumulator > can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the > DC offset? > > this is what i understood. can somebody through some light? > > suggestions are welcome. >Article: 86227
You might find some good reading at http://tinyurl.com/chz9s which can also be found with: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=kc_dig_offset&languageID=1 The techXclusive article goes through dc offset removal in some detail but doesn't cover your explicit technique of analog feedback as far as I recall. Your method seems sound as long as you 1) properly lowpass the DAC feedback and use an integrator (or accommodate the offset feedback in the digital part of the loop) since the feedback will result in 0 DC offset. shridhar@mistralsoftware.com wrote: > Hi, > > we are reading an ADC o/p through FPGA. To remove the DC Offset present > in the ADC input we have a DAC which can remove this DC offset using a > subtractor before the actual analog input (with added DC offset) goes > to ADC. > > Now I want my FPGA to calculate the DC offset from ADC outputs and then > feed this value to DAC input which in turn cancel the DC offset using > subtrator. > > can anybody suggest me how can i implement this in FPGA? I just gone > through net and realized that i can use a subtractor and a MAC. The ADC > output will go to this Subtractor which has the final output of MAC as > other input. the subtractor output will be multiplied with some small > value K (??) and then an accumulator. The final output of accumulator > can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the > DC offset? > > this is what i understood. can somebody through some light? > > suggestions are welcome.Article: 86228
Hello Guys, I am facing some problem in using chipscope. I am using chipscope core inserter has i synthesis my code using synplify. In my code i have any IP core which is provided to me in netlist form. One of my doubt is that when i am assigning signal to trigger signal i am not able to see the IP core module (netlist form). Why is this so? I am using chipscope 6.3i (evaluation). In the final waveform i am not able to view the triggering signal, signal other than triggering signal can be viewed. How i view trigger signal also. I am also not able to give label to signal which i am viewing, it appears as ch0....ch15... Thanks and regards williamsArticle: 86229
Well, if you detect the rising or falling edge of the clock, you can count the number of clocks corresponding to the desired delay. once you reach this coun, you shift the data using 1 MHz clock... This is UART-like data shifting-out i think. If there is no problem with setup/hold time in the receiving device, this should be alright. Hope this helps. Vladislav <JT> wrote in message news:ee8f32c.-1@webx.sUN8CHnE... >I am generating a slow serial data stream in response to a input clock. I >need to delay n uSec's after detecting the clock edge before I output the >data. The input clock is currently running at 10 Khz. I was going to run >another process at 1 Mhz but don't know the best way to wait for a delay >count in the slower 10 Khz process. > > Any suggestions? > > ThanksArticle: 86230
The power supply & external prom is the reason we are using a Lattice XP. The part has the integrated flash and there is an on board regulator that allows me to power the entire part with only 3.3v Fortunately our design fits in the 10k LUT part. The largest they have is a 20k LUT device, so don't know if that is a show stopper for you.Article: 86231
Hello all, I am having a strange thing happening. This was not urgent, so i kinda did not post it previously... I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4 (one) When running the entire ISE flow, everything is smooth, the PROM files are generated using two devices 1804v, one 100% full and another 65% full. FPGA is fully functional and everything is working. (two) When running the same using command line, i get that PROM files are generated using two devices 1804v, one 100% full and another 62% full. When programming FPGA with this configuration, nothing is working. the LEDs which blink once a second per different clock domains are "dead"... I have noticed this with both ISE 6.3 and 7.1 The question is what the hell is happening here? Thank you all for your time and attention Sincerely, VladislavArticle: 86232
Hello! Impact fails, if I want to download a partial bitstream after a normal working fully bitstream has been downloaded. Can anybody tell me why and how is it done the right way?, thank you, Markus ------------------------------------------------------------------- iMPACT gets following error during downloading the partial bitstream: "WARNING:iMPACT:2137 - Error shows in the status register, CRC Error bit is NOT 0." My system breaks down from this moment on (neither LED-movement nor RS232 output) After this, I am not able to initialize the FPGA once again with a full bitstream: "ERROR:iMPACT:1210 - '2':Boundary-scan chain test failed at bit position '1'. A problem may exist in the hardware configuration. ..." For the partial bitstream I use bitgen: "bitgen -w -g activereconfig:yes -g persist:yes -g startupclk:jtagclk -r download.bit changed_system.ncd changed_system_p.bit" I use iMPACT Version 6.3.02iArticle: 86233
Hi all, I want to add two 6 bits signed digit. Something like 6'b10_0110, the MSB '1' is negative digit,other'00100' is absolute value. Or Something like 6'b00_0110, the MSB '0' is positive digit,other'00100' is absolute value. How to design a signed adder to add these too signed digit? Now I convert it to 2's complement,add, and convert it to signed digit. But the overflow control seems not be a easy task. BTW, I use verilog. Any suggestions will be appreciated! Best regards, DavyArticle: 86234
Project VeriPage announces three new articles this month. As always, these and all other articles on Project VeriPage are free. For the complete list of articles, please go to: <URL: http://www.project-veripage.com> (a) Property Specification Language (PSL) Tutorial: Part 3: We wrap up our discussion on PSL with its verification and modeling layers and various miscelleneous features that it offers. <URL: http://www.project-veripage.com/psl_tutorial_7.php> (b) SystemVerilog Dynamic Array: This articles shows how to work with a dynamic array in your simulation environment without declaring its size beforehand. <URL: http://www.project-veripage.com/dyn_array_1.php> (c) SystemVerilog Assertion: Part 2 - Introduction to Sequences: After the Boolean Expression Layer, we move to the Sequence Layer and discuss how to define a sequence and operators that work with sequences. <URL: http://www.project-veripage.com/sva_4.php>Article: 86235
Rob, Yes. One, I count one advantage (after my Romainian role model: The Count on Sesame Street). Austin Rob wrote: > I'm designing with a V2PRO and its config PROM. I noticed that I will need: > > 1. VCCint (PROM) = 1.8V > 2. VCCint (FPGA) = 1.5V > 3. VCCAUX = 2.5V > > The system will only deliver me 5.0V and 3.3V which means that I will need > to generate the above voltages. If I were to use an Altera Stratix part, > and its config device, I would only need to generate the 1.5V--much cleaner. > > I have tight board space constraints which make working with Xilinx much > more difficult. Seems as if Altera has an advantage in this area?? > >Article: 86236
Sean, http://www.xilinx.com/prs_rls/silicon_vir/0568fx60_spirent.htm I apologize that the fx20 did not come out as the first part. The fx60 did. I would suggest in future that you work more closely with your FAE. Perhaps even voluneer to be in the early adopter program if you want to be first. It is often an issue to get the first of any specific part/package: in this case, there was mask making issue that led to delays on two parts. Just bad luck. As it says in the press release, the worst case MGT stress pattern passed error free with no issues. That was a first for Spirent: they had never seen that happen ever before. They actually gave the team a standing ovation. In all my years as an engineer, I have never heard of passing a test getting applause from the customer.... Austin Sean Durkin wrote: > Hi, > > has anyone ever seen a Virtex-4 FX-part with RocketIO-MGTs? Any FX > bigger than the FX12? And I'm talking about seeing it in real life, > holding it in your hand, putting it on your boards, not just seeing a > Xilinx-manufactured, unpowered eval-board at some trade fair... > > Originally, we wanted to use a Virtex-4 FX20 in our latest design. Cool > new part for a cool new prototype, we thought... so we ordered some > engineering samples through our distributor (Insight Memec)... first > they said "No problem, you'll get them in June", so we put it into our > design... after all the schematics were done, and the layout halfway > through, it was "Sorry, you won't get the devices until late July", > which was of course too late, so we had to go back into the design, > change everything to Virtex2 Pro, and cancel the order on the Virtex-4 > parts. > > Now I wanted to use the FX20 for the next design... thinking "Hey, they > told us we would get it in July", so I put it in the schematics, and > ordered the FX20. So now the distributor says "No way, no parts > available, not even engineering samples, production doesn't even start > before October, don't even bother ordering." Now last I heard was that > *mass production* was supposed to start in October, but engineering > samples should be available long before that. Anyway, again I have to > re-do half of my schematic, again I have to waste a lot of time for > nothing, and again, I can't use a Virtex-4. Meaning that for us Virtex-4 > is now dead for all designs and projects this year. > > What's up with that? Is there some problem with the MGTs? I can't even > get a single development board with FX20 parts or bigger, they all have > unknown availability dates. FX12 is no problem, anything bigger I just > can't get my hands on. > > Did they find some serious bug in the silicon and then decided to stop > production or something? > > cu, > SeanArticle: 86237
One more thing to add I am using WinXP Vladislav "Vladislav Muravin" <muravinv@advantech.ca> wrote in message news:90zue.74585$Kk4.909792@news20.bellglobal.com... > Hello all, > > I am having a strange thing happening. > This was not urgent, so i kinda did not post it previously... > > I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4 > > (one) When running the entire ISE flow, everything is smooth, the PROM > files are generated > using two devices 1804v, one 100% full and another 65% full. FPGA is fully > functional and everything is working. > > (two) When running the same using command line, i get that PROM files are > generated > using two devices 1804v, one 100% full and another 62% full. When > programming FPGA with this configuration, > nothing is working. the LEDs which blink once a second per different clock > domains are "dead"... > > I have noticed this with both ISE 6.3 and 7.1 > > The question is what the hell is happening here? > > Thank you all for your time and attention > > Sincerely, > Vladislav >Article: 86238
Davy wrote: > Hi all, > > I want to add two 6 bits signed digit. > Something like 6'b10_0110, the MSB '1' is negative digit,other'00100' > is absolute value. > Or Something like 6'b00_0110, the MSB '0' is positive > digit,other'00100' is absolute value. > > How to design a signed adder to add these too signed digit? > Now I convert it to 2's complement,add, and convert it to signed digit. > But the overflow control seems not be a easy task. > BTW, I use verilog. > > Any suggestions will be appreciated! > Best regards, > Davy ******************************************************************************** Davy, If the data is in 2's complement then just add the two numbers together and you will get the right answer. Remember, 2's complement addition is the same as straight binary. As far as the over flow is concerned, if the sum is not going to exceed the max possible result defined by your resolution(#of bits) you should be fine. Otherwise, just increase the width of the result to compensate for greater result. for example (-7)+(-7) in decimal is (101) + (101) in 2's complement the result (if you do not compensate the result by adding a bit is = (010) => +2 (WRONG!) whereas by adding a bit to the result will take care of this problem 101 +101 ------ 1010 ->(-14) decimal (CORRECT!) Hope this helps. -MORPHEUSArticle: 86239
The TechXclusive paper by Ken chapman...suggested by John_H is the best to tackle your problem. I used it to design my dc-cancellation ckt. It works. Def use the paper to design...unless you have a better solution..let me know -MORPHEUSArticle: 86240
For what it's worth..we were told by visiting Xilinx engineer to NOT upgrade our tools to 7.x but instead wait for 8.1 release in August... Paul C "Ray Andraka" <ray@andraka.com> wrote in message news:kmnue.17953$FP2.12419@lakeread03... > Ray Andraka wrote: > >> Unless you are putting RLOCs on the DSP48's. That is still broken in >> SP2. Last version it worked correctly in is ISE6.3 SP3. ise7.1 SP3 >> fixes that, but has a problem with the C ports on the DSP48 (the C Port >> is physically shared by two DSP48 slices, but shows up individually for >> each slice in the library. If both DSP48s do not have the same value >> tied to the C Port, its CE input and its reset input, the mapper crashes. >> If you are careful, that isn't a problem. The problem comes if one DSP48 >> uses the Cport and one doesn't, you still have to specify the same inputs >> on both. That creates a packing problem unless you've pre-packed the >> DSP48s making sure both Cports are wired identically. >> > I was just told that they managed to get the CR for the Cport error into > SP3, so it sounds like that might work correctly. Time will tell:-) > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com http://www.andraka.com > "They that give up essential liberty to obtain a little temporary safety > deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 86241
Tommy Thorn wrote: > > My sram memory interface works, but I've had to insert an idle cycle to > make the read data settle. > > Reading the spec for the IDT71V416S10 it claims both tAA and tRC to be > 10ns, with a tOH hold time of 4ns min hold time. I thus expected > something like this to work: > > always @(posedge clk100MHz) begin > sram_a <= <new addr>; > latched_data <= sram_d; > end > > where latched_data is from the previous address obviously. It worked > fine under simulation against the idt71v416s10.v model from IDT, but on > the board it wasn't reliable. > > I didn't supply any timing constraints for the FPGA pins connected to > the SRAM and I suspect that to be the problem, but I'm a bit unsure what > should I give as constaints. Suggestions? The problem is that you generate an address, it takes some finite time to actually get out to the pins, then more time to get to the SRAM, then the 10nS to get valid data, then more time to get back to the FPGA, and then a setup time to acquire latched_data. All of which adds up to more than the 10nS cycle time of your clock. But because the tAA is a worst case number, it looks like the actual times are adding up to very close to 10nS, and hence unreliable data. With that clock rate and that device, you should use two clocks to do a read. Timing constraints won't fix it. If you are trying to supply a new address on every clock and capture the data, then you need a faster device. For that kind of operation with a 100MHz clock, I would suggest that you use a synchronous SRAM.Article: 86242
Wasn't there once on Altera's website the possibility to extend the NIOS2 subscription? Any reason it was removed? thx rickArticle: 86243
Hello Does somebody know who is responsible for the GNU sources of the NIOS2 toolchain? Since nothing was ever put back into mainstream gcc/binutils like uClinux support I assume it is Microtronix? thx rickArticle: 86244
The HALT pin on the debug connector of the ML310 is defined as low-active. In the reference design the sense of the signal is then inverted to generate the high-active DBGC405DEBUGHALT signal that goes to the processor. So, if you use the pin on the connector to halt the processor you need to tie it to a '0'. You only need to generate an interrupt if the software sets MSR[WE]. Asserting/deasserting DEBUGHALT does not require an additional interrupt. - Peter Jagadeesh wrote: > Hello Peter, > > Thanks a lot. > > Actually in my design JTAG controls the DGBC405DEBUGHALT pin of the PPC1, i just OR-ed debug signal from JTAG and debug halt from my core such that both of them can control the processor execution. To my suspect i directly assigned halt signal '1'so that processor halts at begining of program,but unfortunately it didn't stopped. > > Do i need to take some other aspects into consideration to halt PPC1? > > You mean that once we send processor to debug halt mode we need to give interupt to bring back for resume execution apart from making DBGC405DEBUGHALT '1'? > > Thnaking You. > > With Regards, JagguArticle: 86245
Hello, I'm a graduate student working with Xilinx ML310 board. I have general question about using iMPACT. When I tried to download the bitstream using IMPACT, it fails 70~80% at the end of downloading showing "Download failed". There is also some case of successful download of 20%. But, I'm disappointed with this high percentage of download failure. Does anyone have similar problem with me? I'm waiting for your advice. Thanks. -- Byung Hwa Kim ( bhkim91@yahoo.com )Article: 86246
I am using Altera's Cyclone EPIC20F4007 Development board and nios II processor. The problem is that I am unable to set the clk freq. from 50 Mhz to 20 Mhz and get the board working. I have changed the clk setting in the SOPC to 20 Mhz and also changed the SDRAM_CLK, PLD_CLKOUT and CLK settings to 20 MHZ by factor 2/5. I have also tried different phase shift settings for SDRAM_CLK(phase shift is -63 degrees in the 50 MHZ, so I supposed it should be-25.2 degrees in the 20 Mhz???), but every time when I try to flash some program to the system via NIOS II IDE I get the next error: sing cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: OK Reading System ID at address 0x021208B8: verified Downloading 01000020 ( 0%) Downloading 01010000 (86%) Downloaded 75KB in 0.9s (83.3KB/s) Verifying 01000020 ( 0%) Verify failed Leaving target processor paused Could anyone give me good advices to solve this problem?? ThanksArticle: 86247
Rick, Altera maintains the GNU toolchain for Nios II. As for uClinux, I am quite ignorant on the matter (I am not sure if any toolchain changes were required). You might ask in the uClinux area of www.niosforum.com. Altera *usually* has all these toolchain sources available on public FTP - I noticed your mentioning that they were removed in a separate post so I had a look and it appears that I cannot locate them either (the sources for all prior versions were up there as of a couple of months ago when I last checked). I am assuming this is an oversight and will follow-up to see what happened. Jesse Kempa Altera jkempa -at- altera -dot- comArticle: 86248
Bump! So, no comment from the otherwise very active Xilinx representants? I'll rephrase my question: Will the Xilinx webshop get an increase or decrease in the the selection of FPGAs in the near future? Of course, a decrease from the single part would mean FPGA shop gone... I just want to find a place to buy those nifty chips, you know :-) DJ -- "Dr Justice" <sorry@no.spam.wanted> wrote in message news:98hte.1609$vS6.49@amstwist00... > Following the Spartan 3 availability threads, I visited the Xilinx webshop. > The only FPGA on offer there is the Spartan 3. IIRC the webshop used > to have a much better selection. It seems a bit strange to me to reduce > the (FPGA) offerings to only 1 kind of FPGA and 1 handbook for > a different FPGA. > > Questions: > Why isn't the full product range available at the webshop? > What are the plans for the webshop? > Where's the best online place to buy Spartan II in low volume? > > DJ > -- > >Article: 86249
Hello Byung, I haven't looked at the specifics of that board but here are a few general things to try: 1) What speed do you have the cable configured to run at? Try a slower speed if possible. If you have a signal integrity issue this will help but it will take longer. 2) There are some Xilinx devices (like some Spartan 3) that have a bug in the readback circuitry so they won't verify all the time. Get the errata for your device from Xilinx website and see if this is the case and if it applies to your device (you may have to compare some information on the chip like mask ID). 3) Try the ID Code looping by right-clicking on the device in Impact. Make the number huge and let it run for a few minutes. That will give you a good idea if its a signal integrity issue as well. If it fails you have one. If it passes you may or may not since the data pattern isn't always the worst case. If you do have a signal integrity issue then its a problem on the board and there won't be much you can do other than mod'ing the board yourself and adding buffers. I'd speak with the manufacturer before doing that. In fact, they should have a good idea if they have an issue since they would have heard from other customers if they did. Those are some basic things to try. The JTAG bus is pretty robust and reliable in general but I've had problems with each of these issues at different points in time. James. On Thu, 2005-06-23 at 09:11 -0700, bhkim91@yahoo.com wrote: > Hello, > > I'm a graduate student working with Xilinx ML310 board. > I have general question about using iMPACT. > When I tried to download the bitstream using IMPACT, it fails 70~80% at > the end of downloading showing "Download failed". > There is also some case of successful download of 20%. > But, I'm disappointed with this high percentage of download failure. > Does anyone have similar problem with me? > I'm waiting for your advice. > Thanks. > > -- Byung Hwa Kim ( bhkim91@yahoo.com ) >
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