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stud_lang_jap@yahoo.com wrote: > Hello Guys, > I am finding difficult in probing virtex 2pro using chipscope. > I am using chipscope pro logic inserter. > I have following doubts regarding it > 1. In my top module (also netlist)i have any IP core which i have > integrated and its black box IP(EDF netlist).I cannot see the black box > IP in the TOP module in chipscope but its present in TOP module > Netlist. I can view all the module except the netlist module . So i am > not able to connect the signal of EDF IP to trigger signal. Why is it > so?? Which version of ChipScope Pro are you using? Version 7.1i added the ability to Insert probes within any portion of a design regardless of the type and number of netlists used. In other words, all EDIF or NGC files are assembled before the Inserter is opened, so any design flow (Modular Design, IP cores, design core resuse, etc) is supported. Any encrypted IP cores will still remain hidden for security reasons. If you are using ChipScope versions prior to 7.1i, this can still be done, albeit manually. Simply run NGCBUILD on your top level netlist before opening the Inserter, as documented in Solution #20185 > 2. Can i not connect the IO port signal of TOP module to triggering > signal of chipscope?. When i connected it gives error in implementation > saying multiple drive. Is any other way to view the IO port signal > along with the internal signal. You are not permitted to connect ChipScope probes to IO ports, as the logic required for the probes are built with general logic and must be connected to internal nodes. Connect your probes to the internal sides of IO buffers to get the same data. For example, if you are using XST, connect your probe to MYPORT_IBUF instead of MYPORT, etc. > > > Thanks and regards, > Williams thanks, David Dye Xilinx ColoradoArticle: 86151
For those who have the same problem. Altera have new files for reprogramming the MAX chip. And so the card will boot at every power-up. The release is dated by 13 June 2005 !!!! patrick.melet@dmradiocom.fr (Patrick) wrote in message news:<54b3002.0506202349.2d016709@posting.google.com>... > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<3hoeseFi5l05U1@individual.net>... > > "Patrick" <patrick.melet@dmradiocom.fr> schrieb im Newsbeitrag > > news:54b3002.0506200605.3dadb7cc@posting.google.com... > > > > > Perhaps it's be better if the RESET is after the 3.3V power-on ? > > > > Use a voltage monitor that releases the reset after ALL voltages are valid. > > > > Regards > > Falk > > > We add a RC circuit beetween the reset from the Stratix circuit to the > MAX circuit. So the MAX is resetted after the 3.3V is ON and sometimes > the program from the flash don't boot !!! > This is a big problem for our system which uilizes 3 boards... > My Support from Altera don't explain me what's happen... > > So is there anybody who have this problem with these EP1S25 cards and > is there a solution ?Article: 86152
On Wed, 2005-06-22 at 16:19 +0200, Antti Lukats wrote: <snip> > so Altera has been simple BS the customers - or maybe there is a secret > place for MAX2 IEEE1532 information ??? Which is worse? If Altera is just promoting BS and market-spin to their customers they should they don't respect their customers. If Altera goes to the effort of implementing and supporting IEEE1532 and hide it from their customers they show that they don't respect their customers. At least the little guys who don't have the contacts and big money to suddenly make the data appear (if that is indeed the case--I have no idea). Hmmm, the conclusion is the same in both instances. That said, this could equally be applied to just about every multi-national known to mankind. James.Article: 86153
Hi JJ, > Well I would say for their time the 8086, Z8000, 68k were all > reasonably well crafted as VLSIs go... Perhaps from a physical layout, but it was the architecture I was commenting on. > As for architecture Intel was only upgrading the 8080 to a 16bit arch, In a terribly feeble way! There were some much better architectures available (and do-able) at the time. > Remarkably all these design teams had very little CAD available to them > for most of the general designs... I'm not sure I agree with that. I worked on a VLSI design system from ComputerVision back in 1978... Regards, AustinArticle: 86154
Actually the bigger issue with 5V tolerance is how the 3V part tolerates 5V input signals - this is one of the nice features of (some of) the Coolrunners which I use. Driving 5V logic from 3V should be no issue - as it was mentioned, HCT, ACT etc. parts have been available for > a decade. However, it should be noted that "TTL compatible" output means more than just guaranteeing output voltage >2.4V for 1 and < 0.4V for 0; it means being able to sink 1.6 mA and to source 400 uA (all out of memory older than 15 years, hope I got it right). Dimiter ------------------------------------------------------------------------- Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com -------------------------------------------------------------------------Article: 86155
Hi Marco,
> Hallo, I followed what you said. I have made a for cicle to write to video
the addresses and sequential addreesses are, in example (decimals -> hex):
> 1998595456 -> 77200000 1998605056 -> 77202580
Those hex values don't correspond to those decimal values at all.
0x77202580 is 1998595456 in decimal.
> How is it possible? Second should be 77200001, I think.
If the value of the pointer "display" is 0x77200000, then the
address of the element (0,0) is &((*display)[0][0]) and will
also be 0x77200000. The address of the "next" element is
&((*display)[0][1]) and will be 0x77200001.
The address of the element (1, 0) is &((*display)[1][0])
and will be 0x77200000 + WIDTH. If the hex values
you gave above are correct, the difference between the
two addresses is 9600 - a "nice" number which is probably
not an accident. Is this one of your screen dimensions, by
any chance?
> I have tried also to copy data into one address:
> (*display)[y][x] = 0xFF;
> But when I print to video (*display)[y][x] I see 0, not 255.
That is a little surprising. I would triple-check your hardware is
all connected up correctly. If you have some other data memory
region in your design, try this test: allocate the display memory
there (by changing 0x77200000 to something else) and see if
you can read and write the first element succesfully.
Another thing to do is declare your array as "volatile":
volatile unsigned char (*display)[Y][X];
This will force the compiler never to optimize away reads and
writes of this array. Otherwise, it may think they have no effect
and not bother to perform them.
Cheers,
-Ben-
Article: 86156Hello, If you instantiate a memory manually, then you might not specify the valid path to MIF file. I think that when you use the memory using the instance template generated by CoreGen, there is a link to the MIF file, check if this link is valid. If it is, but you still do not get the right values, check with xilinx, i.e. you are using compiled libraries, may be there's a problem with the compiled model? Any possible limitations of this model? Cannot really think of anything else... Vladislav "alpha" <zhg.liu@gmail.com> wrote in message news:1119452899.817310.97660@g44g2000cwa.googlegroups.com... > Hi, > > I am trying to use MXE-III to simulate a design (Target V4-FX12) > including a block memory core generated by Coregen (EBKMEMDP_V6_2). > ModelSim DOES NOT initialize memory's value defined in generated > "XXX.mif" file. > Can anyone give some clues? This issue bother me 2 days. Thanks. > > Alpha >Article: 86157
Jedi, Antti, Unfortunately the only official support of this nature is to allow your FPGA logic to access the SPI config port (rather than your host PC doing this). This is done by using either the EPCS serial flash controller or ASMI memory interface peripherals in SOPC Builder. Create an Avalon interface from your design to drive the peripheral you use and proceed from there. Access to extending the JTAG chain in the device and driving these from the host PC are, at least for now, proprietary. Jesse Kempa Altera jkempa -at- altera -dot- comArticle: 86158
yes is only a register but the functionality of this register you must implement self in your VHDL or Verylog designArticle: 86159
Hi Bert, Synopsys DC has actually two VHDL frontends (parsers). The standard one, which is enabled by default, is just crap. It only suppoprts an extremely limited number of VHDL constructs, which makes it almost unusable for modern parameterizable designs. The newer one, called PRESTO, must be explicitly enabled. You can do this by setting the 'hdlin_enable_presto_for_vhdl' to 'true' in your dc.setup script. Hope this helps.Article: 86160
Hi,
I am trying to read file from CF using SysAceMPU with a V4SX35 fpga on a
ML402 board.
I have connected the MPA, MPD, OE, CE, WE, SysAceClk, MPIRQ and IRQ(to
microblaze, opb-bus, ilb and dlmb). My c-code
SYSACE_FILE *psFile;
psFile = sysace_fread("A:\\XILINX\flast.txt", "r");
just freezes in XMD.
Can someone help me with this problem.
Any suggestion is appreciated.
Thanks,
Krishna.
Article: 86161<kempaj@yahoo.com> schrieb im Newsbeitrag news:1119456961.738656.316600@g14g2000cwa.googlegroups.com... > Jedi, Antti, > > Unfortunately the only official support of this nature is to allow your > FPGA logic to access the SPI config port (rather than your host PC > doing this). This is done by using either the EPCS serial flash > controller or ASMI memory interface peripherals in SOPC Builder. Create > an Avalon interface from your design to drive the peripheral you use > and proceed from there. > > Access to extending the JTAG chain in the device and driving these from > the host PC are, at least for now, proprietary. > > Jesse Kempa > Altera > jkempa -at- altera -dot- com > ok, at least we now know 'what is official' - To Altera - the ASMI and JTAG scan primitive has been used by different people outside the 'official' scope, partially by doing some RE on subject as the official documents hide some information about such useage. hiding some features from the customers is not a good idea, IMHO. Actually I feel its rather stupid thing todo. You cant hide whats already partially visible. Any such info hiding attempts just make people pissed off. And it would not stay hidden anyway, nothing ever has. most of the info to access JTAG primitive is there http://wiki.openchip.org/index.php/Altera:JTAG ASMI direct useage without SOPC has been documented also several times by non-altera 3rd parties. AnttiArticle: 86162
On 21 Jun 2005 09:40:16 -0700, "Nemesis" <nemesis2001@gmx.it> wrote: >Maybe my question was not so clear, I just wanted to know if these >BRAMS that shares routing resources with the Multipliers will be >available for other cores that need them (like the FFT i.e.). The BRAMs are still available when using the co-located multiplier, except for BRAMs in the widest data path mode. I.E. you can use the co-located BRAM in x1, x2, x4, x9 mode, but not x18 . This is because the BRAM and MPY share the connection resources to the rest of the fabric. In x18 mode the BRAM uses everything. In the narrower modes, there is enough connection resources remaining to fully support the MPY. Philip Philip Freidin FliptronicsArticle: 86163
Jeff Cunningham wrote: > lovesinghal wrote: > > > Currently, on average, a consumer (who may own cellphone, camera, > > camcorder, ipod, etc.) owns zero FPGAs. Do you see this ratio of number > > of FPGAs/consumer changing? > > There was a thread here recently where someone saw a Spartan3 part in > their new flatscreen TV. Here is a link to some of the Consumer Products which use FPGA's today. http://www.altera.com/corporate/cust_successes/customer_showcase/view_industry/csh-vindustry-consumer.jsp Enjoy, Subroto Datta Altera Corp.Article: 86164
On 21 Jun 2005 23:37:42 -0700, "GaLaKtIkUs™" <taileb.mehdi@gmail.com> wrote: >Hi all! >I'm starting a PhD project in the field of design of SoC systems on >FPGA. >I would like to buy an FPGA board with the following features: >-Sufficient FPGA for small to middle SoCs (OpenCores based cores: >OR1200+Sound+LCD/VGA+USB+UART+Custom cores) >-Sufficient input/output units (USB/PS2/VGA/LCD). >-Ressources for testing. for minimizing the use of lab equipments => >this card will be for use at home. >-Sufficient Flash+RAM. > >All the variants are welcome. > >Another requirement ... I will have to work with the jbits system (for >partial reconfiguration) ... are there any requirements for FPGA boards >?? > >Thanks ! You can find an extremely uptodate list at: http://www.fpga-faq.org/FPGA_Boards.shtml Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 86165
I made a mistake in writing numbers... decimal -> hex 1998585856 -> 77200000 next address: 1998585896 -> 77200028 The display is black/white 320x240 pixels. I defined: height 240 width 40 (because 320/8 = 40. I decided to write 8 bit at a time through software.) ...display[height][width]... It seems it jumps of 40 from one address to the next. Thanks MarcoArticle: 86166
Does anyone know were I can get a DES core for the Xilinx EDK the Target is the Virtex 2 Pro? I need this core to interface to the PLB (processor local bus) or the OPB (on board processor bus). So that the only thing a user has to do is to load the core and send data to it and receive the output. thanks, NRArticle: 86167
"P. Royla" <Nightstorm@gmx.ch> schrieb im Newsbeitrag news:d9b50a$uhh$1@hermes1.rz.hs-bremen.de... Have a look at the floorplanner for the right names. Regards FalkArticle: 86168
"BQ" <spammalatuamamma@gmail.com> schrieb im Newsbeitrag news:mkfue.16513$yM4.241008@twister2.libero.it... > In my project, which uses an Altera Cyclone EP1C12, I need to generate a > lot of different frequencies, such as f=10Mhz, 1MHz, 2.5MHz, 250kHz, etc. > I used counters but quartus' design assistant complains that I'm using > gated clocks. Are there better solutions than counters to achieve what I > need? Or better ways to implement frequency divisors? The counters are right, but don't use the outputs as real clocks. Run everything at the highest frequency (I guess 10 MHz) and use clock enables for the slower parts of the logic. Keeps things easy and safe. Regards FalkArticle: 86169
Antti Lukats wrote: > <kempaj@yahoo.com> schrieb im Newsbeitrag > news:1119456961.738656.316600@g14g2000cwa.googlegroups.com... > >>Jedi, Antti, >> >>Unfortunately the only official support of this nature is to allow your >>FPGA logic to access the SPI config port (rather than your host PC >>doing this). This is done by using either the EPCS serial flash >>controller or ASMI memory interface peripherals in SOPC Builder. Create >>an Avalon interface from your design to drive the peripheral you use >>and proceed from there. >> >>Access to extending the JTAG chain in the device and driving these from >>the host PC are, at least for now, proprietary. >> >>Jesse Kempa >>Altera >>jkempa -at- altera -dot- com >> > > > ok, at least we now know 'what is official' - > > To Altera - the ASMI and JTAG scan primitive has been used by different > people outside the 'official' scope, partially by doing some RE on subject > as the official documents hide some information about such useage. > > hiding some features from the customers is not a good idea, IMHO. Actually I > feel its rather stupid thing todo. You cant hide whats already partially > visible. Any such info hiding attempts just make people pissed off. And it > would not stay hidden anyway, nothing ever has. > > most of the info to access JTAG primitive is there > > http://wiki.openchip.org/index.php/Altera:JTAG > > ASMI direct useage without SOPC has been documented also several times by > non-altera 3rd parties. > To: whom it may concern Not only ASMI usage but also EPCS replacement has been documented and tested with several vendors. One vendors already did it by himself...I can post his repliy here if anybody wants (o; I rather see it as a great feature and "kuul" making stuff like USER JTAG available and documented...doesn't it give some advantage over other vendors? Speaking of hiding I don't really see also the point in removing the NIOS toolchain sources from ftp server, as done some 2 or 3 weeks ago...well...they were obsolete and software developers doing work on BSD systems don't have any chance to use the eval versions toolchain (o; rickArticle: 86170
Hi! I would like to know if the Xilinx Virtex 4 offer the possibility of partially reconfigure bitstreams directly (as in the virtex II using the jbits library). If yes ... what are the hardware (requirement for the fpga board) and software (are the libraries similar to jbits?) requirements ? Thanks in advance. Cheers !Article: 86171
"GaLaKtIkUsT" <taileb.mehdi@gmail.com> schrieb im Newsbeitrag news:1119466002.203505.29190@f14g2000cwb.googlegroups.com... > Hi! > I would like to know if the Xilinx Virtex 4 offer the possibility of > partially reconfigure bitstreams directly (as in the virtex II using > the jbits library). > If yes ... what are the hardware (requirement for the fpga board) and > software (are the libraries similar to jbits?) requirements ? > > Thanks in advance. > Cheers ! > Jbits is dead there is no working useable partial reconfiguration flow for V4 at the moment. I guess there is some work in progress, but nothing readily available. ... nomansland its possible and doable, but you are alone on the path... anttiArticle: 86172
nrivera.eng@gmail.com wrote: > Does anyone know were I can get a DES core for the Xilinx EDK the > Target is the Virtex 2 Pro? I need this core to interface to the PLB > (processor local bus) or the OPB (on board processor bus). So that the > only thing a user has to do is to load the core and send data to it and > receive the output. > > thanks, > NR We have a generic DES and 3DES IP Core which you should be able to adopt to PLB and/or OPB bus. Please see Free IP section on our web site. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 86173
I using AVNET's Virtex II pro development kit. They have included a simple memory project with the board which using xilinx EDK. I want to scrap their memory controller and EDK based project (all the implementations are hidden through the use of countless wrappers), and design my own simple memory controller for on board SRAM and FSM to handle transactions with their PCI bus controller (Spartan IIe) Does anyone have a suggestion as to how to approach this. I have never designed a memory controller before. I am trying to use the board as a coprocessor in a rapid image classification system - it needs to receive data via the PCI bus and operate on it, then put it in a shared SRAM, so it can be accessed via the PCI bus. thanks -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 86174
Hello, I am not getting a clear undertsanding of the debugging part of microblaze. I tried reading many docs. but i dont undetsand the diff. between doing executable and xmdstub. 1. If i have a debug module in my system, how does it work to debug my code? 2.Do i still choose the xmdstub in the compiler settings??? 3. According to my understanding this xmdstub is a software code which goes at mem. loc 0x0. But then doesnt it overwrite the interrupt jump which is at 0x10??? Please share ur understanding..I am toltally confused and need to know this for my project. Thanks.
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Compare FPGA features and resources
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