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I am using a MAX II part in a new design with 3.3V supplies. I understand why the inputs might not be 5 volt tolerant. Altera states that the outputs are not 5 volt tolerant when driving CMOS but are OK for TTL. Since TTL is essentially dead, I'm not sure this is of any real benefit, however this is not my main concern. I don't see why there would be any problem driving a CMOS input provided that the CMOS input will accept 3.3V signals as high. There certainly isn't going to be any significant current flow into the CMOS gate. I think this situation is similiar for a number of FPGAs as well. Could someone enlighten me as to the reasons why, instead of Altera's "because we said so" -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 86026
Hi, I was wondering how can LVPECL/LVDS buffers be implemented in system generator. I am getting illegal buffer when I tried that. Thanks in advance, -ChintanArticle: 86027
Hi Luc, > I found: > Lattice starter has included Leonardo/Precision RTL and Synplify, no > ModelSim > Xilinx ISE WebPack : XST, no Leonardo/Precision, no Synplify, no > ModelSim > Altera QuartusII Web Edition: support for Synplify, Precision and > Modelsim? > > I know it's a simple comparison, but I would like to be clear on this. You should be the expert on the Lattice kit, so I won't comment on that. Quartus Web Edition includes QIS - which is "Quartus Integrated Synthesis", which by now is a pretty decent VHDL/Verilog synthesis tool - and that's coming from someone who used to do tech support for Leonardo. Also, as you stated, Quartus Web Edition indeed has support for, but does not _include_ an RTL simulator. However, it does include a built-in gate-level (functional or timing) simulator, which can also do parts of the design's power analysis. I also understand that there's a hugely crippled, but free version of Modelsim that you can get from Xilinx (this must cost them a fortune), but which, as long as you only code RTL, you can also use for Lattice, Altera, Actel and whichever other vendor, as long as you initially mentally intend to target a Xilinx ;-) However, I haven't read the EULA to the letter. Best regards, BenArticle: 86028
I'm using EDK 7.1.1 and there is an option in IP Import Wizard for "S/W Reset and Module Information Register" that includes device driver support as well. Paul Joey wrote: > > Hi > > I would like to know how we can reset an OPB/PLB Peripheral during runtime. > > Thank you > JoeyArticle: 86029
Jedi wrote: > Luc wrote: > >> Rick, >> >> I can't speak for LatticeEC in specific, but I know that some >> designers tend to write their VHDL very specific for one family. Than >> it will be hard to get the same performance from another device. >> >> I.e. does the compiled design make use of the IO cell? Switching this >> option of can save quite some time (Clock to Out). >> >> Regards, >> >> Luc > > > Actually I test with an out-of-the-box t80 design... > > I know that Altera Quartus does some good job in > using RAM blocks instead of registers automatically > since version 4.1 or 4.2 8and old 2.2 I think) whereas > the backend tools in ispLever and Actel Libero don't. > Hmm..actually t80 performance degraded continiously in Altera Quartus since version 4.1 with same standard settings (and no automatic RAM block placing). Same is true for other similar CPU cores as well... rickArticle: 86030
amko wrote: > ISE Webpack is definitly better choice than Altera Web Edition. Web > Edition does not generate image files (pof. and sof.). In additional > ISE Webpcack has minimal limitations and only big disadvantage is core > generator which is not included in the Webpack. It means you can not > use Xilinx FIFO, DP RAM,... but anywhere you have PLL (DCM)... > Synthisiser XST is also very good and in most case you dont need it > Leonardo or Synplify... > Free Simulator tool (Xilinx Modelsim ) is also avaiable with ISE > Webpack.... > > In the other words you can do it much more with ISE Webpack... > > Regards , > > Amir As Jesse mentioned, Altera's Quartus II Web Edition does in fact generate .pof and .sof programming image files and includes everythiong need to design for Altera's latest CPLD and low-cost FPGA device families. Quartus II Web Edition includes the Quartus II integrated synthesis feature and will work with all of the leading third-party synthesis tools on the market. Quartus II Web Edition in fact includes most of the same features included in the subscription version minus some device support for the largest high-density FPGA devices and HardCopy Structured ASICs. A comparison between Quartus II Web Edition and Quartus II subscription edition software can be viewed on the Altera web site at http://www.altera.com/products/software/products/quartus2web/features/sof-quarweb_features.html. Quartus II Web Edition also supports Altera's OpenCore Plus evaluation IP so you can configure and evaluate IP in hardware before purchasing an IP license. OpenCore Plus IP can be downloaded from the Altera IP MegaStore at http://www.altera.com/products/ip/ipm-index.html. I hope this information is helpful to you. Regards, Rob Kruger rkruger-at-altera.comArticle: 86031
This is the case of very cautious worst-case specifications. If the CMOS output is truly complementary (most of them are nowadays), and there is no pulldown load, Voh will in reality be exactly = Vcc (although the specification will probably mention a lower value.) So Voh min = 3.0 V or slightly higher. A True CMOS input has an input threshold around 40 to 60% of Vcc ( or 30 to 70%), and Vcc might be as high as 5.5 V So the input threshold might be well above 3 V. Now you see that this interface does not work "worst case" If the CMOS input is called TTL (just an indication of input threshold, no other realtion to the bipolar TTL technology), then the input threshold is artificially made much lower, around 1.5 V, and the interface works perfectly. Clear? Peter Alfke, Xilinx ApplicationsArticle: 86032
Hi, I think the important distinction to make is the distinction between TTL signaling levels and TTL parts. I see many people (including myself) who use "TTL" and "seventy four hundred series devices" interchangably. > I don't see why there would be any problem driving a CMOS input provided > that the CMOS input will accept 3.3V signals as high. There certainly isn't > going to be any significant current flow into the CMOS gate. What you cite is exactly the issue. If a 5.0v CMOS device has a Vih,min that is 90% of the 5.0v supply rail, your programmable logic device output isn't going to satisfy the requirement -- because it will only be able to pull up to 3.3v. Counterpoint, consider a 5.0v TTL device, where the Vih,min might be around 2.4 volts. Your programmable logic device will be able to pull up higher than what is required, so it will work properly. At the end of the day, the best advice I can offer you is to read the datasheets of both parts and carefully consider the signaling levels and thresholds, and don't forget to design for some noise margin. EricArticle: 86033
Marc Randolph wrote: > Jeremy Stringer wrote: > >>I'm starting a new project at the moment, and I'm looking at upgrading >>to ISE 7.1, since I prefer not to change synth/par tool versions >>mid-project. I noted that a number of people complained about 7.1 when >>it first came out, but also noted that Service Pack 2 is out now. Can >>anybody comment on the state of ISE 7.1 at the moment? > > > Howdy Jeremy, > > I don't use Linux, but Windoze based 7.1i has stablized enough that > chances are slim you'd run into any problems with it - and even if you > do, they are likely fixed in SP3 (due out in the next week or so). Thanks Marc, Looks like I'll upgrade after all :) JeremyArticle: 86034
"Peter Alfke" <peter@xilinx.com> wrote in news:1119307329.734267.74850 @f14g2000cwb.googlegroups.com: > This is the case of very cautious worst-case specifications. > > If the CMOS output is truly complementary (most of them are nowadays), > and there is no pulldown load, Voh will in reality be exactly = Vcc > (although the specification will probably mention a lower value.) > So Voh min = 3.0 V or slightly higher. > > A True CMOS input has an input threshold around 40 to 60% of Vcc ( or > 30 to 70%), and Vcc might be as high as 5.5 V So the input threshold > might be well above 3 V. > Now you see that this interface does not work "worst case" > > If the CMOS input is called TTL (just an indication of input threshold, > no other realtion to the bipolar TTL technology), then the input > threshold is artificially made much lower, around 1.5 V, and the > interface works perfectly. > Clear? > Peter Alfke, Xilinx Applications > Hi, I think the important distinction to make is the distinction between TTL signaling levels and TTL parts. I see many people (including myself) who use "TTL" and "seventy four hundred series devices" interchangably. > I don't see why there would be any problem driving a CMOS input provided > that the CMOS input will accept 3.3V signals as high. There certainly isn't > going to be any significant current flow into the CMOS gate. What you cite is exactly the issue. If a 5.0v CMOS device has a Vih,min that is 90% of the 5.0v supply rail, your programmable logic device output isn't going to satisfy the requirement -- because it will only be able to pull up to 3.3v. Counterpoint, consider a 5.0v TTL device, where the Vih,min might be around 2.4 volts. Your programmable logic device will be able to pull up higher than what is required, so it will work properly. At the end of the day, the best advice I can offer you is to read the datasheets of both parts and carefully consider the signaling levels and thresholds, and don't forget to design for some noise margin. Eric Thanks Peter & Eric, This explanation makes perfect sense to me now. I understand that my CMOS inputs need to interpret a nominal 3.3 V level reliably as a logic high signal level. This is usually the case with the devices I will be interfacing with. I think Altera could have clearly stated this in their manuals or web site as well (perhaps Xilinx does). -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 86035
Hi All, Thanks for your responses. Marc and Jim, your responses were very interesting. I learned a lot going through those searches. Rene, I did not say that I will base my PhD topic on this discussion. My advisor is helping me decide a topic in a major way. Through this side discussion, I want to know the industry opinion and opinions of people who use FPGAs in their designs. Regards, -LoveArticle: 86036
Hi all, I'm having a hell of a time trying to use a Xilinx IPCore (DDS). I can generate the CORE, it seems I can instantiate it (not sure -- verilog/fpga newbie). Everything seems to be ok, but I get no output -- like the output pins are not connected to module's sin/cos output... Can anyone provide a sample (small one) code showing how to really instantiate a CORE into a Verilog projet ? Thank you, Angilberto.Article: 86037
Greetings, I have a situation where Post Translate timing is significantly different from behavioral/RTL simulation. I am not not speaking of simple delays, the outputs/data are different than what they should be. What is interesting is that the design works on the FPGA board. I implemented a serial port in loopback mode in Xilinx, if I type a character on Hyperterm I get the same returned from the FPGA. I have set timing constraints but to no effect. YZArticle: 86038
Steve, Thanks for the update. This is good news! What about the XC3S1000s? I thought I saw those on the website yesterday but now they are gone. Were the bigger parts on the webstore before the availability problems? Ricky (big XC3S1000 user).Article: 86039
Nemesis wrote: > Hi all, > I implemented a fir filter using the MacFir5.0 core from Xilinx. > The filter 2 coefficient sets of 33 taps, with 14 bit > coefficients and data. > > I was looking at the resouces utilization and I found a strange data, > the filter requires 33 multipliers and 33 block ram. > > I can't understand why it requires so much block rams! Each block ram > should store 1k x 18bits! > If I set the core to use the distributed ram for coefficients or > for data this number doesn't change, of course it goes to zero when > I set the core to use the distributed ram for both coefficients and > data. > > I read on the User Guide that multipliers and block ram shares routing > resources, > is that the cause of the great number of bram used? > AFAIK, the core will pack together a MULT18x18 and a BRAM with a connection between the two to maximize speed. The coefficients end up getting replicated in each BRAM. If you want to reduce the area, check to see if your input data rate is low compared to the clock rate. If so, you can tell the core gen about this and it will re-use the same multiplier for multiple taps. If you can't do this, consider using DA filters. -JimArticle: 86040
Does anybody have filter design experience with FPGA? I would like to know a general picture with recent FPGA technologies like XtremeDSP and others. I am also curious about the limitation of FPGA design on filter design, like the maximum center frequency and bandwidth of the filters that can be implemented with FPGA. Could anybody let me know if I am able to simulate a SAW (surface acoustic wave ) filter with 185MHz center frequency and 4MHz double-side bandwidth, and Max. 20dB insertion loss inside of a FPGA? Any information will be highly appreciated. Thanks in advance. JohnsonArticle: 86041
amko wrote: > ISE Webpack is definitly better choice than Altera Web Edition. Web > Edition does not generate image files (pof. and sof.). In additional > ISE Webpcack has minimal limitations and only big disadvantage is core > generator which is not included in the Webpack. It means you can not > use Xilinx FIFO, DP RAM,... but anywhere you have PLL (DCM)... > Synthisiser XST is also very good and in most case you dont need it > Leonardo or Synplify... > Free Simulator tool (Xilinx Modelsim ) is also avaiable with ISE > Webpack.... > > In the other words you can do it much more with ISE Webpack... > > Regards , > > Amir > Perhaps you've been using a version of Quartus Web Edition from long before I started looking at FPGAs... QII web edition can do pretty much everything the "full" edition can do except really big designs - if you are looking for medium or large Stratix I/II chips, logic region locking, RTL viewing, and a few other big design features, you'll need the full pack. Otherwise, the web edition will do it all. I also get the impression that steadily more features get moved from the "full" edition down to the web edition - it's not long ago that physical synthesis for register retiming was full edition only. About the only thing missing from the web edition is a Linux version - I expect that will come soon, though, now that there is a free Linux version of the Xilinx tools...Article: 86042
Jim George wrote: [MAC_FIR and BRAM] > AFAIK, the core will pack together a MULT18x18 and a BRAM with a > connection between the two to maximize speed. The coefficients end up > getting replicated in each BRAM. Ah! OK, so this is the cause. > If you want to reduce the area, check > to see if your input data rate is low compared to the clock rate. If so, > you can tell the core gen about this and it will re-use the same > multiplier for multiple taps. This is not my situatuon. I have a data rate of 64MHz and I need to decimateit to 32MHz, when I syntesize the core with sample_rate=clock=64MHz, I get a maximum clock frequency of 180MHz (V2pro50-6), but if I synthesize the core with sample_rate=64MHz and clock=128MHz then XST reports the maximum clock to be 126MHz. > If you can't do this, consider using DA filters. I think I'll try them, now I just checked "use distributed ram" for both coefficients and data, and spending some extra slices I got 0 BRAM used. But I have one last question, are these BRAM really free to use?Article: 86043
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<3hoeseFi5l05U1@individual.net>... > "Patrick" <patrick.melet@dmradiocom.fr> schrieb im Newsbeitrag > news:54b3002.0506200605.3dadb7cc@posting.google.com... > > > Perhaps it's be better if the RESET is after the 3.3V power-on ? > > Use a voltage monitor that releases the reset after ALL voltages are valid. > > Regards > Falk We add a RC circuit beetween the reset from the Stratix circuit to the MAX circuit. So the MAX is resetted after the 3.3V is ON and sometimes the program from the flash don't boot !!! This is a big problem for our system which uilizes 3 boards... My Support from Altera don't explain me what's happen... So is there anybody who have this problem with these EP1S25 cards and is there a solution ?Article: 86044
lovesinghal wrote: > Rene, I did not say that I will base my PhD topic on this discussion. > My advisor is helping me decide a topic in a major way. Through this > side discussion, I want to know the industry opinion and opinions of > people who use FPGAs in their designs. Ok, you couldn't have known. The FPGAs are great to work with, enable a lot of developments and save a lot of work. Whether they further evolve or not doesn't change much as what is here already is plenty. The development is a bit too fast though. When you do a new design with brand new chips, then they tend to be outdated the next time you assemble a batch. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 86045
On 20 Jun 2005 13:37:10 -0700, "xilinx_user" <barrinst@ix.netcom.com> wrote: >Yes. I think we owe a big round of thanks to Peter Alfke and his crew >for making this happen. > >Mike Harrison wrote: >> Further to recent discussiuons here, I Just noticed That S3s have appeared in the Xilinx web store. >> A few are even shown as in stock.... Hmmm now everything is shown in stock but the parts bigger then 400 have disappeared - I'm sure they were there at the weekend when I first noticed.....Article: 86046
On Mon, 20 Jun 2005 22:07:52 GMT, Al Clark <dsp@danvillesignal.com> wrote: >I am using a MAX II part in a new design with 3.3V supplies. > >I understand why the inputs might not be 5 volt tolerant. > >Altera states that the outputs are not 5 volt tolerant when driving CMOS >but are OK for TTL. Since TTL is essentially dead, I'm not sure this is of >any real benefit, however this is not my main concern. TTL is dead but HC and AC logic is available with TTL input levels (HCT/ACT), which you will need to use if driving from 3.3v logic.Article: 86047
Hi, I have generated two SCFIFOs with Altera Quartus (4.2 SP1) MegaWizardManager. One optimized for best speed (that is Quartus is said to add output registers) and one for smallest area (no output registers). After compiling the two FIFOs I have a look at their structure in the RTLViewer. And yet I cannot see any output registers for the "best speed" optimized one. I can go down the hierachy until I see the RAM block but there are no additional flipflops between the RAM block and the outputs of the SCFIFO. Why ? Rgds Andr=E9Article: 86048
ALuPin@web.de wrote:
> And yet I cannot see any output registers for the "best speed"
> optimized one. I can go down the hierachy until I see the
> RAM block but there are no additional flipflops between the
> RAM block and the outputs of the SCFIFO.
Speed/Area constraints are just hints.
If you know what you want, skip the wizard
and write your own code.
-- Mike Treseler
Article: 86049
yaseenzaidi@NETZERO.com wrote:
> I have a situation where Post Translate timing is significantly
> different from behavioral/RTL simulation. I am not not speaking of
> simple delays, the outputs/data are different than what they should be.
Gate level sims are more complex than functional.
I expect your error is here.
However, if static timing is ok and the thing works
I wouldn't bother performing or debuging a gate sim.
-- Mike Treseler
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