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Hello all,
I finally fixed the problem and the FAT File system on Compact Flash
works fine in my configuration.
Here's some treatments that I did.
1. Make the CF have only one partition which occupies the whole space.
2. Format it using "mkdosfs" (you can get http://www.mager.org/mkdosfs/)
Also, refer to Answer Database 14456.
3. When you open the file, use the full path.
(i.e. sysace_fopen("a:\\filename.txt", "r"); )
I hope this will help the people who will have the same struggling with
me in the future.
Also, you can get the working example in XUP Demonstration and Reference
Designs page. (http://www.xilinx.com/univ/xupv2p_demo_ref_designs.html)
Check out Slide Show example.
Sewook.
p.s. Paul Calvert, thank you very much.
Sewook Wee wrote:
> Hello,
>
> I am trying to test file system on Compact Flash.
>
> Now, my configuration is following.
>
> 1. ML310 Board
> 2. Core : PowerPC (uni-processor system)
> 3. Boot : Using BRAM inside
> 4. OS : Standalone
> 5. Library added : XilFatFs
>
> The hw platform has been compiled and looks working.
> Also I have no problem to compile the code.
> Simply, the problem is that I can not open the file with "sysace_fopen"
>
> Is there anyone who has an example design that I can start with?
> Thank you in advance.
>
> Sewook Wee
Article: 86276So basically I would set a flag/signal in the 10 Khz clock process. Wait for the flag to be set in the 1 Mhz process, then count n clocks then put data out on the serial port? Thanks, JT "Vladislav Muravin" <muravinv@advantech.ca> wrote in message news:UOyue.74572$Kk4.905480@news20.bellglobal.com... > Well, if you detect the rising or falling edge of the clock, you can count > the number of clocks corresponding to the desired delay. > once you reach this coun, you shift the data using 1 MHz clock... This is > UART-like data shifting-out i think. > If there is no problem with setup/hold time in the receiving device, this > should be alright. > > Hope this helps. > > Vladislav > > <JT> wrote in message news:ee8f32c.-1@webx.sUN8CHnE... >>I am generating a slow serial data stream in response to a input clock. I >>need to delay n uSec's after detecting the clock edge before I output the >>data. The input clock is currently running at 10 Khz. I was going to run >>another process at 1 Mhz but don't know the best way to wait for a delay >>count in the slower 10 Khz process. >> >> Any suggestions? >> >> Thanks > >Article: 86277
what is the width of your polynomial. Is it -7 to +4.... "Kris Neot" <Kris.Neot@hotmail.com> wrote in message news:42bb65e4@news.starhub.net.sg... > My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one byte > each clock period. What are the equations to inplement this data > scrambler? > > > Thanks. > > >Article: 86278
shridhar@mistralsoftware.com wrote: > Hi, > > we are reading an ADC o/p through FPGA. To remove the DC Offset present > in the ADC input we have a DAC which can remove this DC offset using a > subtractor before the actual analog input (with added DC offset) goes > to ADC. > > Now I want my FPGA to calculate the DC offset from ADC outputs and then > feed this value to DAC input which in turn cancel the DC offset using > subtrator. > > can anybody suggest me how can i implement this in FPGA? I just gone > through net and realized that i can use a subtractor and a MAC. The ADC > output will go to this Subtractor which has the final output of MAC as > other input. the subtractor output will be multiplied with some small > value K (??) and then an accumulator. The final output of accumulator > can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the > DC offset? > > this is what i understood. can somebody through some light? > > suggestions are welcome. > You can avoid potential stability issues (can happen with IIR smoothing filters and due to pipeline delays in converters) if you can ensure your ADC inputs are grounded briefly (at startup, or by issuing a "calibrate" command) and measuring the offset. This can be fed back until the offset is below 1 bit. This of course only works if it's the ADC offset you wish to cancel, and not the offset present in the input signal itself -Jim if you are blr based, I used to work in the offices just above yours...Article: 86279
Vladislav Muravin wrote: > One more thing to add I am using WinXP > > Vladislav > > > "Vladislav Muravin" <muravinv@advantech.ca> wrote in message > news:90zue.74585$Kk4.909792@news20.bellglobal.com... > >>Hello all, >> >>I am having a strange thing happening. >>This was not urgent, so i kinda did not post it previously... >> >>I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4 >> >>(one) When running the entire ISE flow, everything is smooth, the PROM >>files are generated >>using two devices 1804v, one 100% full and another 65% full. FPGA is fully >>functional and everything is working. >> >>(two) When running the same using command line, i get that PROM files are >>generated >>using two devices 1804v, one 100% full and another 62% full. When >>programming FPGA with this configuration, >>nothing is working. the LEDs which blink once a second per different clock >>domains are "dead"... >> >>I have noticed this with both ISE 6.3 and 7.1 >> >>The question is what the hell is happening here? >> >>Thank you all for your time and attention >> >>Sincerely, >>Vladislav >> > > > Startup clock selection? .UCF file not included in command line version? (happened to me, resulted in a smoked board :( )Article: 86280
hi havard, thanks for the tips!!Article: 86281
I am just giving a general hint, should be applicable to your case also after some changes What you do is to tap the x7 and x4 bit of polynomial and XOR it with the bit 0 of incoming data stream. The xored value is your output bit 0. Then DEPENDING upon the protocol, you may either push in the output bit to msb position of polynomail and shift all other bits of polynomial either right or left depending upon your direction convention. Repeat the above process each input bit.... "Kris Neot" <Kris.Neot@hotmail.com> wrote in message news:42bba2e8@news.starhub.net.sg... > Sorry typo, should be S(x) = x(-7) + x(-4) + 1. > What is the method to do conversion? > > > "newsgroup" <skeffect@gmail.com> wrote in message > news:d9g6mk$9j$1@bunyip2.cc.uq.edu.au... >> what is the width of your polynomial. Is it -7 to +4.... >> >> "Kris Neot" <Kris.Neot@hotmail.com> wrote in message >> news:42bb65e4@news.starhub.net.sg... >> > My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one >> > byte >> > each clock period. What are the equations to inplement this data >> > scrambler? >> > >> > >> > Thanks. >> > >> > >> > >> >> > >Article: 86282
"Eric Smith" <eric@brouhaha.com> schrieb im Newsbeitrag news:qhaclgn1s6.fsf@ruckus.brouhaha.com... > Can anyone in the know comment on what the likely order of > availability of Spartan-3e parts (in sub-1000 piece quantities, > not zillions) will be? I'm hoping that the 3S500E in the > chipscale BGA will be one of the first; I've been waiting for > a high-density FPGA in a tiny package. It's a shame that none > of the Spartan-3 parts larger than the 3S50 are available in > that package. > > Thanks, > Eric > Antti's forecast 1) NO S3E before September 2005 2) NO chipscale BGA before Q1 2006 lets hope I am wrong :)Article: 86283
Sorry typo, should be S(x) = x(-7) + x(-4) + 1. What is the method to do conversion? "newsgroup" <skeffect@gmail.com> wrote in message news:d9g6mk$9j$1@bunyip2.cc.uq.edu.au... > what is the width of your polynomial. Is it -7 to +4.... > > "Kris Neot" <Kris.Neot@hotmail.com> wrote in message > news:42bb65e4@news.starhub.net.sg... > > My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one byte > > each clock period. What are the equations to inplement this data > > scrambler? > > > > > > Thanks. > > > > > > > >Article: 86284
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1119582877.274140.121020@f14g2000cwb.googlegroups.com... > What's so great about a 30-year old CPU ? > Peter Alfke > some things just are great the best and fastest computer I ever had was selfmade made on protoboard -Z80 4MHz -64k dram 6164 (from russian military fabs, nice golden ceramic) -2716 boot loader, self written -WD2793 -8251 uart -5 inch floppy this thing booted CP/M from COLD start during 2 rotations of the floppy disk I used specially pathced version of M80 to write assembly for COP processor on that machine. I could potentially use the same machine for PLD development even today There is virtually no modern PC that boots as fast today - the technology is kind advanceing but PC's are getting only slower as of the user point of view. There are uncounted number of Z80 based home computer designs AnttiArticle: 86285
hi jesse, If I gate the CPU clock it won't be able to execute any instructions. So it cannot access any memory or peripheral also. I didn't understand why it should go to sleep routine. Can you elaborate. Thanks sunnyArticle: 86286
hi david, I found that altera provides some sort of clock control block which may be useful for me. thanksArticle: 86287
Antti, I got ours promised (but not 100% confirmed) for end of June (3S500E, CP132). Let's hope YOU are wrong... ;-) Thomas (sitting here sweating, maybe it's just the heat in Austria, maybe it's also the fear of not getting the parts in time...) > Antti's forecast > > 1) NO S3E before September 2005 > 2) NO chipscale BGA before Q1 2006 > > lets hope I am wrong :) "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:d9g8if$p07$02$1@news.t-online.com... > "Eric Smith" <eric@brouhaha.com> schrieb im Newsbeitrag > news:qhaclgn1s6.fsf@ruckus.brouhaha.com... >> Can anyone in the know comment on what the likely order of >> availability of Spartan-3e parts (in sub-1000 piece quantities, >> not zillions) will be? I'm hoping that the 3S500E in the >> chipscale BGA will be one of the first; I've been waiting for >> a high-density FPGA in a tiny package. It's a shame that none >> of the Spartan-3 parts larger than the 3S50 are available in >> that package. >> >> Thanks, >> Eric >> > > Antti's forecast > > 1) NO S3E before September 2005 > 2) NO chipscale BGA before Q1 2006 > > lets hope I am wrong :) > > > > >Article: 86288
yeah, if one has patience, one can derive each byte one by one. I thought there must be some shortcut to this tideous process. "newsgroup" <skeffect@gmail.com> wrote in message news:d9g8ca$qkp$1@bunyip2.cc.uq.edu.au... > I am just giving a general hint, should be applicable to your case also > after some changes > > What you do is to tap the x7 and x4 bit of polynomial and XOR it with the > bit 0 of incoming data stream. The xored value is your output bit 0. Then > DEPENDING upon the protocol, you may either push in the output bit to msb > position of polynomail and shift all other bits of polynomial either right > or left depending upon your direction convention. > > Repeat the above process each input bit.... > > > "Kris Neot" <Kris.Neot@hotmail.com> wrote in message > news:42bba2e8@news.starhub.net.sg... > > Sorry typo, should be S(x) = x(-7) + x(-4) + 1. > > What is the method to do conversion? > > > > > > "newsgroup" <skeffect@gmail.com> wrote in message > > news:d9g6mk$9j$1@bunyip2.cc.uq.edu.au... > >> what is the width of your polynomial. Is it -7 to +4.... > >> > >> "Kris Neot" <Kris.Neot@hotmail.com> wrote in message > >> news:42bb65e4@news.starhub.net.sg... > >> > My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one > >> > byte > >> > each clock period. What are the equations to inplement this data > >> > scrambler? > >> > > >> > > >> > Thanks. > >> > > >> > > >> > > >> > >> > > > > > >Article: 86289
Wau! I like to be wrong on some occasions :) Antti "Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:42bbafca$0$13522$91cee783@newsreader01.highway.telekom.at... > Antti, > > I got ours promised (but not 100% confirmed) for end of June (3S500E, > CP132). Let's hope YOU are wrong... ;-) > > Thomas > (sitting here sweating, maybe it's just the heat in Austria, maybe it's also > the fear of not getting the parts in time...) > > > Antti's forecast > > > > 1) NO S3E before September 2005 > > 2) NO chipscale BGA before Q1 2006 > > > > lets hope I am wrong :) > > "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag > news:d9g8if$p07$02$1@news.t-online.com... > > "Eric Smith" <eric@brouhaha.com> schrieb im Newsbeitrag > > news:qhaclgn1s6.fsf@ruckus.brouhaha.com... > >> Can anyone in the know comment on what the likely order of > >> availability of Spartan-3e parts (in sub-1000 piece quantities, > >> not zillions) will be? I'm hoping that the 3S500E in the > >> chipscale BGA will be one of the first; I've been waiting for > >> a high-density FPGA in a tiny package. It's a shame that none > >> of the Spartan-3 parts larger than the 3S50 are available in > >> that package. > >> > >> Thanks, > >> Eric > >> > > > > Antti's forecast > > > > 1) NO S3E before September 2005 > > 2) NO chipscale BGA before Q1 2006 > > > > lets hope I am wrong :) > > > > > > > > > > > >Article: 86290
NuHorizons has a decent online store selling most varieties of Xilinx FPGAs/CPLDs. Check them out www.nuhorizons.com --Neeraj Jim Granville wrote: > Austin Lesea wrote: > > All, > > > > Face it, Peter and I both are absolute true believers in on-line > > shopping. And we believe that buying FPGAs should be no more painful > > than buying a book at Amazon.com. > > > > Sure, if you want 25 of them, or if you need support and services, you > > may not want to buy online, but rather through your local and helpful > > distributor who will actually send the FAE to you to help (if needed). > <snip> > > You might sell more than you think. > One common issue with Distis, is many don't like to break SPQ's > - so that places a quantize effect on availability. > It means there will be both pilot run, and also run-rounding needs. > > Programmable logic is stocked much more poorly than generic > microcontrollers, simply because the range changes so rapidly. > > > TIP for Xilinx: Put the SPQ on the webstore (somewhere), so users can > see at a glance if contacting the Disti is likely to be helpfull, > or a waste of time... > > I just looked at my XC2C32 data sheet, plenty of order codes (19!), > but not a single SPQ!... > > -jgArticle: 86291
Kris, definitely yo can do the whole process in one go. For that either you have to write a simple program which tells you the bit combinations or since in your case, data is just 8 bits, so you can manually derive the equation But I guess, the synthesis tool will be doing the same thing for you, if you just write everything in loop, can't guarantee but it should do so..... "Kris Neot" <Kris.Neot@hotmail.com> wrote in message news:42bbaf85$1@news.starhub.net.sg... > yeah, if one has patience, one can derive each byte one by one. > I thought there must be some shortcut to this tideous process. > > > > "newsgroup" <skeffect@gmail.com> wrote in message > news:d9g8ca$qkp$1@bunyip2.cc.uq.edu.au... >> I am just giving a general hint, should be applicable to your case also >> after some changes >> >> What you do is to tap the x7 and x4 bit of polynomial and XOR it with the >> bit 0 of incoming data stream. The xored value is your output bit 0. Then >> DEPENDING upon the protocol, you may either push in the output bit to msb >> position of polynomail and shift all other bits of polynomial either >> right >> or left depending upon your direction convention. >> >> Repeat the above process each input bit.... >> >> >> "Kris Neot" <Kris.Neot@hotmail.com> wrote in message >> news:42bba2e8@news.starhub.net.sg... >> > Sorry typo, should be S(x) = x(-7) + x(-4) + 1. >> > What is the method to do conversion? >> > >> > >> > "newsgroup" <skeffect@gmail.com> wrote in message >> > news:d9g6mk$9j$1@bunyip2.cc.uq.edu.au... >> >> what is the width of your polynomial. Is it -7 to +4.... >> >> >> >> "Kris Neot" <Kris.Neot@hotmail.com> wrote in message >> >> news:42bb65e4@news.starhub.net.sg... >> >> > My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one >> >> > byte >> >> > each clock period. What are the equations to inplement this data >> >> > scrambler? >> >> > >> >> > >> >> > Thanks. >> >> > >> >> > >> >> > >> >> >> >> >> > >> > >> >> > >Article: 86292
Peter Alfke <peter@xilinx.com> wrote: > The situation will get better, much better. This is work in progress, > so I do not want to create confusion or overly optimistic (early) > expectations. But we are (painfully) aware that something must be done, > and it will. Witness the improvements earlier this week... > Peter Alfke Configuration devices in the webshop would be appreciated! -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 86293
"info_" <"info_"@\\nospam_no_underscore_alse-fr.com> wrote in message news:NPEue.4593$hV3.1461@nntpserver.swip.net... > bijoy wrote: > >> Hi >> >> Any body used FFT core given by coregenerator in Xilinx ? >> >> Does it work as they said in their data sheet.. >> >> regards bijoy > > It works very well, it is efficient, and has lots of nice features. except that it is quite inefficient when it comes to calculation time efficiency > As for any macro, I would recommend making some (RTL) simulations > to ascertain how it must be initialized and used. > > > Bert CuzeauArticle: 86294
Hi I have a small question. I have a PLB Peripheral with "Software Addressable Registers". Say the baseaddress of my peripheral is 0x90000000 . I have five 64bit registers in my logic. So, the addresses of each of the registers would be baseaddress plus 0x00, 0x08, 0x10, 0x18 and 0x20 respectively. What happens when I try to read, or what would be the output when I read the memory addresses in between. I always believed that the "Bus2IP_WrCE"signal will assume only "10000", "01000", "00100", "00010" and "00001" and the corresponding register values would be read out from the corresponding registers. Is it possible that I can read out the values "byte-shifted"?Article: 86295
On a sunny day (Fri, 24 Jun 2005 09:35:03 +0000 (UTC)) it happened Uwe Bonnes
<bon@elektron.ikp.physik.tu-darmstadt.de> wrote in
<d9gk47$kqa$1@lnx107.hrz.tu-darmstadt.de>:
>Peter Alfke <peter@xilinx.com> wrote:
>> The situation will get better, much better. This is work in progress,
>> so I do not want to create confusion or overly optimistic (early)
>> expectations. But we are (painfully) aware that something must be done,
>> and it will. Witness the improvements earlier this week...
>> Peter Alfke
>
>Configuration devices in the webshop would be appreciated!
I would rather have these in the FPGA itself, as flash.
1) better security
2) saves on chip costs
3) saves on PCB cost
4) saves work on power up stuff
5) saves time
6) saves shipping cost
7) saves on PCB space
8) and if you use a 739 pin connector like AMD processors, then you can just
send customers an upgrade, they send old one back for re-programming.
9) more reliable
10) faster power up
..
99999) less power?
beep
Article: 86296newsgroup wrote: > Kris, > > definitely yo can do the whole process in one go. > For that either you have to write a simple program which tells you the bit > combinations or > since in your case, data is just 8 bits, so you can manually derive the > equation > > But I guess, the synthesis tool will be doing the same thing for you, if you > just write everything in loop, can't guarantee but it should do so..... Yes, it works. I have made scramblers that way (in VHDL). It should also be possible in Verilog, assuming your tool implements the 2001 version of the language. Regards, AllanArticle: 86297
Very creative! You should work for Actel / LatticeXP-marketing ;-) I would reduce your list mainly to better security. E.g. it is simpler to socket and ship a $1 8pin SPI-flash than the $$$$ 1000pin FPGA... But upgrade via RS-232 or something, as we do, is even better... Thomas "Jan Panteltje" <pNaonStpealmtje@yahoo.com> schrieb im Newsbeitrag news:1119611642.a327c9d5e28eb26f262ca1e83907e569@teranews... > On a sunny day (Fri, 24 Jun 2005 09:35:03 +0000 (UTC)) it happened Uwe > Bonnes > <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in > <d9gk47$kqa$1@lnx107.hrz.tu-darmstadt.de>: > >>Configuration devices in the webshop would be appreciated! > I would rather have these in the FPGA itself, as flash. > 1) better security > 2) saves on chip costs > 3) saves on PCB cost > 4) saves work on power up stuff > 5) saves time > 6) saves shipping cost > 7) saves on PCB space > 8) and if you use a 739 pin connector like AMD processors, then you can > just > send customers an upgrade, they send old one back for re-programming. > 9) more reliable > 10) faster power up > .. > 99999) less power? > beepArticle: 86298
Peter Alfke wrote: > Well. European geography was never a US forte. Confusing Sweden with > Switzerland is much worse than mixing up Finland and Sweden. Hell, for > a few hundred years, before Napoleon, those two were actually together. > In Europe, I have asked people whether they know the difference between > Michigan and Minnesota, and I got a blank stare... > Peter Alfke Sorry to push this thread further off topic, but... a) Michigan and Minnesota, while as large as many European countries are not countries, while Finland and Sweden are. b) You'd get a lot of blank stares in the US, too. c) At least you didn't confuse Sweden and Norway, you could be shot for that ;-)Article: 86299
Quick question: Anyone know who set the LVTTL spec if there is such a defined spec. As in, IEEE, ANSI, TIA, EIA, etc... Thanks, Kevin
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Compare FPGA features and resources
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