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"Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message
news:1119842683.022247.67660@o13g2000cwo.googlegroups.com...
> Hi,
> I am implementing a particular voice compression algorithm in a Spartan
> 3 FPGA and am directly instantiating Xilinx primatives to get the best
> (and most reliable) performance, I hope. The spartan 3 datasheet
> provides a "Figure 6: Simplified Diagram of the Left-Hand SLICEM". This
> info is good but I'm wanting more detail than is provided in this
> diagram. The datasheet hints there is more "Options to invert signal
> polarity .... are not shown". Is there any documentation that gives an
> even more detailed view of the Spartan 3 Slice?
> (I've googled without success so far.)
>
> I suspect FPGA Editor will tell me more but I don't have access to that
> yet. Also I see the ISE 7.1i Timing Analyser pops up some nice diagrams
> of the slice when one clicks on some of the hyperlinks in the timing
> analysis report. These diagrams show invertor options on some of the
> slice input signals but I can't help wondering if there are other
> options?
>
> Regards
> Andrew
In general, I'd recommend the Spartan-3E data sheet for the CLB description.
Both Spartan-3 and Spartan-3E share the same CLB logic but the Spartan-3E
data sheet has additional material, starting on PDF page 20.
http://www.xilinx.com/bvdocs/publications/ds312.pdf [1.7M]
Attached is the diagram for a SLICEM slice from ISE 7.1i, FPGA Editor. The
SLICEM slices include the option for 32 bits of distributed RAM or 32 shift
register bits. A SLICEL slice is similar, but it is Logic only, without
Memory. From the diagram, you can see the 2:1 multiplexers on some of the
slice control inputs, namely the clock (CLK), clock enable (CE), and
set/reset (SR) inputs.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.
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Article: 86426Hi Peter, Thanks for your comments, I realise the LUT can implement any boolean function of 4 variables (or SRL, 16x1 RAM, etc). But say the F-LUT and FFX Flop are both used (and the F-LUT output is connected to the D input of FFX). If the logic cell includes an invertor on the BX input, don't I effectively get this invertor for free and I can use it on the BX to BXOUT path? This invertor is additional logic than provided by the LUT. Also, if invertors present on the FAND inputs then I get a 2input function generator for free? (obviously there are restrictions, F1, F2 must be the inputs, can't use the carry chain for something else - the output would come out XB.) Or am I trying to push the Spartan 3 logic cell too far? In case anyone is interested, what I was trying to do is find the floating point exponent(4 bits) for a 14bit unsigned number. I havn't spent a lot of time on it, but the best I have come up with so far is firstly a priority encoder to find the location of the MSB. The priority encoder is implemented with a "carry-propagate-kill" using the MUXCY and 2 LUTS per bit. (one LUT to control the MUXCY carry propagation and 1 LUT to generate the priority encoded output). I then use a further 8 LUTS to encode the 14 bit priority encoded value to a binary exponent(4 bits - 2 LUTS per bit). I feel like it would be nice to somehow make use of the FAND or XORF or F5MUX to reduce the amount of LUTS required but can't quite see how yet..... Regards Andrew Peter Alfke wrote: > If you use a LUT as a 16-bit ROM (its normal application), then there > is no benefit whatsoever in the ability to invert any or all of the 4 > inputs, or the output. Anything you might do with inverters can be done > by just redefining the 16 LUT bits. > Clock enable Write Enable and Clock polarity may sometimes "need" > inverters, but even that is rare. > The LUT is a very versatile tool; that's why we are so loyal to it... > Peter AlfkeArticle: 86427
To run two seperate standalone programs on both PPCs simultaneously follow these steps. I assume that both processors are on the same PLB and share BRAM (e.g. 64KB) at the top of the address space. 1. Enable bootloop for one of the processors. This will add a small program to the BRAM at address -4 (reset vector) that loops to itself. Both processors will execute this program once they come out of reset. 2. Add a standalone program to the software projects and associate it to the first processor. In my example I run this program from address [-64K, -32K[, i.e. give it a start address of 0xffff0010. Now, map the .boot and .boot0 sections to the beginning of that area by adding -Wl,--section-start,.boot=0xffff0000 -Wl,--section-start,.boot0=0xffff0004 to "Additional Compiler Flags". Alternatively, you can write your own linker script (see documentation) to achieve the same result 3. Repeat the step above for the second processor but change all address to map into the [-32k, -4[ address range. 4. Compile your software projects. 5. Use XMD to download both programs. You can start two XMDs and use one to connect to the first processor with connect ppc hw and the other one to the second processor with connect ppc hw -debugdevice cpunr 2 Alternatively, you can use one XMD and work from there. I hope this helps. - Peter jaggu wrote: > thanks Peter.. > > how can I run seperate standalone programs on both PPC's simultaneously, especially how can I download onto target. I couldnt do "update bitstream" as it says elf file associated with PPC_1 should be downloaded thorugh jtag..via gdb. only 1 program which is asscocited with ppc_0 am able to update with bitsream. > > thank you for your time and consideration, > > regards JagguArticle: 86428
Marc Reinig wrote: > Michael, > >> I can't imagine how this core >> can implement CRC error correction > > I doubt that it does or even tries to do CRC error correction. USB > requires devices do CRC generation and checking. Devices do no > correcting. They just flags errors if they occur. > > Marco You are both correct. The item Michael is referring to is that once a packet has been take from the FIFO it cannot be resent if the transmission was not successful. Michaels description os "CRC correction" was misleading, this is a generic mechanism for retransmitting any packet that has not been ack'ed, regardless if it was due to CRC error, time out, or the host being plain out busy. Nevertheless the USB 1.1 IP has been successfully implemented and used in many, many different projects. Only error recovery is now as smooth as it could be ... rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis ****** Certified USB 2.0 HS OTG and HS Device IP Cores ******Article: 86429
Hi, "Waiting for clock" means that there is no activity on the clock signal that you have specified. I don't quite understand why you reset the device. HavardArticle: 86430
I'm curious. Why do you need an FPGA with bitstream encryption?Article: 86431
Michael Dreschmann wrote: >>I doubt that it does or even tries to do CRC error correction. USB >>requires devices do CRC generation and checking. Devices do no >>correcting. They just flags errors if they occur. > > With CRC error correction I mean the whole thing, retransmit or > discard received data with bad CRC. The 1.1 core uses external FIFOs > for every endpoint. For an OUT endpoint you have the (output) signals > data_out, write_strobe and (input) signal buffer_full in the entity of > the core. Because I can't find any buffer memory inside the core that > can hold 64 bytes (the max packed size I used) I assume that it sends > every received byte from the USB directly to the external endpoint > FIFO. This could be easily fixed by adding one control signals to the FIFOs: commit This signal commits current rd pointer for OUT endpoints to the master rd pointer. commit would be asserted when one of the following conditions is true after transmission: 1) we have received an ACK; 2) it's an asynchronous endpoint; On the receive side (IN endpoints), it would be a bit trickier. Two cases can occur here: 1) We have detected a CRC error and never ack'ed a packet, in which case the host will resend - everything is cool for this case. 2) If the host never receives the ACk (or the ACK is corrupted) it will resend the packet. We should be discarding packets with the wrong DATA id, but I don't think that is implemented either. Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis ****** Certified USB 2.0 HS OTG and HS Device IP Cores ****** > But what if a CRC error is detected at the end? There is no way the > core can delete the last packed he just send to the FIFO. So, if he > doesn't send a handshake in reply to this bad packed he will geht it a > second time and will probably write it to the FIFO again. If he send's > an ACK then you still have a bad packed in your FIFO. > The core has an CRC Error output signal (for all endpoints together) > but I don't see how I can use it to avoid such problems... > > MichaelArticle: 86432
Piotr Wyderski wrote: > Hello, > > I would like to build a 1GBit/s data encryptor/decryptor using > an FPGA chip, but I have a big problem with an appropriate > chip. It should contain about 3000LE, 70 IO pins and at least > 12 dual-port RAM blocks (I need two read ports per block) configurable > as 512x8 banks. Additionally, it should be Flash-based or SRAM > -based with encrypted bitstream. And must be cheap. Here are the > options I know of: > > 1. Altera Cyclone 1C3-8. It is perfectly suited for my needs, > and is very cheap. There is extremely good design software > available. But it can't be used: it's totally unsecure. > > 2. Actel ProASIC+: flash-based and cheap, but their > memory blocks are not big enough and have only > one read port. Terribly bad software quality. > > 3. Actel ProASIC3: good, moderately expensive but not yet available. > > 4. Lattice XP: unknown price, unknown availability, technically suitable, > I've heard many bad opinions about Lattice, but personally I have no > experience with their chips. > > 5. Xilinx Virtex4: too powerful and thus probably much too expensive, > good availability, very good support [:-)], software quality unknown, > but probably comparable to Quartus. > > Could you please write something about remaining options? > > Best regards > Piotr Wyderski What cypher are you going to use ? We are getting about 20 Gbps in a Virtex 2 3000, for 1Gbps you can get away in a Spartan 3. Thats for AES with 128 bit keys. 256 bit key take a 25-30% larger FPGA. My guess is that you can do 1 Gbps in any low cost/low end FPGA with the right architecture ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis ****** Certified USB 2.0 HS OTG and HS Device IP Cores ******Article: 86433
allanherriman@hotmail.com wrote: > I'm curious. Why do you need an FPGA with bitstream encryption? > Piotr wants to do crypto in the FPGA. Also, he certainly needs secret keys inside the FPGA for working with digital crypto (speudo). Piotr needs FPGA bitstream encryption to make sure the secret key is safe and to protect his design and encryption method ! Laurent www.amontec.comArticle: 86434
I checked with an oscillo the clock signal and it's ok and connected on the good pin (N30). The message disappears when i reset the device, i suppose the clock is behind a latch and the reset permits to make the signal pass through this latch.Article: 86435
>Piotr wants to do crypto in the FPGA. 'Doing crypto' does not imply a requirement for bitstream encryption. One needs to change the keys from time to time, so they can't be part of the bitstream. So having secret keys does not imply a requirement for bitstream encryption either. IP protection makes sense, although the actual crypto part of the design will probably be an industry standard design (e.g. AES, 3DES, etc).Article: 86436
>> >> 4. Lattice XP: unknown price, unknown availability, technically suitable, >> I've heard many bad opinions about Lattice, but personally I have no >> experience with their chips. >> I have used lattice since i started programming and find there FPGA and PLD products extremely good, i have found there software to be ideal for low yield projects and cheap!! My last project used the XPGA (a varient on the XP) and found it to have great functionality and easy to get hold of. As mentioned previously in this thread, the distributor WBC will provide you with all Lattice products and will normally give you some shiny samples if you ask nicely :-) Use Lattice chips; not enough people do!!!!!!!! ;-> Hope this helpsArticle: 86437
Xilinx devices tend to do well in this kind of application because of their SRL16s that can be used as delay elements for line buffers or as part of a DSP function. We are already doing work in this area with one of customers on a DVI output stage and video processing unit. In the short term our Broaddown2 product may meet you needs either standalone or with one our add-on Swinyard modules. Q3 will see the launch of Broaddown4 which will offer a higher performance Virtex-4 solution if that is what you need. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Dave Moore" <dave.m.moore@baesystems.com> wrote in message news:42c025a9_1@glkas0286.greenlnk.net... > Hi All, > I'm after a piece of FPGA or DSP-based hardware for the purposes of > performing real time video processing on digital high bandwidth video - > typically DVI 1280x1024 @ 60Hz. > Can anybody recommend a board (either PCI/PC or VME based) that would > have > the appropriate DVI-like inputs and outputs and which would be likley to > have sufficient bandwidth to handle this resolution?. > > Any comments or suggestions are sgratefully receieved. > > Ta, > Dave > > >Article: 86438
Oh I forgot to say that a new option called "OVERCOAT" is now available on Broaddown2 that allows easy stacking of boards if you want an array of FPGAs. Nothing too complex - we simply fit some of the DIL Headers back to front to allow easy insertion into the board in a board stack. The limit on the stack size are the number of Broaddown2s you have, your power supply and physically the space you have. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1119949298.14408.0@ersa.uk.clara.net... > Xilinx devices tend to do well in this kind of application because of > their SRL16s that can be used as delay elements for line buffers or as > part of a DSP function. We are already doing work in this area with one of > customers on a DVI output stage and video processing unit. > > In the short term our Broaddown2 product may meet you needs either > standalone or with one our add-on Swinyard modules. Q3 will see the launch > of Broaddown4 which will offer a higher performance Virtex-4 solution if > that is what you need. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > > "Dave Moore" <dave.m.moore@baesystems.com> wrote in message > news:42c025a9_1@glkas0286.greenlnk.net... >> Hi All, >> I'm after a piece of FPGA or DSP-based hardware for the purposes of >> performing real time video processing on digital high bandwidth video - >> typically DVI 1280x1024 @ 60Hz. >> Can anybody recommend a board (either PCI/PC or VME based) that would >> have >> the appropriate DVI-like inputs and outputs and which would be likley to >> have sufficient bandwidth to handle this resolution?. >> >> Any comments or suggestions are sgratefully receieved. >> >> Ta, >> Dave >> >> >> > >Article: 86439
As a development board manufacturer there isn't a lot point supporting an old interface. The cost of doing a new design don't make a viable business proposition unless the customer is bearing part of the costs or there is a niche market that could have reasonable shipment numbers. We are looking at PC104PLUS and have already got a board that we did for a customer built and working. It is likely that we will do a PC104PLUS board but no release timescales yet. If some comes along and asks for any reasonable number of such boards they will tend to get done quickly. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "amko" <sinebrate@yahoo.com> wrote in message news:1119885824.518330.202810@g47g2000cwa.googlegroups.com... > Hello Everybody ! > > I have looking for FPGA PC104 development board for some time. I like > to buy PC104 development board with new generation of FPGAs/CPLDs. > > I think it is not good decision to buy board with old FPGAs or CPLDs > (Xilinx: Spartan, Spartan 2, Virtex E.. or Altera: Flex, ACEX or > APEX..), because of providing these devices in future. ????? > Until now I have found only one vendor which have PC104 card with > Virtex 2 (http://www.derivation.com/), but this is big animal for my > necessity :) > > Also I have found some vendors which offer PC104 development board with > old FPGAs (Nova Engineering, APS, Mesa Electronics,Arius). Probably the > main reason why new FPGAs are not used on PC104 development board is > that PC104 bus is 5V and the most new FPGAs/CPLDs are not 5V > tolerant?????? > > > Do you know any vendor which manufactured FPGA PC104 card with new > generations of FPGAs/CPLDs? I do not need any special peripherals in > first development cycle. I need some memory (???), enough(???) I/O pins > (3.3V, 5V), oscillator (???), JTAG, UART... > > And do you know where I can get ISA bus specifications??? > > thank you, > > Regards, > > Amir >Article: 86440
> It depends on how you implement those registers. Normally, Bus2IP_BE plays
> role besides Bus2IP_RdCE/WrCE and the IPIF has byte-steering logic to put
> the byte to the correct lane. So you should be able to do byte read/write.
> >
> > I always believed that the "Bus2IP_WrCE"signal will assume only "10000",
> > "01000", "00100", "00010" and "00001" and the corresponding register
> values
> > would be read out from the corresponding registers. Is it possible that
I
> Your assumption is correct, but you'll also need Bus2IP_BE in order to
> support writing to individual byte.
> > can read out the values "byte-shifted"?
I had a small code like this in my C program to see what happens when I read
between these addresses:
for (counter=0x08;counter<0x10; counter++){
data = read_decoder_register(XPAR_PLB_DEVICE_0_BASEADDR,counter);
printf(" Data read is = %d\n\r", data);
}
I had written integer value 2 in my 64bit register and for each count, the
corresponding integer value that I read out is:
Data read is = 2 which is 10
Data read is = 512 which is 10 00000000
Data read is = 131072 which is 10 00000000 00000000
Data read is = 33554432 which is 10 00000000 00000000 00000000
Data read is = 0
Data read is = 0
Data read is = 0
Data read is = 0
These are the values that I read out. I still cannot find any good
explanations for this.
One more Question. How can I control this Bus2IP_BE signal in my C code?
Thank you.
Joey
Article: 86441Hi I have a small Question. How can I control this Bus2IP_BE signal in my C code? JoeyArticle: 86442
Joey wrote: > Hi > > I have a small Question. > How can I control this Bus2IP_BE signal in my C code? By using according functions to access your peripheral. I.e. if you use XIo_In8 to read from your peripheral, only one of the bits in Bus2IP_BE will be set (because you're performing a one-byte-read), if you use XIo_In16, then two will be set (2-byte-read), if you use XIo_In32, all four will be set. Same applies for the _Out-functions, or if you use pointers to access memory (then if it's a pointer to a char, one bit in Bus2IP_BE is set, if it's a pointer to a word, two bits are set and so on). cu, SeanArticle: 86443
All went well... did the job marvellously. I can use this knowledge to take over the world... much appreciated. TaArticle: 86444
Thank you for your answer John, A few things more I like to know. First can you please tell me does it then make sense to buy PC104 board with old FPGAs (Xilinx: Spartan, Spartan 2, Virtex E.. or Altera: Flex 10k, ACEX or APEX 2..) if design which I should make must be actual at least next 5 years? Or in other words I want to know if you think that these development boards (with old FPGAs which I listed) will be provided in next five years. Or you may recommend me if it is better to buy Non-PC104 FPGA development board with new generations of FPGAs and design hardware bridge which will have on one side PC104 bus. I need PC104 interface bus because I work design for physics accelerator where PC104 format and PC104 bus is some kind of standard. I am also interesting in PC104PLUS board, which you have mentioned above? What will contain this borad. Thank you for answer in advance?? Regards, AmirArticle: 86445
Historically FPGAs in general have had exceedingly long lifetimes compared to other chips. However both Xilinx and Altera have obsoleted parts and will continue to do so. If I was starting a new design for a customer I would normally recommend the latest family to maximise lifetime and minimise cost. Sometimes there are a few exceptions to that rule. For instance Spartan-2 is 5V tolerant without external resistors or bus switches. Good for space critical designs. Lifetimes of development boards tend to be long but products can disappear or be obsoleted. You have no guarantee that a product will be here in 5 years. Other factors can also kill off a board. 64 bit PCI is now disappearing from PC motherboards and may result in 64bit PCI based development boards not having a host system. Are you going to buy a board that you can't buy a host for? The board we currently have is V2-PRO based. Given that V4 is new and we already use Spartan-3 we probably will go for one of these for a new development board. We are likely to use a similar approach to the Broaddown family with minimalist standard fit of components and allow user selectable modules for the required comms and features. That said we may fit CAN transceivers, high speed serial interfaces(V4 only) and flash memory to the design. The latter two are already working on the V2-Pro design with the high speed link operating successfully at 2.5GBit/s. If you requirement is likely to be more than one off, or needs a special long term support agreement, then please take this off-line. We can offer a lot more than what we discuss publicly either here or on our website. Any of the emails on our website can be used to contact me. Just mark it for my attention and it will be directed to me. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "amko" <sinebrate@yahoo.com> wrote in message news:1119960707.820170.182550@g43g2000cwa.googlegroups.com... > Thank you for your answer John, > > A few things more I like to know. > First can you please tell me does it then make sense to buy PC104 board > with old FPGAs (Xilinx: Spartan, Spartan 2, Virtex E.. or Altera: > Flex 10k, ACEX or APEX 2..) if design which I should make must be > actual at least next 5 years? Or in other words I want to know if you > think that these development boards (with old FPGAs which I listed) > will be provided in next five years. > > Or you may recommend me if it is better to buy Non-PC104 FPGA > development board with new generations of FPGAs and design hardware > bridge which will have on one side PC104 bus. I need PC104 interface > bus because I work design for physics accelerator where PC104 format > and PC104 bus is some kind of standard. > I am also interesting in PC104PLUS board, which you have mentioned > above? What will contain this borad. > > Thank you for answer in advance?? > > Regards, > Amir >Article: 86446
Hello,
I know FPGA's are not suitable for sieving large numbers however
one set of numbers (Proth numbers, related to the Sierpinski
conjecture) I think would fit an FPGA quite well.
Sorry if this is a relatively basic or silly question but I'm
a novice with FPGAs although I've been reading up on them and
playing around with the software.
I'd be dealing with numbers in the 32 to 64 bit range (current
limits of sieving are around 50 bit numbers) and hoping to put
many sievers on one FPGA (I have a Spartan-3 dev kit with
200k gates).
The basic algorithm is this:-
p - 64 bit number (a prime) although top bit will never be set
r - 64 bit number (0 <= r < p)
maxn - 50,000,000 but easily replaced with 2^26 if easier
The above would be supplied by a controlling computer via
parallel or RS232 connection and stored somewhere in the 1M-byte
of RAM. The controlling computer would make sure there are plenty
of these values available in memory for the sievers to grab.
An individual siever would:-
grab p and r from memory and mark this as 'in progress'.
set initial_r=r /* r being another 64 bit var */
set n=1 /* n is a 64 bit counter */
while( n <= maxn ) {
if( r == 0 ) {
stop. shove n back into memory and mark result as done(1)
}
r=r<<1; /* multiply by 2 */
r--; /* decrement r by 1. r will always be > 1 so no need for
bounds checking */
if( r >= p ) {
r-=p; /* again, always +ve result */
}
n++; /* increment n by one */
if( r == initial_r ) { /* comparison */
stop. shove n back into memory and mark result as done(2)
}
}
Obviously I'd like as many sieve units as possible on the final
FPGA but I'd be looking to implement just one at first (without
the control unit), then the control function, then multiple
sievers.
Sound feasible for an FPGA?
Sound feasible for an FPGA novice :-) ?
Ta,
-Alex
Article: 86447Hi Alex, > Sound feasible for an FPGA? The single Siever won't be much of a problem, but you will ultimately be limited by your memory bandwidth if you want to implement multiple Sievers. > Sound feasible for an FPGA novice :-) ? Oh, definitely doable. Apart from the ultra-basics it will teach you FSM design, pipelining and other useful stuff. Later on you should be able to tack an embedded CPU (preferrably NIOS due to its easy bus structure) to the Siever(s). However, please use a simple SRAM. They're more expensive, but at least you don't have to complicate things by having to write the SDRAM state machine as well. Good luck! BenArticle: 86448
Hi Rick, What about Arrow? BenArticle: 86449
How exactly does the address translate to an OCM address? I can't really find anything solid on the matter and I looked at the values of the DSARC register and but I couldn't really find any connection between that value and my CPU OCM addresses. I know the upper 8 bits are not used, bit I didn't understand why the lower 2 bits are discarded, is this for 32 bit alignment? Thanks in advance Jim
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