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Hi, I am working with the PPC405 processor on a Xilinx Virtex2Pro board and was wondering if it's possible to access the reservation granule where reservations for the semaphore instructions lwarx and [i:a40a6a8998][b:a40a6a8998]stwcx[/b:a40a6a8998][/i:a40a6a8998] are set? Your help will be greatly appreciatedArticle: 86551
Ok, without looking at it in more detail the math is beyond me at this point. If you want to get a feeling for clock rates achievable on the FPGA, just try some simple stuff and put it through the tools. Create a 16 bit adder in VHDL/Verilog and put it through the tools. Do the same for comparator. Try 32 bit and 64bit adders. Make sure you register the inputs and outputs of course. Not a bad way to learn an HDL language either. Try something simple in the HDL and have a look to see what the synthesizer created. Remember that the underlying spartan 3 logic cell has one 4 input lookup table (LUT) and 1 flipflop. The flip flop can be used for pipelining and often it is already an unused resource so effectively it comes for free. Yes there is always a tradeoff between FPGA resource usage and speed (clock rate). E.g. a bit serial multiplier uses very little logic resource but takes multiple clock cycles to compute the result. Alternatively a fully parallel multiplier can produce a result every clock cycle. Regards AndrewArticle: 86552
I guess this is more of a Xilinx question than a VHDL question. Anyways, once again, I find myself wanting to set the value of a generic on the top-level of my chip design from the synthesis tool -- XST, in this case -- either from the GUI or from the command line. I know I can do this in Precision ... So what's the magic incantation? Thanks, -a (devel (at) latke dot net)Article: 86553
Peter & Austin, I deeply apologize for not being of aware of these issues. My intentions were good. Really sorry. AmrArticle: 86554
Peter and Austin, Again, please do accept my apologies. I asked this question just out of curiosity and maybe out of naiveness !! AmrArticle: 86555
Hi Stuart, Stuart J Adams wrote: > Anyone have experience putting multiple microblaze's > in a single FPGA ?? We are working with multi CPU microblaze systems - it worksd pretty much as expected under current EDK tools. > Is it practical to put 2/4/8 processors in a single > device and have them share a single DDR DRAM memory > subsystem ? Technically it's easy, just design it in EDK and off you go. But... if you hang 8 MicroBlazes off the OPB connecting to OPB_DDR controller, they'll spend a lot of time waiting on the bus for memory read/write. Caches help of course, but BRAM is a precious commodity. The new multichannel controller (mch_opb_sdram) and CacheLink interfaces get memory accesses off the OPB bus, but you are limited in how many separate memory ports you get (4), and thus how many CPUs can share that memory (2 CPUs, one channel each for I and D). Regardless of which you choose, there's no coherency between the CPU caches. This requires some thought if you are using the shared memory for interprocessor communications. Interesting stuff, and microblaze + EDK is a nice platform for experimentation. Regards, JohnArticle: 86556
Amr, do not feel bad. No need to apoligize. Austin and I are able to decide what we want to tell the public, and what is better left un-said. Keep asking questions, and even complaining (hopefully not too much). We will answer to the best of our ability, but also in loyalty to our employer. Cheers Peter AlfkeArticle: 86557
Peter, Thanks a million for the reply. This is really what I needed to hear from you. I can tell you for sure, I'll keep asking scores of questions, but complaining a little:) AmrArticle: 86558
Hi gabor,
Thanks for the clarifications.
The reading will basically happen in two phases.The flow is given
below, i will start implementing the same.
check it and reply if any clarifications.
**********READ PHASE 1**********
Step 1
I2C Start (master) S
Step 2
I2C General address (master) 1 0 1 0 0 0 0 0
Step 3
I2C Acknowledge (slave) A
Step 4
I2C write register address (master) 0 0 0 0 0 0 0 0
Step 5
I2C Acknowledge (slave) A
Step 6
I2C Stop (master) P
**********READ PHASE 2**********
Step 7
I2C Start (master) S
Step 8
I2C General address (master) 1 0 1 0 0 0 0 1
Step 9
I2C Acknowledge (slave) A
Step 10
I2C Read data (slave) Data Data Data Data Data Data Data Data
Step 11=86
I2C Not acknowledge (master) A
Step 12
I2C Stop (master) P
=86Repeat steps 10 and 11 for all bytes read. Master does not
acknowledge the last read data received.
Gabor wrote:
> praveen.kantharajapura@gmail.com wrote:
> > Hi Gabor ,
> >
> > Thanks for the reply. My EEPROM is write protected i will only be
> > reading the first 128 bytes, is this flow diagram all right.
> >
> >
> > 1-bit 8-bits 1-bit
> >
> > Start from master --->> EEPROM Slave address("10100001") -->> ACK
> > from eeprom --->>
>
> Actually you need to start with write address "10100000" in order
> to write the address register (you don't need to write the EEPROM
> array so write protect doesn't matter).
>
> >
> >
> > 8-bits 1-bit
> > Write register address "00000000" --->> ACk from EEPROM
>
> Right here you need to switch to read mode. There are two
> ways to do this. Either master sends Stop followed by Start
> or master sends repeated start. If you intend to reuse this
> code for other peripherals besides EEPROM, you'll find the
> repeated start is compatible with more chips.
>
> Then you need to provide slave address "10100001" for read
> and get ack from slave then:
>
> > 8-bits 1-bit
> > --->> Data[0]
> > from EEPROM --->> ACK from master
> >
> > 8-bits 1-bit
> >
> > ................. --->>Data[127] from EEPROM --->> STOP from master
> >
> > I will generate the STOP condition after receiving 128 bytes.
> >
> > Any comments on this.
> >
> >
> > Regards,
> > Praveen
> >
> >
> Also you talk about "bits" when you send start and stop. These
> conditions
> do not toggle the SCL line so they are not usually counted as "bits"
> as would be data or Ack cycles.
>=20
> Regards,
> Gabor
Article: 86559>>>>> "Sven" == Sven Gowal <sgowal@gmail.com> writes: Hi, Sven> I haven't been able to find any useful resources on how to Sven> install the new Linux 2.6 kernel on the ML310 board. Basic ML300 support is in the normal kernel.org tree from 2.6.10 onwards. See: http://ozlabs.org/pipermail/linuxppc-embedded/2004-October/015637.html -- Bye, Peter KorsgaardArticle: 86560
> One way is to scramble the data, which creates additional transitions > (The very low probability of the scrambler actually eliminating > transitions can be statistically ignored). This depends on the scrambler polynomial. The original POS (Packet Over SONET) spec, RFC1619, relied on the 7th order SONET polynomial for scrambling. This was unfortunately easy to 'spoof' with specially created packets. An additional 43rd order scrambler was added in RFC2615 to reduce the chance that this denial of service attack could succeed. "The major change from RFC 1619 is the addition of payload scrambling ... RFC 1619 was operationally found to permit malicious users to generate packets with bit patterns that could create SONET/SDH-layer low-transition-density synchronization problems, ... The use of the x^43 + 1 self-synchronous scrambler was introduced to alleviate these potential security problems. Predicting the output of the scrambler requires knowledge of the 43-bit state of the transmitter as the scrambling of a known input is begun. This requires knowledge of both the initial 43-bit state of the scrambler when it started and every byte of data scrambled by the device since it was started. The odds of guessing correctly are 1/2**43, with the additional probability of 1/127 that a correct guess will leave the frame properly aligned in the SONET/SDH payload, which results in a probability of 9e-16 against being able to deliberately cause SONET/SDH-layer problems. This seems reasonably secure for this application." http://www.ietf.org/rfc/rfc1619.txt http://www.ietf.org/rfc/rfc2615.txt Regards, AllanArticle: 86561
Hi Mike, thank you for your answer. In a later stage of the design the read positions of the RAM will be pushed back into the FIFO whereas the corresponding entry in the RAM will be cleared that is filled with zeros. But right now I want to perform more functional test sequences with regard to writing positions in the RAM. But since there are only 32 "positions" available I'd need to reset the content of the RAM after 32 write actions into it. Rgds Andr=E9 Mike Treseler schrieb: > ALuPin@web.de wrote: > > > > After the FIFO is empty I could reset my design within my testbench. > > Yes, just push more data in using the testbench. > > > But the contents of the RAM should also be resetted or rather > > be initialized again with zeros. > > That's not what will happen on the bench. > A fifo can only access data it has pushed in. > You want 'U's elsewhere to make sure your > head and tail counters are working ok. >=20 > -- Mike TreselerArticle: 86562
Hi, do you have cache enable? Do you use a 64 bit pointer during the copy routine? How does your c-code looks like? AndreasArticle: 86563
I'm getting the error during building that it cannot find a certain net that is referenced in the .ucf file. But the net does exist. It's an input clock signal that is defined in the VHDL file and the MPD. Is tehre somewhere else I need to define it for the ucf to be able to locate it? Thanks again. (Sorry for so many questions...) Jim TuilmanArticle: 86564
No. no error messages. But sometimes, and only sometimes, bitgen fails and the usual "Send error report to microsoft" window will appear. But as I said, only sometimes. "Sean Durkin" <smd@despammed.com> schrieb im Newsbeitrag news:3ifq1hFl8b6rU1@individual.net... > Joey wrote: > > Hello > > > > I have a strange problem. I am trying to implement a decoder as a plb > > peripheral. The problem appears when I am trying to synthesis the core. > > Sometimes it synthesises properly using up 34 block rams. But sometimes, it > > doesn't. Can anybody give any reasonable explanations for this. > A little more info would be helpful... What happens if it doesn't > synthesize "properly"? Any error messages? > > cu, > SeanArticle: 86565
Sylvain Munaut <com.246tNt@tnt> wrote: > I'd like to find a really small FPGA that I could solder by hand, > like in a VQ44 or VQ64 package. Ideally, it should only require a > single 3.3v supply, but a dual supply core/io would be OK too if > really necessary. Actel has the A1010B in CQ84. I don't think there are smaller packages left on market. Backdraw is the high price, and the fpga is only one time programmable. The fpga needs also 5V. And 500LE migth be far more logic than the a1020 provides. If you come to numbers >1000 you could Ask actel for the a54sx in the same package. The A54Sx come along with 3.3V. If your requirement small is only because of hand soldering, you could also look at other packages with 0.5 pin pitch like PQ and TQ. bye thomasArticle: 86566
Jim, Leave the constraint out of the UCF, run translate, and look at the Floorplanner. Can you see the net then? Or, with the constraint still out of the UCF, run map, and use the FPGA editor to find the net. Cheers, Syms. <zoinks@mytrashmail.com> wrote in message news:1120122060.439566.186510@z14g2000cwz.googlegroups.com... > I'm getting the error during building that it cannot find a certain net > that is referenced in the .ucf file. But the net does exist. It's an > input clock signal that is defined in the VHDL file and the MPD. Is > tehre somewhere else I need to define it for the ucf to be able to > locate it? > > Thanks again. (Sorry for so many questions...) > > Jim Tuilman >Article: 86567
Hi all, Please help me with JTAG routing. How can i connect the TDI of the FPGA to a I/O pad. I want this connection in normal mode. Already posted a message but got no replay. is there any other procedures i have to complete to get a replay. Please help meArticle: 86568
"vssumesh" <vssumesh_asic@yahoo.com> schrieb im Newsbeitrag news:1120127683.077609.4560@z14g2000cwz.googlegroups.com... > Hi all, Please help me with JTAG routing. > How can i connect the TDI of the FPGA to a I/O pad. I want this > connection in normal mode. > Already posted a message but got no replay. is there any other > procedures i have to complete to get a replay. Please help me > JTAG pins are directly connected only to on chip TAP and are not directly accessible, aall you can do is to connect to the BSCAN primitive, but that has some limitations, depending on the device selected. There is no other way to connect to TDI pin otherwise. you get better reply if you explain why you need that connection and/or what you want to accomplish AnttiArticle: 86569
Hi I am very glad to announce that the very first succesful 3rd party reference design has been verified on the smallest ever Linux ready standalone FPGA module. Entner Electronics did send us their Eric5 reference design (as a .bit file made with ISE), I copied the attachment onto mini-SD card, inserted it into the card slot, powered up and - Thomas could you please comment back our response time? How many minutes did elapse from the time you sent the email until I replayed back with 'it works' confirmation? I am happy as a cricket! And Entner Electronics has really deserved their free of charge HydraXC module its almost on the way to them already! links: http://www.hydraxc.com - the home of the smallest standalong FPGA computer http://www.entner-electronics.com the makers of ERIC5 tiniest FGPA processor http://wiki.openchip.org/index.php/HydraXC - un-official hydraxc support pages Antti PS needless to say the Eric5 demo worked the first time we tried. Thomas has not seen the hydraxc fpga module, and I have not had access to the Eric5 design files. It just worked first attempt tried.Article: 86570
I'll try that, thanks. Altough I never used floorplanner, or the FPGA editor. I just started this 2 months ago :)Article: 86571
Hello... Wasn't there once an application note on Actel.com for initialising internal RAM from an SPI memory? rickArticle: 86572
Ray Andraka wrote: > Austin Lesea wrote: > > > Marc, > > > > Contact your FAE for information. > > > > The information packet on this subject states the shift in Vt is > > reversable. > > > > Austin > > As does everything I found in general on NBTI by searching google with > "NBTI" Howdy Ray, Google had found me a few mentions of it sometimes being irreversable under certain conditions - hence the question. Perhaps I'm misunderstanding it, or it doesn't apply to the problem that the V4's have. Here's the best reference: http://www.reed-electronics.com/semiconductor/article/CA602829?spacedesc=webex Best regards, MarcArticle: 86573
I already found the problem: apparentlythe ucf files are case sensitive, and I forgot a cap d'oh!Article: 86574
Hi Antti, great that things are working fine in the first try. So this was really a good "joint venture". Your response time was 17 minutes, but maybe we should also subtract some minutes of e-mail-delay from that ;-) BTW: The design includes - ERIC5-core (largest version with stack and interrupts) - UART - I/O-Ports (LED and LCD-display) - Download-functionality via UART The resource usage is 376 LUTs in a Spartan3-1000 (less then 3%). Of course ERIC5 is also available for all other popular FPGA-families, the smallest core-version takes about 100 LEs in an Altera Cyclone. I am already curios for the HydraXC ;-) Regards Thomas www.entner-electronics.com "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:da0isp$ab$01$1@news.t-online.com... > Hi > > I am very glad to announce that the very first succesful 3rd party > reference > design has been verified on the smallest ever Linux ready standalone FPGA > module. > > Entner Electronics did send us their Eric5 reference design (as a .bit > file > made with ISE), I copied the attachment onto mini-SD card, inserted it > into > the card slot, powered up and - Thomas could you please comment back our > response time? How many minutes did elapse from the time you sent the > email > until I replayed back with 'it works' confirmation? > > I am happy as a cricket! > > And Entner Electronics has really deserved their free of charge HydraXC > module its almost on the way to them already! > > links: > http://www.hydraxc.com - the home of the smallest standalong FPGA computer > http://www.entner-electronics.com the makers of ERIC5 tiniest FGPA > processor > > http://wiki.openchip.org/index.php/HydraXC - un-official hydraxc support > pages > > Antti > > PS needless to say the Eric5 demo worked the first time we tried. Thomas > has > not seen the hydraxc fpga module, and I have not had access to the Eric5 > design files. It just worked first attempt tried. > >
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