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Hi Sunny, Others have covered the main things to watch out for here. There is one more: If you want to consider stopping the clock entirely to a CPU or set of CPUs, you should consider having them jump to some sort of sleep routine that will spin until woken up. The reason is that you don't want the processor to attempt a memory or peripheral access when it is sleeping, as this will essentially 'lock' access to the slave in question (which could possibly be acceptable depending on your system, but if you have shared memory and not all processors are 'turned off' it can be bad news). Obviously you'll either need an instruction cache (and a cycle through the sleep loop to get that code cached) so that no memory access is initiated. About JTAG: The Tck frequencies vary by the cable that you're using. I believe the USB Blaster is fastest with a 10MHz Tck (this is from memory, not a datasheet). The JTAG UART and Nios debug core logic were built with the assumption that the CPU clock is running more quickly. Obviously if you do not want to debug or use the JTAG UART this won't be a consideration. Jesse Kempa Altera jkempa -at- altera -dot- comArticle: 86251
I have been wondering about how to use DCMs in a design lets say im doing some dsp filter design and I want my embedded multipliers to run as fast as possible. I synthesize my design using ISE or some other tool and my design synthesizes with a clock rate of say 75 mhz. Now lets say I add my DCMs and asychronous FIFO's to this design around the embedded multipliers. The thing that worries me is that i still have some delays in my clock signal, as well as in the data signals in my design. When I use the DCM, how do i know that the clock wont switch faster than the device can actually register? When designing something like this how do you know what is a safe multiplication factor so that all signals will behave as expected? thanks -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 86252
Thank you both for your excellent answers. The function may be a good workaround, and I also suspect that presto wasn't enabled. Thx again, Bert CuzeauArticle: 86253
The situation will get better, much better. This is work in progress, so I do not want to create confusion or overly optimistic (early) expectations. But we are (painfully) aware that something must be done, and it will. Witness the improvements earlier this week... Peter AlfkeArticle: 86254
"Peter Alfke" <peter@xilinx.com> wrote in message news:1119544967.668456.249260@o13g2000cwo.googlegroups.com... > The situation will get better, much better. This is work in progress, > so I do not want to create confusion or overly optimistic (early) > expectations. But we are (painfully) aware that something must be done, > and it will. Witness the improvements earlier this week... > Peter Alfke That's good to hear (despite warnings about early optimism :-)). I look forward to painless low volume chip-shopping. Thank you for the hint! DJ --Article: 86255
Vladislav Muravin wrote: > Hello, > > If you instantiate a memory manually, then you might not specify the valid > path to MIF file. > I think that when you use the memory using the instance template generated > by CoreGen, there is a link to the MIF file, check if this link is valid. > If it is, but you still do not get the right values, check with xilinx, i.e. > you are using compiled libraries, may be there's a problem with the compiled > model? > Any possible limitations of this model? > Cannot really think of anything else... > > Vladislav I would also take a look to the XCO file. It may be corrected in 7.1, but ISE 6.3 may fail to update XCO files if they are located in a directory different from the main project. Only the local copies of the XCO (created when the IP is generated) present in the main project directory present are updated.Article: 86256
Hi Jesse (o; 1st: thanx for the Linux sources on CD (o: kempaj@yahoo.com wrote: > Rick, > > Altera maintains the GNU toolchain for Nios II. As for uClinux, I am > quite ignorant on the matter (I am not sure if any toolchain changes > were required). You might ask in the uClinux area of www.niosforum.com. Actually I have started checking out current microtronix uclinux and official uclinux distribution to do a merger into official tree since Microtronix uClinux only allows building on Windows. > > Altera *usually* has all these toolchain sources available on public > FTP - I noticed your mentioning that they were removed in a separate > post so I had a look and it appears that I cannot locate them either > (the sources for all prior versions were up there as of a couple of > months ago when I last checked). I am assuming this is an oversight and > will follow-up to see what happened. The last version I saw was called gnupro-3.2...those were only toolchain sources for nios32 as I remember and were based on gcc-2.95.x/binutils-2.10 or lower... If Altera agrees I could mirror the NIOS2 sources along with MacOSX binaries under uclinux.net (o; rickArticle: 86257
Hello, Started to look at the xapp635 to implement link port interface in Virtex II device. I ran a simulation (VHDL version) with the test bench that came with the app note and it did not pass the test. There is a bug in the receiver implementation. It fails at the very first reception. I have identified the bug to be we_en signal going to the block ram. Did anyone have any other issues with this core? The app note claims to have achieved 500 Mb/s per line, which translates to 250 MHz clock. Now I have my suspicions on these numbers :-). Does anyone have any numbers that they achieved? The test board Xilinx used seems to be Danube DSP board from Bittware. The Bittware website claims a max throughput on these links to be 1GB/s which translates to 125 MHz clock rate. Maybe someone had better luck with Verilog version of the core. Cursory look into verilog source files tells me it also has the same bug. Fixing the bug is going to be a pain as there are no comments what so ever in the code. Looks like they intentionally stripped all the comments before releasing the code. Wondering if its better to write my own receiver based on the same technique rather than trying to fix this one. Wondering if I can open a webcase or 'bug' Xilinx about this one as its only a xapp, is free and comes with no warranty what so ever. BrijeshArticle: 86258
On Thu, 2005-06-23 at 15:43 -0400, Brijesh wrote: > Hello, > > Started to look at the xapp635 to implement link port interface in Virtex II > device. I ran a simulation (VHDL version) with the test bench that came with the > app note and it did not pass the test. There is a bug in the receiver > implementation. It fails at the very first reception. > <snip> > Fixing the bug is going to be a pain as there are no comments what so ever in > the code. Looks like they intentionally stripped all the comments before > releasing the code. Wondering if its better to write my own receiver based on > the same technique rather than trying to fix this one. I ran into the same thing although I'm only looking at a 1-bit implementation. The _complete_ lack of comments in the VHDL is crazy. Given the fact that it is meant as a design starting point I would have imagined it to be about 90% comments to explain why things were done and other options that are possible. The description in the PDF, while it helps, is no replacement for inline comments. I just started working on my implementation so I can't really give any more guidance at this point. I found XAPP265 to be more useful than the two TigerSharc related app notes. The only exception is that the receiver clock is not continuous so you can't take it into a DCM. James.Article: 86259
someone92@hotmail.com wrote: > Hi, > I'm starting to learn FPGA programming (using a Xilinx Spartan II > 200K). I will use VHDL and already have bought VHDL books, but I think > I also need a general introduction to FPGA so I plan to buy a book on > FPGA. I found this one: > > FPGA-Based System Design by Wayne Wolf > > I would like to know if this book is any good, especialy for a beginer > like me. I also if it will be useful in the futur for some more > advanced stuff, or is it just a entry level book that you throw away > once you know the stuff. It's expensive, that's why I don't want any > chance. > > If you have any other suggestion it could be useful. what I'm really > looking for is an introduction on FPGA structure (CLB,IOB,BLOCK > RAM,etc..), not a VHDL or VERILOG programming book > > Thanks > Did you check Clive Maxfield's The Design Warrior's Guide to FPGAs ? Much nicer to read than a databook anyway. Bert CuzeauArticle: 86260
bijoy wrote: > Hi > > Any body used FFT core given by coregenerator in Xilinx ? > > Does it work as they said in their data sheet.. > > regards bijoy It works very well, it is efficient, and has lots of nice features. As for any macro, I would recommend making some (RTL) simulations to ascertain how it must be initialized and used. Bert CuzeauArticle: 86261
Bo wrote:
>For what it's worth..we were told by visiting Xilinx engineer to NOT upgrade
>our tools to 7.x but instead wait for 8.1 release in August...
>
>
>
I'm still using 6.3 SP3 because there are a few show-stoppers in 7.1.
Remains to be seen whether they are all fixed in SP3 or not.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 86262Brijesh wrote: > Hello, > > Started to look at the xapp635 to implement link port interface in Virtex II > device. I ran a simulation (VHDL version) with the test bench that came with the > app note and it did not pass the test. There is a bug in the receiver > implementation. It fails at the very first reception. > > I have identified the bug to be we_en signal going to the block ram. > > Did anyone have any other issues with this core? > The app note claims to have achieved 500 Mb/s per line, which translates to 250 > MHz clock. Now I have my suspicions on these numbers :-). Does anyone have any > numbers that they achieved? > > The test board Xilinx used seems to be Danube DSP board from Bittware. The > Bittware website claims a max throughput on these links to be 1GB/s which > translates to 125 MHz clock rate. > > Maybe someone had better luck with Verilog version of the core. Cursory look > into verilog source files tells me it also has the same bug. > > Fixing the bug is going to be a pain as there are no comments what so ever in > the code. Looks like they intentionally stripped all the comments before > releasing the code. Wondering if its better to write my own receiver based on > the same technique rather than trying to fix this one. > > Wondering if I can open a webcase or 'bug' Xilinx about this one as its only a > xapp, is free and comes with no warranty what so ever. > > Brijesh I have not used Xapp635, but I have use the Verilog link port design that is in Xapp634, and it works for me. I am using it to comunicate between Virtex-II FPGAs, and not with a TigerSHARC. Maybe it is worth a look. Regards, John McCaskillArticle: 86263
Hi, The volunteer CPCNG Design Team is working on a family computer based on eZ80 CPU. We have designed a board (euroboard, 160x110, 4 layers, as you can see at http://cpcng.hytherion.com). Gerber files are ready for production. We search someone to help us for the programmation of the Xilinx FPGA (includes the development of IDE, CRTC6845, I/O interception trick, SRAM interface). We have defined the pinout but our last FPGA developer is not able to help us now. We are motivated and interested for fast result. If you're interested to join the team, please contact me at ChristopheGuelff@aol.com Thanks ! ChrisArticle: 86264
Easy reading, a bit chatty. Uneven covereage, dwells on the subjects he understands well, is short where he doesn't. But, don't we all... ;-) Peter AlfkeArticle: 86265
All, Face it, Peter and I both are absolute true believers in on-line shopping. And we believe that buying FPGAs should be no more painful than buying a book at Amazon.com. Sure, if you want 25 of them, or if you need support and services, you may not want to buy online, but rather through your local and helpful distributor who will actually send the FAE to you to help (if needed). (A side note, ever try to return something non-technical and totally trivial bought online? Advice: just don't even try it, it is often too painful with the way most web retailing is done today. They get your credit card number, they ship, they bill. That is about all they can do, or will do.) That said, we do have to balance all the requirements. After all, we have agreements with many distributors, representatives, and other partners. We have IOS 9000, ISO 14001, TS16949 (basically the only FPGA company with this pedegree of Quality Standards approvals). We have international customers. We have tax laws to meet. We have export/import laws that have to be considered. Not too mention offering the excellent quality of service all of our customers have grown to expect. We not only have to have an online shop, but the damned BEST online shop! Since you can buy anything you like on line (basically), it seems all too easy. In reality, it is a difficult and complex issue. There are many pits to fall in. So, optomism is great, but patience is a virtue we may have to ask you to indulge us with while we work our way through the maze of issues to allow you to simply just be a click away from your parts ... Austin Dr Justice wrote: > "Peter Alfke" <peter@xilinx.com> wrote in message > news:1119544967.668456.249260@o13g2000cwo.googlegroups.com... > >>The situation will get better, much better. This is work in progress, >>so I do not want to create confusion or overly optimistic (early) >>expectations. But we are (painfully) aware that something must be done, >>and it will. Witness the improvements earlier this week... >>Peter Alfke > > > That's good to hear (despite warnings about early optimism :-)). > I look forward to painless low volume chip-shopping. > > Thank you for the hint! > > DJ > -- > >Article: 86266
Geoff, I would set the clock constrints for the fastest clock that is to be used out of the DCM. Austin geoffrey wall wrote: > I have been wondering about how to use DCMs in a design > lets say im doing some dsp filter design and I want my embedded multipliers > to run as fast as possible. I synthesize my design using ISE or some other > tool > and my design synthesizes with a clock rate of say 75 mhz. Now lets say I > add > my DCMs and asychronous FIFO's to this design around the embedded > multipliers. > The thing that worries me is that i still have some delays in my clock > signal, as well > as in the data signals in my design. When I use the DCM, how do i know that > the clock > wont switch faster than the device can actually register? When designing > something like > this how do you know what is a safe multiplication factor so that all > signals will behave as expected? > > thanksArticle: 86267
info_ wrote: > someone92@hotmail.com wrote: > >> Hi, >> I'm starting to learn FPGA programming (using a Xilinx Spartan II >> 200K). I will use VHDL and already have bought VHDL books, but I think >> I also need a general introduction to FPGA so I plan to buy a book on >> FPGA. I found this one: >> >> FPGA-Based System Design by Wayne Wolf >> >> I would like to know if this book is any good, especialy for a beginer >> like me. I also if it will be useful in the futur for some more >> advanced stuff, or is it just a entry level book that you throw away >> once you know the stuff. It's expensive, that's why I don't want any >> chance. >> >> If you have any other suggestion it could be useful. what I'm really >> looking for is an introduction on FPGA structure (CLB,IOB,BLOCK >> RAM,etc..), not a VHDL or VERILOG programming book >> >> Thanks >> > > Did you check Clive Maxfield's > The Design Warrior's Guide to FPGAs ? > > Much nicer to read than a databook anyway. > > Bert Cuzeau Aahh...the guy who wrote that Linus Torvalds is from Sweden (o; rickArticle: 86268
Can anyone in the know comment on what the likely order of availability of Spartan-3e parts (in sub-1000 piece quantities, not zillions) will be? I'm hoping that the 3S500E in the chipscale BGA will be one of the first; I've been waiting for a high-density FPGA in a tiny package. It's a shame that none of the Spartan-3 parts larger than the 3S50 are available in that package. Thanks, EricArticle: 86269
"Davy" <zhushenli@gmail.com> wrote in message news:1119535229.847172.158780@g44g2000cwa.googlegroups.com... > Hi all, > > I want to add two 6 bits signed digit. > Something like 6'b10_0110, the MSB '1' is negative digit,other'00100' > is absolute value. > Or Something like 6'b00_0110, the MSB '0' is positive > digit,other'00100' is absolute value. Did you try 6'sb100110 + 6'sb000110 ? That is a signed addition. That is a lot safer than doing the 2's complement conversion your self and using '95 unsigned addition. It is Verilog 2000, so use the Verilog 2000 mode on your tool (complain if they still don't support Verilog 2000). > > How to design a signed adder to add these too signed digit? > Now I convert it to 2's complement,add, and convert it to signed digit. > But the overflow control seems not be a easy task. > BTW, I use verilog. > > Any suggestions will be appreciated! > Best regards, > Davy >Article: 86270
Well. European geography was never a US forte. Confusing Sweden with Switzerland is much worse than mixing up Finland and Sweden. Hell, for a few hundred years, before Napoleon, those two were actually together. In Europe, I have asked people whether they know the difference between Michigan and Minnesota, and I got a blank stare... Peter AlfkeArticle: 86271
Austin Lesea wrote: > All, > > Face it, Peter and I both are absolute true believers in on-line > shopping. And we believe that buying FPGAs should be no more painful > than buying a book at Amazon.com. > > Sure, if you want 25 of them, or if you need support and services, you > may not want to buy online, but rather through your local and helpful > distributor who will actually send the FAE to you to help (if needed). <snip> You might sell more than you think. One common issue with Distis, is many don't like to break SPQ's - so that places a quantize effect on availability. It means there will be both pilot run, and also run-rounding needs. Programmable logic is stocked much more poorly than generic microcontrollers, simply because the range changes so rapidly. TIP for Xilinx: Put the SPQ on the webstore (somewhere), so users can see at a glance if contacting the Disti is likely to be helpfull, or a waste of time... I just looked at my XC2C32 data sheet, plenty of order codes (19!), but not a single SPQ!... -jgArticle: 86272
My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one byte each clock period. What are the equations to inplement this data scrambler? Thanks.Article: 86273
Hi, Thank you for your help! But where can I get Verilog2001's tutorial or definition on this subject. Thanks! DavyArticle: 86274
What's so great about a 30-year old CPU ? Peter Alfke
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