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Hi, do you have changed the modelsim.ini before you started the simulation?Article: 86776
Dave, As can be expected, any FPGA's performance will vary based on the coding style, the application, and the use of device specific features. We use more than 100 designs from custoemrs to compare performance just for that reason. We also evaluate each design carefully to make sure that it is using the device resources appropriately (both for us, and our competitors). Xilinx claims the high road, both in superior performance, and superior density (size). We claim more than that, actually... A quick browse of the websites will provide you with more information than you can read in one lifetime. http://www.xilinx.com/products/virtex4/overview/performance.htm is a good review of V4, which illustrate how we beat all other FPGAs in EVERY category. In fact, some categories there is no competition at all (ie 10 Gb/s serial IOs, IBM PPC, and Ethernet MACs). Quite a claim (at first glance), but consistent with Xilinx values, we wouldn't make such a claim if it wasn't true, and backed by data, evaluation boards, white papers, applications notes, and customer testimonials. Superior in EVERY way, Virtex 4. Austin Dave wrote: > Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit > reprogrammable format? > > Their data sheet claims 450MHz PPC and 500MHz DSP. The -12 speed grade of > the XC4VFX40 or 60 devcies sound like they won't be available until next > year, though. > > I couldn't find definitive data in the Altera literature about the speed of > the Stratix II parts. Do these parts run at speeds approaching the Virtex 4 > parts? > > Does Lattice offer high-speed devices with built-in microprocessor, DSP, and > RAM support? It appears the EC family supports RAM at up to 200MHz. > > Thanks. > > Dave > >Article: 86777
In article <1120654853.854340.227610@z14g2000cwz.googlegroups.com>, Jon Beniston <jon@beniston.com> wrote: >> So a SII -3 is faster than a SII -5, and V4 -10 is slower than V4 -12. > >Do I detect a hint of NLP there? :) Xilinx used to do the same tihng. But when they were in danger (with the continued processing/development) of having a XC4000 - -1, they decided to switch the numbering scheme to "Higher is faster" with the Virtex line. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 86778
Nju Njoroge wrote: > Hi, > > I'm using ModelSim SE 6.0a with ISE 7.1 (SP 2) and EDK (SP 1). I get > the following error with the PPC SmartModel. > > # Loading work.ppc405_0_wrapper(structure) > # Loading C:/simlib/EDK_Lib/ppc405_v2_00_c/.ppc405_top(structure) > # Loading C:/simlib/unisim/.ppc405(ppc405_v) > # Loading C:/simlib/unisim/.ppc405_swift_bus(ppc405_swift_bus_v) > # Loading C:/simlib/unisim/.ppc405_swift(smartmodel) > # Loading c:\Modeltech_6.0a\win32/libsm.dll > # ** Error: Unable to read LMC SmartModel library file "** Fatal: > Foreign module requested halt. > # Time: 0 ps Iteration: 0 Instance: > /system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst > File: C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd > # FATAL ERROR while loading design > # Error loading design > # Error: Error loading design > > The VHDL file, > C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd, is > where it is supposed to be and it looks legit when I open it. Also, I > recently upgraded from EDK 6.3, in which the SmartModel worked well. In > the upgrade, I followed the usual set of procedures > (http://www.xilinx.com/ise/embedded/ps_ug.pdf, page 120). Additionally, > all the simulations were re-compiled for the new versions of ISE and > EDK. The smartmodel_wrappers.vhd does not appear to be your problem. The error message claims the problem is with the "LMC" library. This would probably be defined in your modelsim project file with a line like: libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so Have you made sure that the combination of the environment variable and the rest of the line points to the correct file?Article: 86779
ALuPin@web.de wrote:
> Question: What if the signal in the slow clock domain should also be
> one clock cycle high ?
Make a synchronizer and a
synchronous level change detector
on the fast clock.
-- Mike Treseler
Article: 86780Vladislav Muravin wrote: > No, this is not the best method. Actually, this not a good method at all. And since he didn't say why it is not a good method... If your clk_rd and clk_wr are asynchronous (you don't actually mention whether they are), then this method is guaranteed to corrupt the data. Let's look at why. You get a strobe_in and generate a fast_event and capture the data. These signals travel to the registers that make up slow_clock_process, each signal taking slightly different amounts of time due to routing. Some of the fast_column signals go faster than fast_event, and some go slower. A clk_rd event happens to occur in the time between when fast_event has arrived, but not all of the fast_column signals. If the clocks are truly asynchronous, this is guaranteed to happen occasionally. The fast_event causes slow_event to be captured, but only part of the slow data, because not all the fast data has arrived yet. On the next clk_wr, the fast process sees the slow_event flag and takes away fast_event. There are a number of possible solutions, but the best solution depends to a large extent on the characteristics of when the fast data arrives, and the relative clock speeds. > > > "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message > news:11cnn43fdchjqc8@corp.supernews.com... >> Hello group, >> >> I am attempting to get data (column_in) from a fast >> clock domain(clk_wr) to a slow clock domain(clk_rd). >> >> Is this the best method? >> >> fast_clock_process: process(clk_wr) >> begin >> if(clk_wr'event and clk_wr='1') then >> if( fast_event='1' and slow_event='1') then >> fast_event <= '0'; >> elsif( strobe_in='1' ) then >> fast_event <= '1'; >> fast_column <= column_in; >> end if; >> end if; >> end process; >> >> slow_clock_process: process(clk_rd) >> begin >> if(clk_rd'event and clk_rd='1') then >> slow_event <= '0'; >> if( fast_event='1' ) then >> slow_event <='1'; >> slow_column <= fast_column; >> end if; >> end if; >> end process; >>Article: 86781
schellho wrote: > A question for the Xilinx guru's out there: > > I am experimenting with the map -bp switch (map slice logic) in order > to make better use of device resources. > > I am constraining my outputs with IOB = TRUE so that the mapper maps > them to IOB flops. When I use the -bp switch, however, I have an output > flop that is mapped to a block RAM despite the IOB constraint. The > clk-to-out timing specification is unreachable so the map fails with an > error message. I have tried applying the IOB constraint in the verilog > and in the UCF file. > > Is there a way to force the mapper to ignore the -bp switch for certain > flops (other than creating and maintaining a mapping file), or am I > stuck with having to choose between IOB packed flops and block RAM > mapping? > > I am using ISE6.1i. > > Thanks in advance! > > Mark Hi Mark, Try assigning the same BLKNM attribute to the FF and Pad, or a LOC constraint on the FF if you already have an IO layout. These are both harder constraints than IOB = TRUE and should work. Another approach would be to specify the logic to be packed into BRAM using the file based system documented in Answer Record 15888. Regards, BretArticle: 86782
NLP stands for Neuro-Linguistic Programming... (I had to google that...) IT is interesting that despite this frenzy about top speed, most users always buy the (cheaper) slow speed grades... Makes you wonder what's so important. This reminds me of car advertising in Europe, where top speed used to be the big issue. "My fast 260 kmph BMW is better than your slow 255 kmph Mercedes !" Nowadays, the distinction is more about important issues, like the number of cupholders and foldable back seats... Peter AlfkeArticle: 86783
<00andiweb.de> schrieb im Newsbeitrag news:ee8f784.0@webx.sUN8CHnE... > Hi, > > did you call the exception init function (XExc_init() ) which assigns the vectortable to the evpr register? > > How does you c-code looks like? Yes I did. Here is how it lokks like !! XExc_Init(); // Register external interrupt handler XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT, (XExceptionHandler)PLB_DECODER_Intr_DefaultHandler,(void *)XPAR_PLB_DECODER_0_BASEADDR); // Enable PPC non-critical interrupts XExc_mEnableExceptions(XEXC_NON_CRITICAL); enable_decoder_interrupts(XPAR_PLB_DECODER_0_BASEADDR);Article: 86784
Thanks Rob. How do I tell Quartus that I want a specific pin to be open drain? Do I have to do something special? Or is it automatic and transparent to the user? Thanks, ErnieArticle: 86785
Since you have System ACE CF in your system that is the easiest way to load both bitstream and ELF file. Please read up in the EDK documentation how to generate an ACE file for your system. - Peter Andi wrote: > Hi, > > do you want to run the program out of sdram or out of the bram? What is the size of the c-code? Do you use the edk system as top level? Or do you integrate the edk system in your own top level? > > The tool flow from edk supports the mechanism to fit the c-code -> elf-file in the bram during the bitgen procedure. > > Then when the fpga is loaded the c-code starts directly.Article: 86786
ernie wrote:
> How do I tell Quartus that I want a specific pin to be open drain? Do
> I have to do something special? Or is it automatic and transparent to
> the user?
It will be inferred automatically from the code
if you write it as Sylvain suggested.
my_od_out <= '0' when my_od_sig = '0' else 'Z';
Picking the pin number for my_od_out
is best done with the Quartus GUI.
-- Mike Treseler
Article: 86787"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1120668551.532800.247620@g14g2000cwa.googlegroups.com... > IT is interesting that despite this frenzy about top speed, most users > always buy the (cheaper) slow speed grades... Makes you wonder what's > so important. "Geiz ist geil", a slogan heavily used in advertising of a big electronic market chain. ;-) > This reminds me of car advertising in Europe, where top speed used to > be the big issue. > "My fast 260 kmph BMW is better than your slow 255 kmph Mercedes !" > Nowadays, the distinction is more about important issues, like the > number of cupholders and foldable back seats... Even on the Autobahn here, most top ten cars are limited by electronic, not engine power. So all the BMW, Mercedes, Porsche easily reach 250 km/h, when the electronic suddenly decides, "That enough, dude". Regards FalkArticle: 86788
In article <3j2j7qFnsjmeU1@individual.net>, Falk Brunner <Falk.Brunner@gmx.de> wrote: >Even on the Autobahn here, most top ten cars are limited by electronic, not >engine power. So all the BMW, Mercedes, Porsche easily reach 250 km/h, when >the electronic suddenly decides, "That enough, dude". I know the BMW and Mercedes have the limiters, but I thought Porsche said "We ain't gentlemen, we aren't holding to the gentlemen's agreement" -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 86789
Thanks Mike, That helps a lot. I appreciate it! Cheers, ErnieArticle: 86790
Duane Clark wrote: > Nju Njoroge wrote: > > Hi, > > > > I'm using ModelSim SE 6.0a with ISE 7.1 (SP 2) and EDK (SP 1). I get > > the following error with the PPC SmartModel. > > > > # Loading work.ppc405_0_wrapper(structure) > > # Loading C:/simlib/EDK_Lib/ppc405_v2_00_c/.ppc405_top(structure) > > # Loading C:/simlib/unisim/.ppc405(ppc405_v) > > # Loading C:/simlib/unisim/.ppc405_swift_bus(ppc405_swift_bus_v) > > # Loading C:/simlib/unisim/.ppc405_swift(smartmodel) > > # Loading c:\Modeltech_6.0a\win32/libsm.dll > > # ** Error: Unable to read LMC SmartModel library file "** Fatal: > > Foreign module requested halt. > > # Time: 0 ps Iteration: 0 Instance: > > /system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst > > File: C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd > > # FATAL ERROR while loading design > > # Error loading design > > # Error: Error loading design > > > > The VHDL file, > > C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd, is > > where it is supposed to be and it looks legit when I open it. Also, I > > recently upgraded from EDK 6.3, in which the SmartModel worked well. In > > the upgrade, I followed the usual set of procedures > > (http://www.xilinx.com/ise/embedded/ps_ug.pdf, page 120). Additionally, > > all the simulations were re-compiled for the new versions of ISE and > > EDK. > > The smartmodel_wrappers.vhd does not appear to be your problem. The > error message claims the problem is with the "LMC" library. This would > probably be defined in your modelsim project file with a line like: > > libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so > > Have you made sure that the combination of the environment variable and > the rest of the line points to the correct file? Yes, I have these variables set appropriately (as instructed by the Platform Studio User Guide, page 120). In my modelsim.ini, I have: libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll where $LMC_HOME points to %XILINX%\smartmodel\nt\installed_nt. I did not change this configuration when upgrading from 6.3 to 7.1. In 6.3, this used to work, but it no longer does for 7.1.Article: 86791
Duane Clark wrote: > A clk_rd event happens to occur in the time between when fast_event has > arrived, but not all of the fast_column signals. If the clocks are truly > asynchronous, this is guaranteed to happen occasionally. The fast_event > causes slow_event to be captured, but only part of the slow data, > because not all the fast data has arrived yet. > Also, I should point out that since fast_event goes to all the slow side registers, it arrives at each individual register at different times, which is another source of asynchronous problems. There is a simple rule for situations where that can happen. If a control signal crossing a clock domain goes to multiple places, then it must go through a synchronizing flipflop first.Article: 86792
Well....
First, let me ask "why"? What's the logic functionality you are after?
Second, what you are doing is driving a net from two different processes,
which unacceptable by the synthesis tool.
try replacing two last processes into one as following:
always @(posedge clk or posedge b)
begin
if (b) c <= 1;
else c <= 0;
end
Vladislav
"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1120660339.335787.104570@g49g2000cwa.googlegroups.com...
> hello all,
> i have some doubt on the timing specs of FF set and rests.
> I wrote the folllowing code in verilog.
>
> always @(posedge clk)
> if (a == 0) b <= clk;
> else b <= 0;
>
> always @(posedge b)
> c <= 1;
>
> always @(posedge clk)
> c <= 0;
>
>
> my intention was to momentarly rest the 'c' and if 'a' is true then
> turn it back on. But the synthesizer gave error stating that
> simultanious assign ment is not possible. How can i achive this . i
> though like setting 'b' will take time thus the setting and resiing of
> 'c' will take place at differnt times. please give me comments on this
> issue.
>
Article: 86793"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag news:dah51p$1toj$1@agate.berkeley.edu... > In article <3j2j7qFnsjmeU1@individual.net>, > Falk Brunner <Falk.Brunner@gmx.de> wrote: > >Even on the Autobahn here, most top ten cars are limited by electronic, not > >engine power. So all the BMW, Mercedes, Porsche easily reach 250 km/h, when > >the electronic suddenly decides, "That enough, dude". > > I know the BMW and Mercedes have the limiters, but I thought Porsche > said "We ain't gentlemen, we aren't holding to the gentlemen's > agreement" Hmm, dont know at all. I don't own a Porsche. Yet . . . ;-) Regards FalkArticle: 86794
There was a thread with this subject line last September. Steve Knapp from Xilinx responded in the thread as follows: "I have a separate document that I will send you that includes all the relevant PCI 3.0 timing and which parameters that you can ignore if you're on the same PC board." I sent Steve an email last week but haven't gotten a response yet. If anyone has a copy of this document I'd much appreciate a copy. You can send it to bsefton@sandel.com. By the way, anybody running PCI in Spartan-3 at 66MHz? If so, which core are you using? Thanks, Bob S.Article: 86795
"stbcasa" <jtrabal@engin.umass.edu> writes: > I programmed it with the Opencores PCI core. The problem is that when > I plug it in the PCI slot of the computer the board turn on but the > computer doesn't and the computer work well without the PCI board > plugged. Any help? Capture a logic analyzer trace of the PCI bus and see if there's anything obvious going wrong? For instance, if the FPGA is driving signals when it shouldn't.Article: 86796
General things to check: 1. Does your design pin-out (.ucf file) match the board? 2. Does the design meet timing constraints for the bus speed of your computer? 3. Does the design load fully before PCI reset is released? This is often a sticking point. If you have a computer with a real reset button you can try to extend power-on reset time on the PCI bus. Otherwise you can minimize the FPGA load time by setting the CCLK rate as high as your PROM can go (in the configuration options). Also some motherboards have very short PCI reset times. If yours does, try a different system. Usually your best bet is a generic (e.g. ASUS - not Dell, IBM, Compaq) motherboard which usually has provisions for PCI reset switch and uses the "power good" output of the power supply to extend reset to a minimum of 250 milliseconds. The spec. for PCI is much shorter than this. Good luck, Gabor stbcasa wrote: > Hi everyone, > > I recently bought a Spartan II 2s200 PCI Board to use in a project. > I programmed it with the Opencores PCI core. The problem is that when > I plug it in the PCI slot of the computer the board turn on but the > computer doesn't and the computer work well without the PCI board > plugged. Any help? Thanks in advance. > > Regards; > > JorgeArticle: 86797
Hello, I am using VIIPro on ML310 board, and trying to port Linux on it. While I was trying to check out the Linux Kernel Source using BitKeeper(BK), it complained that BK is not free anymore. Is there anyone who knows where can I get the kernel source? The version that I need is v2.4.21. Thank you. Sewook WeeArticle: 86798
Hello! Currently I design FPGA design which will have pc104(ISA) bus. First at all I cannot find detailed ISA bus specification on Internet (I think for free). Also PCI to ISA bus bridge(national: CS5530) which is located on processor card (that I use) and generate PC104 timing does not contain any useful information in datasheet. I read on this forum a lot about ISA bus and I am little confused :)... if ISA bus signals are synchronized on ISA bus clock or are received and transmitted on (rising ?)edge of IOR# and IOW# signals. Also I am not sure If I need address latch signal (BALE) or I can latch address bus on IOR# and IOW# signals??? I see example: http://www.jacyltechnology.com/documents/AP002.pdf and it is all synchronized to PC104 clock signal...... Is it only special case?? In my design FPGA must act as slave on ISA bus and should support 8-bit and 16-bit I/O mode and DMA. So my question is where I can get detailed ISA bus specification (free :)) and how much this specification are depend on devices.. I think setup time, hold time... How is better to implement PC104 bus design sync or async? (Here I also have in mind possible problems with async design if i change FPGA) Thank you and regards, AMIRArticle: 86799
I don't know about "free", but I've always referred to "ISA and EISA Theory and Operation" by Ed Solari (Anabooks). This goes into considerable detail about real usage of the ISA bus including common mis-usage you may need to design around. It also contains EISA stuff which is more amusing than useful since PCI came out. Also by Ed Solari: "AT bus design: Compatible with IEEE P996, 8 and 16 bit ISA, E-ISA, and EISA design" Or this one by Ed Nisley "The Embedded PCs ISA Bus" amko wrote: > Hello! > > Currently I design FPGA design which will have pc104(ISA) bus. First at > all I cannot find detailed ISA bus specification on Internet (I think > for free). > Also PCI to ISA bus bridge(national: CS5530) which is located on > processor card (that I use) and generate PC104 timing does not contain > any useful information in datasheet. > > I read on this forum a lot about ISA bus and I am little confused :)... > if ISA bus signals are synchronized on ISA bus clock or are received > and transmitted on (rising ?)edge of IOR# and IOW# signals. > Also I am not sure If I need address latch signal (BALE) or I can latch > address bus on IOR# and IOW# signals??? > > > I see example: http://www.jacyltechnology.com/documents/AP002.pdf > and it is all synchronized to PC104 clock signal...... Is it only > special case?? > > In my design FPGA must act as slave on ISA bus and should support 8-bit > and 16-bit I/O mode and DMA. > > So my question is where I can get detailed ISA bus specification (free > :)) and how much this specification are depend on devices.. I think > setup time, hold time... > How is better to implement PC104 bus design sync or async? (Here I also > have in mind possible problems with async design if i change FPGA) > > Thank you and regards, > > AMIR
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