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On Wed, 2 Nov 2005 18:09:56 +0100, "Antti Lukats" <antti@openchip.org> wrote: > >the the PCI_LOGIC is undocumented FPGA primitive do you happen to have >addtional info about it? >is useable in non xilinx design by using hard macro wrapper around it or by >other means? > >Antti You may want to look here for some guidance (Tue, 20 Mar 2001) http://www.fpga-faq.com/archives/30000.html#30017 Surprisingly, I helped Kevin with this 3 years ago (Fri, 05 Apr 2002 ) http://www.fpga-faq.org/archives/41675.html#41698 and Kevin posted the following useful article that includes how to instantiate it, and the equation it implements: http://www.fpga-faq.org/archives/49775.html#49799 Damn, that www.FPGA-FAQ.org archive is good :-) Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 91301
"Mike Harrison" <mike@whitewing.co.uk> wrote in message
news:0uhim1pm7fn218r7fctq34a0qtaftfthr3@4ax.com...
> On 2 Nov 2005 14:20:17 -0800, "Peter Alfke" <peter@xilinx.com> wrote:
>
>>I promised an answer. The digging took a bit longer...
>>
>>The good news is that Xilinx has many thousands of S3e100 in TQ144, and
>>hundreds in vq100 packages, as well as many S3500 in several packages.
>>The bad new is that -today- these parts are still ES ("early silicon")
>>which distribution hates to touch, because the parts will become
>>obsolete very soon, once the production version becomes available.
>
> So why not put them in the web store....
Yeah!
You'd think ES parts would be prime candidates for the web store.
-- Ed
Article: 91302is there a way to use spartan3 dcm in active-hdl??Article: 91303
Xilinx has IP that you could evaluate (yes, it costs $, but I believe there is a free evaluation license which should be available.) We have used it in the past. (Both evaluation and $ license.) JTW <atarynka@gazeta.pl> wrote in message news:1130533636.244872.199890@g43g2000cwa.googlegroups.com... >I am looking for a program / a website / or anything that would allow > me to verify Reed Solomon code that my FPGA generates. Any help will be > greatly appreciated. > > Regards, > Wojciech ToczynskiArticle: 91304
I have implemented the lwip2.00a in the edk. Even though I specified the number of connections to be five, I can only have two open. ANyone know why? -- ---------------------------------------------- Posted with NewsLeecher v3.0 Final * Binary Usenet Leeching Made Easy * http://www.newsleecher.com/?usenet ----------------------------------------------Article: 91305
Hello, I'm trying to implement a bidirectional bus. I've declared the port as inout std_logic_vector, and the simulation shows only "UUU...". Any idea how I control the inout bus? read: process(clk2x) begin if rising_edge(clk2x) then if read_data = '1' then u_data_o <= ddr_dq; u_data_valid <= '1'; else u_data_o <= (others => '0'); u_data_valid <= '0'; end if; end if; end process read; write: process(clk2x) begin if falling_edge(clk2x) then if write_data = '1' then ddr_dq <= u_data_i; ddr_dqs <= clkstr; elsif read_data = '0' then ddr_dq <= (others => 'Z'); ddr_dqs <= 'Z'; end if; end if; end process write;Article: 91306
air_bits@yahoo.com wrote: > Rene Tschaggelar wrote: > >>Why are those guys so keen on C ? Suggesting >>compatibility with something while having least >>readability ? >> >>Rene > > > The description at the project page pretty much says it all: > > "C provides an excellent alternative to VHDL/Verilog for algorithmic > expression of tasks targeting FPGAs for reconfigurable computing." > > Project page at http://sourceforge.net/projects/fpga > > The object is to use FPGAs as computing engines, and less concerned > about how to describe circuits in an HDL for synthesis, as most > hardware designers would with VHDL or Verilog. VHDL and Verilog are the > rough equivalent of programming in assemenbly language, as the > implementation languages are directly expressing clocks, registers and > wires which adds a tremendous design state factor and skill level in > their use. > > Simplifed C to netlist compilers, such as FpgaC are attempting to hide > most of synthesis details, to ease the design burden for hardware > implementations of applications which have rich algorithmic complexity. > These applications range from doing network stacks in FPGAs for wire > speed performance at gigabit rates, to richly parallel algorithms such > as searching which are performance limited by the serial nature of > traditional CPU/Memory architectures. > > FPGAs in this decade are simply building blocks for high performance > computing, > not just a dense PLD to express hardware funtions for the logic > designer. Thanks. It is a pitty that C was chosen. The choice of C means some guys want to adhere to a standard, instead of flexibly adapt to the problems ahead. There should be a way to tell the compiler how quick I want to have an operation. Do I want a one cycle result with an enormous loockup table, do I want an N-digit multiply accumulate loop, do I want an NlogN solution or is it even less important. Is this being solved by a bunch of #pragma ? I'd be interested in the first floating point unit coming out of such a compiler. ReneArticle: 91307
Much as Peter has said.. Two methods.. one is to run a second timer and compare results... you can get to ppm accuracy then provided you reference is accurate enough. We do this to check serial clocks against a 25 ppm reference. Another is to use a simple RC filter on a couple of pins from the FPGA... note that it is important that the centre tap is connected by a C to the FPGA... so that if the FPGA remains inactive either high or low it will have no effect. I've also done this for a rough is the clock 16 MHz or not .. 8 Mhz turn on/off or there abouts .. not very accurate but it wasn't necessary. Simon "Peter Alfke" <peter@xilinx.com> wrote in message news:1130967597.327071.315120@g47g2000cwa.googlegroups.com... > This is easy if you have a continuously-running clock somewhere. > If you don't, you can easily detect when the clock starts for the first > time after power-on ( have the clock advance a 2-bit counter that you > had reset during power-on.) > But if you also want to detect if the clock has diappeared later on, > you need some timing element somewhere. > There is no mystery, it's all very logical, and your sharp Gallic > analytical mind will understand that... > Cheers > Peter Alfke, Xilinx >Article: 91308
HDL has a benefit that you can include abstract ideas in your FPGA. That's why HDL is better. I can also see the point of using C as a base language... But I can just imagine the latest windows.. instead of crashing once a week..it now crashes every mili second :-).. Poor software is still poor software... C isn't typed strong enough to use with out adding other tools, so it would be at the bottom of my list of recommended software. Also anything you create in C you will need to be able to verify. Failing to do so will only lead to hours and hair loss. Pascal would have been a better choice IMO. Simon "Eric Smith" <eric@brouhaha.com> wrote in message news:qhfyqelkvf.fsf@ruckus.brouhaha.com... > air_bits@yahoo.com writes: > > I can build them at a schematic level too, so why is any HDL better? > > I can even wire them out of TTL so why is using an FPGA better? > > Heck, I can even wire them out of diodes or vacumn tubes, .... > > > > So why waste people time bitching about others preferences, and the > > tools > > they use to implement them. If you like VHDL, certainly use it. > > I'm not the one claiming that any particular HDL is better than > another. But I'm trying to understand the hype about using C as > an HDL. Where is the actual benefit? >Article: 91309
Simon Peacock wrote: > HDL has a benefit that you can include abstract ideas in your FPGA. That's > why HDL is better. > > I can also see the point of using C as a base language... But I can just > imagine the latest windows.. instead of crashing once a week..it now crashes > every mili second :-).. Poor software is still poor software... C isn't > typed strong enough to use with out adding other tools, so it would be at > the bottom of my list of recommended software. Also anything you create in > C you will need to be able to verify. Failing to do so will only lead to > hours and hair loss. > > Pascal would have been a better choice IMO. Or Modula-2, or IEC 61131, ... or even better, something like : http://research.microsoft.com/fse/asml/ "AsmL is the Abstract State Machine Language. It is an executable specification language based on the theory of Abstract State Machines." -jgArticle: 91310
The mighty P125. It's on datasheets from 2002, but it's not on the website anymore. Anyone I've asked about it has told me they don't think that it was never made, certainly never for more than engineering samples. Then I read a paper where they claim to have "implemented on Xilinx Virtex-II Pro XC2VP125." I'm not so sure they did, but a quick search found the supplier below claiming that such chips were available, in both industrial and commercial grades. What's the deal? http://www.sierraic.com/pnresults.asp?part=XC2VP125&btnsearch=Search RobinArticle: 91311
<ncunha@gmail.com> wrote in message news:1130999863.735643.147920@g49g2000cwa.googlegroups.com... > Hello, > I'm trying to implement a bidirectional bus. I've declared the port as > inout std_logic_vector, and the simulation shows only "UUU...". Any > idea how I control the inout bus? > > read: process(clk2x) > begin > if rising_edge(clk2x) then > if read_data = '1' then > u_data_o <= ddr_dq; > u_data_valid <= '1'; > else > u_data_o <= (others => '0'); > u_data_valid <= '0'; > end if; > end if; > end process read; > > write: process(clk2x) > begin > if falling_edge(clk2x) then > if write_data = '1' then > ddr_dq <= u_data_i; > ddr_dqs <= clkstr; > elsif read_data = '0' then > ********** Are you sure you meant 'read_data' there? Else it only tristates when you're not reading. I think. HTH, Syms. ********** > > ddr_dq <= (others => 'Z'); > ddr_dqs <= 'Z'; > end if; > end if; > end process write; >Article: 91312
The inout buses are controlled in the same manner as in or out buses Make sure that the ddr_dq and u_data_i are getting values at the previous edge of when u expects the data in the inout bus.Article: 91313
Rene Tschaggelar (none@none.net) wrote: : Why are those guys so keen on C ? Suggesting : compatibility with something while having least : readability ? : Rene Oee might ask the same question about hardware engineers and Perl - why is this such a commonly used tool? I'd venture to guess that after being forced to accept VHDL or Verliog as the prime language, the idea of using Perl or C derivatives for hardware proramming doesn't seem so twisted. cdsArticle: 91314
Jim Granville wrote: > How about some examples, of some real applications, that can be coded > in either, and the resulting source examples, and the FPGA resource > mapping that results ? Here's a reference that was posted here a while ago and I'm just following up just now: "Survey of C-based Application Mapping Tools for Reconfigurable Computing" http://klabs.org/mapld05/program_sessions/session_c.html On p14, the C-based implementation performs faster than the VHDL implementation, despite the VHDL being developed after 'semester-long endeavor into algorithm?s parallelism'. They point to one of their own references that describes the implementation, but I guess you'd probably need to ask them for the resulting source. I guess Celoxica can probably give you some references to C-based examples too. Note that this sort of example is a more likely application in the HPC community rather than the hardware design community per se. MartinArticle: 91315
I think we have to accept that high-level languages are going to be the future for FPGAs. Not to say that HDLs will be replaced entirely, but they'll be largely supplanted by the HLLs. Algorithms are easier to verify: testing can be done using a software compiler and, providing you can trust your tools and hardware infrastructure, you shouldn't need to do extensive hardware testing of the implemented algorithm. Why should we want to know what's going on inside of the FPGA? Development time too is vastly reduced. I think C has been selected as the starting point for most HLL-to-HDL tools not because of its eminent suitability for the task, but because it decreases the pain in switching to the new tool. C syntax is familiar, it's a good jumping-on point. However, my experience in using these tools tells me that hopes for massive re-use of legacy code are still very much a pipe-dream. You will still have to understand the underlying hardware. You will have to understand the spatial, temporal and memory tradeoffs, and understand how to infer the pipelining and parallelism that is most suitable. What HLLs free you up from is the need to fiddle about with the timing on pipelines and other such details. I can change the mix of ALUs in a complex pipelined algorithm easily and painlessly. I don't need to go and manually re-time my pipeline to account for the changes (and so know I won't make an off-by-one error, introducing a fiendish bug). First generation tools are far from perfect, but they will see use because they significantly decrease development time. Your HLL-designed system may not be as efficient as the best possible VHDL design, but if it's good enough and you get to market months before the competition, you'll come out on top. Once the user base has been built up, I see the tools maturing and becoming less and less C-like. New languages will be demanded to better express parallelism and pipelining and to account for heterogeneous processing units and memory structures. Sorry if I've gone on a bit... :) RobinArticle: 91316
air_bits@yahoo.com schrieb: > Eric Smith wrote: > >>That doesn't explain *why* it's an excellent alternative. I can just >>as easily state that "C provides a terrible alternative to VHDL/Verilog >>for algorithmic expression of tasks targetting FPGAs for reconfigurable >>computing". So why is their statement any more accurate than mine? > > > There are probably a few hundred billion statements of C/C++ IP for > designs which > contain easily reusable code segments (IE cores) in nearly every > application > area. Probably a few trillion, when you include privately held IP in > addition > to what is on SourceForge and other open source depositories. Ok, you want to map GUIs, database engines, programming languages a.s.o. directly on an FPGA. Perhaps it makes sense to map 1% of all application to an FPGA.FPGAs offer massive parallelism, therefore only application/problems which utilize this parallelism should be implemented in FPGAs. They are all a kind of communication system or signal processing system. > > I suspect, the total IP coded in VHDL/Verilog is three to four orders > of magnitude less. May be, but it uses the hardware very efficiently > > So that is three reasons why C can be an excellent althernative for > reconfigurable computing projects, and for the home hobbyist that > already knows C and would like to use an FPGA for a reconfigurable > platform for their robotic or other project. Never, since most of them think in sequential algorithms and don't understand the advantages of hardware. Bye TomArticle: 91317
Hallo, I would have a suggestion about. The job consist in: developing a microprocessor based system for data acquisition. I have begun working with fpga about 1 year ago. I have developed some opb peripherals and a microcontroller based on microblaze. How much could I ask as monthly wage? Many Thanks MarcoArticle: 91318
>Never, since most of them think in sequential algorithms and don't >understand the advantages of hardware. What are you saying? That people who don't understand hardware don't make good hardware designs? Why would that make VHDL better than a HLL-to-VHDL tool? I could just as easily say that people who've never heard of algorithms don't understand the advantages of a microprocessor, therefore assembler is better than C. It's a non sequitur...Article: 91319
Thomas Reinemann wrote:
> FPGAs offer massive parallelism, therefore only
> application/problems which utilize this parallelism should be
> implemented in FPGAs. They are all a kind of communication system or
> signal processing system.
All? Perhaps you should read these for other high-performance computing
applications that can be accelerated using FPGAs:
@MISC{compton00reconfigurable,
author = {K. Compton and S. Hauck},
title = {Reconfigurable Computing: A Survey of Systems and Software},
year = {2000},
text = {K. Compton, S. Hauck, Reconfigurable Computing: A Survey
of Systems and Software, submitted to ACM Computing Surveys, 2000.},
url = {http://citeseer.nj.nec.com/compton00reconfigurable.html},
}
@ARTICLE{hauck98roles,
author = {Scott Hauck},
title = {{The Roles of FPGAs in Reprogrammable Systems}},
journal = {Proceedings of the IEEE},
year = {1998},
volume = {86},
number = {4},
pages = {615--638},
month = {Apr},
url = {http://citeseer.nj.nec.com/hauck98roles.html},
}
>> I suspect, the total IP coded in VHDL/Verilog is three to four orders
>> of magnitude less.
> May be, but it uses the hardware very efficiently
Isn't that what people said about assembly language? And GOTO statements?
>> So that is three reasons why C can be an excellent althernative for
>> reconfigurable computing projects, and for the home hobbyist that
>> already knows C and would like to use an FPGA for a reconfigurable
>> platform for their robotic or other project.
> Never, since most of them think in sequential algorithms and don't
> understand the advantages of hardware.
Yawn. I wonder when people from traditional hardware design backgrounds
will get over this kind of attitude.
So what if some hobbyists don't 'get' it at first? People aren't born
hardware designers, nor software programmers. Are you really saying you've
never made any mistakes while you were learning?
It's not like using a HLL for FPGA design is only useful for hobbyists
anyway.
Martin
Article: 91320You have not given anywhere near enough info to even hazard a guess. Where you live, where the jobs is, your education, experience, .... are all HUGE factors in this. "Marco" <marcotoschi@nospam.it> wrote in message news:dkcud4$r16$1@nnrp.ngi.it... > Hallo, > I would have a suggestion about. > > The job consist in: developing a microprocessor based system for data > acquisition. > > I have begun working with fpga about 1 year ago. I have developed some opb > peripherals and a microcontroller based on microblaze. > > How much could I ask as monthly wage? > > Many Thanks > Marco >Article: 91321
I live in Italy. I've a Laurea degree (equivalent to a Master of Science degree) in Electronic Engineering with specialization in analog and digital integrated circuits. I have worked for about 1 year to develop a microcontroller based on microblaze. It is a part of a test bench for industrial electric motors, pump and engines. I have developed the electronic system. A mechanical engineer has developed the mechanical parts. I have experience in developing opb peripherals, interfacing them to a complete system. I hope that these informations are enough. MarcoArticle: 91322
Its my understanding that Xilinx paper launched the 2vp125 in response to a large Altera part. A customer never materialized with a big enough order to justify fabbing the monster, but the tools did (and perhaps still do) support the part. The paper you are refering to probably just produced a bitstream for the part. If you'll notice, the website you refer to does not list any quantities for the 2vp125 as they do for the 100 part. StephenArticle: 91323
Thanks, That more or less tallies with what I thought. I think the people who wrote the paper I'm alluding to wanted to slightly obscure the fact that they had only taken it so far as simulation, and not actually implemented it in hardware. And their plan would have worked perfectly had it not been for their targeting of a non-existent part :-) Cheers, RobinArticle: 91324
Hi, there are a couple of general control signals for the DCM, i.e. STATUS[7:0], one of which STATUS[1], indicates if CLKIN is stopped. I've never used this myself and I'm not sure if it will be of help to you but there's more details in the V2Pro platform handbook should you need it. Good luck, Ben. seb_tech_fr wrote: > Hi ! > I need advice to build a very small firmware which will detect if a > clock signal is active or not. > Indeed, My FPGA (V2Pro) is connected to other devices/boards and > receives a clock signal. However, this clock signal is not active at > the begining and I would like to inform other devices/boards if clock > signal is ready or not. > > My question is : How can I do to know if a signal clock is active? > > I thought to implement a counter driven by this clock. But this will > not ensure me that signal is a clock at X MHz. > > May I use a DCM, and look at the LOCKED signal? > > All ideas are welcomed. > > > Thank you. >
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